2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "main/shaderimage.h"
27 #include "brw_fs_surface_builder.h"
29 #include "brw_program.h"
32 using namespace brw::surface_access
;
35 fs_visitor::emit_nir_code()
37 /* emit the arrays used for inputs and outputs - load/store intrinsics will
38 * be converted to reads/writes of these arrays
43 nir_emit_system_values();
45 /* get the main function and emit it */
46 nir_foreach_overload(nir
, overload
) {
47 assert(strcmp(overload
->function
->name
, "main") == 0);
48 assert(overload
->impl
);
49 nir_emit_impl(overload
->impl
);
54 fs_visitor::nir_setup_inputs()
56 if (stage
!= MESA_SHADER_FRAGMENT
)
59 nir_inputs
= bld
.vgrf(BRW_REGISTER_TYPE_F
, nir
->num_inputs
);
61 nir_foreach_variable(var
, &nir
->inputs
) {
62 fs_reg input
= offset(nir_inputs
, bld
, var
->data
.driver_location
);
65 if (var
->data
.location
== VARYING_SLOT_POS
) {
66 reg
= *emit_fragcoord_interpolation(var
->data
.pixel_center_integer
,
67 var
->data
.origin_upper_left
);
68 emit_percomp(bld
, fs_inst(BRW_OPCODE_MOV
, bld
.dispatch_width(),
70 } else if (var
->data
.location
== VARYING_SLOT_LAYER
) {
71 struct brw_reg reg
= suboffset(interp_reg(VARYING_SLOT_LAYER
, 1), 3);
72 reg
.type
= BRW_REGISTER_TYPE_D
;
73 bld
.emit(FS_OPCODE_CINTERP
, retype(input
, BRW_REGISTER_TYPE_D
), reg
);
74 } else if (var
->data
.location
== VARYING_SLOT_VIEWPORT
) {
75 struct brw_reg reg
= suboffset(interp_reg(VARYING_SLOT_VIEWPORT
, 2), 3);
76 reg
.type
= BRW_REGISTER_TYPE_D
;
77 bld
.emit(FS_OPCODE_CINTERP
, retype(input
, BRW_REGISTER_TYPE_D
), reg
);
79 int location
= var
->data
.location
;
80 emit_general_interpolation(&input
, var
->name
, var
->type
,
81 (glsl_interp_qualifier
) var
->data
.interpolation
,
82 &location
, var
->data
.centroid
,
89 fs_visitor::nir_setup_single_output_varying(fs_reg
*reg
,
90 const glsl_type
*type
,
93 if (type
->is_array() || type
->is_matrix()) {
94 const struct glsl_type
*elem_type
= glsl_get_array_element(type
);
95 const unsigned length
= glsl_get_length(type
);
97 for (unsigned i
= 0; i
< length
; i
++) {
98 nir_setup_single_output_varying(reg
, elem_type
, location
);
100 } else if (type
->is_record()) {
101 for (unsigned i
= 0; i
< type
->length
; i
++) {
102 const struct glsl_type
*field_type
= type
->fields
.structure
[i
].type
;
103 nir_setup_single_output_varying(reg
, field_type
, location
);
106 assert(type
->is_scalar() || type
->is_vector());
107 this->outputs
[*location
] = *reg
;
108 this->output_components
[*location
] = type
->vector_elements
;
109 *reg
= offset(*reg
, bld
, 4);
115 fs_visitor::nir_setup_outputs()
117 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
119 nir_outputs
= bld
.vgrf(BRW_REGISTER_TYPE_F
, nir
->num_outputs
);
121 nir_foreach_variable(var
, &nir
->outputs
) {
122 fs_reg reg
= offset(nir_outputs
, bld
, var
->data
.driver_location
);
125 case MESA_SHADER_VERTEX
:
126 case MESA_SHADER_GEOMETRY
: {
127 unsigned location
= var
->data
.location
;
128 nir_setup_single_output_varying(®
, var
->type
, &location
);
131 case MESA_SHADER_FRAGMENT
:
132 if (var
->data
.index
> 0) {
133 assert(var
->data
.location
== FRAG_RESULT_DATA0
);
134 assert(var
->data
.index
== 1);
135 this->dual_src_output
= reg
;
136 this->do_dual_src
= true;
137 } else if (var
->data
.location
== FRAG_RESULT_COLOR
) {
138 /* Writing gl_FragColor outputs to all color regions. */
139 for (unsigned int i
= 0; i
< MAX2(key
->nr_color_regions
, 1); i
++) {
140 this->outputs
[i
] = reg
;
141 this->output_components
[i
] = 4;
143 } else if (var
->data
.location
== FRAG_RESULT_DEPTH
) {
144 this->frag_depth
= reg
;
145 } else if (var
->data
.location
== FRAG_RESULT_STENCIL
) {
146 this->frag_stencil
= reg
;
147 } else if (var
->data
.location
== FRAG_RESULT_SAMPLE_MASK
) {
148 this->sample_mask
= reg
;
150 int vector_elements
= var
->type
->without_array()->vector_elements
;
152 /* gl_FragData or a user-defined FS output */
153 assert(var
->data
.location
>= FRAG_RESULT_DATA0
&&
154 var
->data
.location
< FRAG_RESULT_DATA0
+BRW_MAX_DRAW_BUFFERS
);
156 /* General color output. */
157 for (unsigned int i
= 0; i
< MAX2(1, var
->type
->length
); i
++) {
158 int output
= var
->data
.location
- FRAG_RESULT_DATA0
+ i
;
159 this->outputs
[output
] = offset(reg
, bld
, vector_elements
* i
);
160 this->output_components
[output
] = vector_elements
;
165 unreachable("unhandled shader stage");
171 fs_visitor::nir_setup_uniforms()
173 if (dispatch_width
!= 8)
176 uniforms
= nir
->num_uniforms
/ 4;
178 nir_foreach_variable(var
, &nir
->uniforms
) {
179 /* UBO's and atomics don't take up space in the uniform file */
180 if (var
->interface_type
!= NULL
|| var
->type
->contains_atomic())
183 if (type_size_scalar(var
->type
) > 0)
184 param_size
[var
->data
.driver_location
/ 4] = type_size_scalar(var
->type
);
189 emit_system_values_block(nir_block
*block
, void *void_visitor
)
191 fs_visitor
*v
= (fs_visitor
*)void_visitor
;
194 nir_foreach_instr(block
, instr
) {
195 if (instr
->type
!= nir_instr_type_intrinsic
)
198 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
199 switch (intrin
->intrinsic
) {
200 case nir_intrinsic_load_vertex_id
:
201 unreachable("should be lowered by lower_vertex_id().");
203 case nir_intrinsic_load_vertex_id_zero_base
:
204 assert(v
->stage
== MESA_SHADER_VERTEX
);
205 reg
= &v
->nir_system_values
[SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
];
206 if (reg
->file
== BAD_FILE
)
207 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
);
210 case nir_intrinsic_load_base_vertex
:
211 assert(v
->stage
== MESA_SHADER_VERTEX
);
212 reg
= &v
->nir_system_values
[SYSTEM_VALUE_BASE_VERTEX
];
213 if (reg
->file
== BAD_FILE
)
214 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_BASE_VERTEX
);
217 case nir_intrinsic_load_instance_id
:
218 assert(v
->stage
== MESA_SHADER_VERTEX
);
219 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INSTANCE_ID
];
220 if (reg
->file
== BAD_FILE
)
221 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_INSTANCE_ID
);
224 case nir_intrinsic_load_invocation_id
:
225 assert(v
->stage
== MESA_SHADER_GEOMETRY
);
226 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
227 if (reg
->file
== BAD_FILE
) {
228 const fs_builder abld
= v
->bld
.annotate("gl_InvocationID", NULL
);
229 fs_reg
g1(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
230 fs_reg iid
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
231 abld
.SHR(iid
, g1
, brw_imm_ud(27u));
236 case nir_intrinsic_load_sample_pos
:
237 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
238 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
239 if (reg
->file
== BAD_FILE
)
240 *reg
= *v
->emit_samplepos_setup();
243 case nir_intrinsic_load_sample_id
:
244 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
245 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
246 if (reg
->file
== BAD_FILE
)
247 *reg
= *v
->emit_sampleid_setup();
250 case nir_intrinsic_load_sample_mask_in
:
251 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
252 assert(v
->devinfo
->gen
>= 7);
253 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
254 if (reg
->file
== BAD_FILE
)
255 *reg
= fs_reg(retype(brw_vec8_grf(v
->payload
.sample_mask_in_reg
, 0),
256 BRW_REGISTER_TYPE_D
));
259 case nir_intrinsic_load_local_invocation_id
:
260 assert(v
->stage
== MESA_SHADER_COMPUTE
);
261 reg
= &v
->nir_system_values
[SYSTEM_VALUE_LOCAL_INVOCATION_ID
];
262 if (reg
->file
== BAD_FILE
)
263 *reg
= *v
->emit_cs_local_invocation_id_setup();
266 case nir_intrinsic_load_work_group_id
:
267 assert(v
->stage
== MESA_SHADER_COMPUTE
);
268 reg
= &v
->nir_system_values
[SYSTEM_VALUE_WORK_GROUP_ID
];
269 if (reg
->file
== BAD_FILE
)
270 *reg
= *v
->emit_cs_work_group_id_setup();
273 case nir_intrinsic_load_helper_invocation
:
274 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
275 reg
= &v
->nir_system_values
[SYSTEM_VALUE_HELPER_INVOCATION
];
276 if (reg
->file
== BAD_FILE
) {
277 const fs_builder abld
=
278 v
->bld
.annotate("gl_HelperInvocation", NULL
);
280 /* On Gen6+ (gl_HelperInvocation is only exposed on Gen7+) the
281 * pixel mask is in g1.7 of the thread payload.
283 * We move the per-channel pixel enable bit to the low bit of each
284 * channel by shifting the byte containing the pixel mask by the
285 * vector immediate 0x76543210UV.
287 * The region of <1,8,0> reads only 1 byte (the pixel masks for
288 * subspans 0 and 1) in SIMD8 and an additional byte (the pixel
289 * masks for 2 and 3) in SIMD16.
291 fs_reg shifted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
293 stride(byte_offset(retype(brw_vec1_grf(1, 0),
294 BRW_REGISTER_TYPE_UB
), 28),
296 brw_imm_uv(0x76543210));
298 /* A set bit in the pixel mask means the channel is enabled, but
299 * that is the opposite of gl_HelperInvocation so we need to invert
302 * The negate source-modifier bit of logical instructions on Gen8+
303 * performs 1's complement negation, so we can use that instead of
306 fs_reg inverted
= negate(shifted
);
307 if (v
->devinfo
->gen
< 8) {
308 inverted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
309 abld
.NOT(inverted
, shifted
);
312 /* We then resolve the 0/1 result to 0/~0 boolean values by ANDing
313 * with 1 and negating.
315 fs_reg anded
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
316 abld
.AND(anded
, inverted
, brw_imm_uw(1));
318 fs_reg dst
= abld
.vgrf(BRW_REGISTER_TYPE_D
, 1);
319 abld
.MOV(dst
, negate(retype(anded
, BRW_REGISTER_TYPE_D
)));
333 fs_visitor::nir_emit_system_values()
335 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
336 for (unsigned i
= 0; i
< SYSTEM_VALUE_MAX
; i
++) {
337 nir_system_values
[i
] = fs_reg();
340 nir_foreach_overload(nir
, overload
) {
341 assert(strcmp(overload
->function
->name
, "main") == 0);
342 assert(overload
->impl
);
343 nir_foreach_block(overload
->impl
, emit_system_values_block
, this);
348 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
350 nir_locals
= ralloc_array(mem_ctx
, fs_reg
, impl
->reg_alloc
);
351 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
352 nir_locals
[i
] = fs_reg();
355 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
356 unsigned array_elems
=
357 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
358 unsigned size
= array_elems
* reg
->num_components
;
359 nir_locals
[reg
->index
] = bld
.vgrf(BRW_REGISTER_TYPE_F
, size
);
362 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
365 nir_emit_cf_list(&impl
->body
);
369 fs_visitor::nir_emit_cf_list(exec_list
*list
)
371 exec_list_validate(list
);
372 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
373 switch (node
->type
) {
375 nir_emit_if(nir_cf_node_as_if(node
));
378 case nir_cf_node_loop
:
379 nir_emit_loop(nir_cf_node_as_loop(node
));
382 case nir_cf_node_block
:
383 nir_emit_block(nir_cf_node_as_block(node
));
387 unreachable("Invalid CFG node block");
393 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
395 /* first, put the condition into f0 */
396 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
397 retype(get_nir_src(if_stmt
->condition
),
398 BRW_REGISTER_TYPE_D
));
399 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
401 bld
.IF(BRW_PREDICATE_NORMAL
);
403 nir_emit_cf_list(&if_stmt
->then_list
);
405 /* note: if the else is empty, dead CF elimination will remove it */
406 bld
.emit(BRW_OPCODE_ELSE
);
408 nir_emit_cf_list(&if_stmt
->else_list
);
410 bld
.emit(BRW_OPCODE_ENDIF
);
414 fs_visitor::nir_emit_loop(nir_loop
*loop
)
416 bld
.emit(BRW_OPCODE_DO
);
418 nir_emit_cf_list(&loop
->body
);
420 bld
.emit(BRW_OPCODE_WHILE
);
424 fs_visitor::nir_emit_block(nir_block
*block
)
426 nir_foreach_instr(block
, instr
) {
427 nir_emit_instr(instr
);
432 fs_visitor::nir_emit_instr(nir_instr
*instr
)
434 const fs_builder abld
= bld
.annotate(NULL
, instr
);
436 switch (instr
->type
) {
437 case nir_instr_type_alu
:
438 nir_emit_alu(abld
, nir_instr_as_alu(instr
));
441 case nir_instr_type_intrinsic
:
443 case MESA_SHADER_VERTEX
:
444 nir_emit_vs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
446 case MESA_SHADER_GEOMETRY
:
447 nir_emit_gs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
449 case MESA_SHADER_FRAGMENT
:
450 nir_emit_fs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
452 case MESA_SHADER_COMPUTE
:
453 nir_emit_cs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
456 unreachable("unsupported shader stage");
460 case nir_instr_type_tex
:
461 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
464 case nir_instr_type_load_const
:
465 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
468 case nir_instr_type_ssa_undef
:
469 nir_emit_undef(abld
, nir_instr_as_ssa_undef(instr
));
472 case nir_instr_type_jump
:
473 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
477 unreachable("unknown instruction type");
482 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
483 const fs_reg
&result
)
485 if (!instr
->src
[0].src
.is_ssa
||
486 instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_intrinsic
)
489 nir_intrinsic_instr
*src0
=
490 nir_instr_as_intrinsic(instr
->src
[0].src
.ssa
->parent_instr
);
492 if (src0
->intrinsic
!= nir_intrinsic_load_front_face
)
495 nir_const_value
*value1
= nir_src_as_const_value(instr
->src
[1].src
);
496 if (!value1
|| fabsf(value1
->f
[0]) != 1.0f
)
499 nir_const_value
*value2
= nir_src_as_const_value(instr
->src
[2].src
);
500 if (!value2
|| fabsf(value2
->f
[0]) != 1.0f
)
503 fs_reg tmp
= vgrf(glsl_type::int_type
);
505 if (devinfo
->gen
>= 6) {
506 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
507 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
509 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
511 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
512 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
514 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
516 * This negation looks like it's safe in practice, because bits 0:4 will
517 * surely be TRIANGLES
520 if (value1
->f
[0] == -1.0f
) {
524 tmp
.type
= BRW_REGISTER_TYPE_W
;
525 tmp
.subreg_offset
= 2;
528 bld
.OR(tmp
, g0
, brw_imm_uw(0x3f80));
530 tmp
.type
= BRW_REGISTER_TYPE_D
;
531 tmp
.subreg_offset
= 0;
534 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
535 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
537 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
539 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
540 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
542 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
544 * This negation looks like it's safe in practice, because bits 0:4 will
545 * surely be TRIANGLES
548 if (value1
->f
[0] == -1.0f
) {
552 bld
.OR(tmp
, g1_6
, brw_imm_d(0x3f800000));
554 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, brw_imm_d(0xbf800000));
560 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
)
562 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
565 fs_reg result
= get_nir_dest(instr
->dest
.dest
);
566 result
.type
= brw_type_for_nir_type(nir_op_infos
[instr
->op
].output_type
);
569 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
570 op
[i
] = get_nir_src(instr
->src
[i
].src
);
571 op
[i
].type
= brw_type_for_nir_type(nir_op_infos
[instr
->op
].input_types
[i
]);
572 op
[i
].abs
= instr
->src
[i
].abs
;
573 op
[i
].negate
= instr
->src
[i
].negate
;
576 /* We get a bunch of mov's out of the from_ssa pass and they may still
577 * be vectorized. We'll handle them as a special-case. We'll also
578 * handle vecN here because it's basically the same thing.
586 fs_reg temp
= result
;
587 bool need_extra_copy
= false;
588 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
589 if (!instr
->src
[i
].src
.is_ssa
&&
590 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
591 need_extra_copy
= true;
592 temp
= bld
.vgrf(result
.type
, 4);
597 for (unsigned i
= 0; i
< 4; i
++) {
598 if (!(instr
->dest
.write_mask
& (1 << i
)))
601 if (instr
->op
== nir_op_imov
|| instr
->op
== nir_op_fmov
) {
602 inst
= bld
.MOV(offset(temp
, bld
, i
),
603 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
605 inst
= bld
.MOV(offset(temp
, bld
, i
),
606 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
608 inst
->saturate
= instr
->dest
.saturate
;
611 /* In this case the source and destination registers were the same,
612 * so we need to insert an extra set of moves in order to deal with
615 if (need_extra_copy
) {
616 for (unsigned i
= 0; i
< 4; i
++) {
617 if (!(instr
->dest
.write_mask
& (1 << i
)))
620 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
629 /* At this point, we have dealt with any instruction that operates on
630 * more than a single channel. Therefore, we can just adjust the source
631 * and destination registers for that channel and emit the instruction.
633 unsigned channel
= 0;
634 if (nir_op_infos
[instr
->op
].output_size
== 0) {
635 /* Since NIR is doing the scalarizing for us, we should only ever see
636 * vectorized operations with a single channel.
638 assert(_mesa_bitcount(instr
->dest
.write_mask
) == 1);
639 channel
= ffs(instr
->dest
.write_mask
) - 1;
641 result
= offset(result
, bld
, channel
);
644 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
645 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
646 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
652 inst
= bld
.MOV(result
, op
[0]);
653 inst
->saturate
= instr
->dest
.saturate
;
658 bld
.MOV(result
, op
[0]);
662 /* AND(val, 0x80000000) gives the sign bit.
664 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
667 bld
.CMP(bld
.null_reg_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
669 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
670 op
[0].type
= BRW_REGISTER_TYPE_UD
;
671 result
.type
= BRW_REGISTER_TYPE_UD
;
672 bld
.AND(result_int
, op
[0], brw_imm_ud(0x80000000u
));
674 inst
= bld
.OR(result_int
, result_int
, brw_imm_ud(0x3f800000u
));
675 inst
->predicate
= BRW_PREDICATE_NORMAL
;
676 if (instr
->dest
.saturate
) {
677 inst
= bld
.MOV(result
, result
);
678 inst
->saturate
= true;
684 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
685 * -> non-negative val generates 0x00000000.
686 * Predicated OR sets 1 if val is positive.
688 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_G
);
689 bld
.ASR(result
, op
[0], brw_imm_d(31));
690 inst
= bld
.OR(result
, result
, brw_imm_d(1));
691 inst
->predicate
= BRW_PREDICATE_NORMAL
;
695 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
696 inst
->saturate
= instr
->dest
.saturate
;
700 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
701 inst
->saturate
= instr
->dest
.saturate
;
705 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
706 inst
->saturate
= instr
->dest
.saturate
;
710 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
711 inst
->saturate
= instr
->dest
.saturate
;
715 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
716 inst
->saturate
= instr
->dest
.saturate
;
720 if (fs_key
->high_quality_derivatives
) {
721 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
723 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
725 inst
->saturate
= instr
->dest
.saturate
;
727 case nir_op_fddx_fine
:
728 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
729 inst
->saturate
= instr
->dest
.saturate
;
731 case nir_op_fddx_coarse
:
732 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
733 inst
->saturate
= instr
->dest
.saturate
;
736 if (fs_key
->high_quality_derivatives
) {
737 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0],
738 brw_imm_d(fs_key
->render_to_fbo
));
740 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0],
741 brw_imm_d(fs_key
->render_to_fbo
));
743 inst
->saturate
= instr
->dest
.saturate
;
745 case nir_op_fddy_fine
:
746 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0],
747 brw_imm_d(fs_key
->render_to_fbo
));
748 inst
->saturate
= instr
->dest
.saturate
;
750 case nir_op_fddy_coarse
:
751 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0],
752 brw_imm_d(fs_key
->render_to_fbo
));
753 inst
->saturate
= instr
->dest
.saturate
;
758 inst
= bld
.ADD(result
, op
[0], op
[1]);
759 inst
->saturate
= instr
->dest
.saturate
;
763 inst
= bld
.MUL(result
, op
[0], op
[1]);
764 inst
->saturate
= instr
->dest
.saturate
;
768 bld
.MUL(result
, op
[0], op
[1]);
771 case nir_op_imul_high
:
772 case nir_op_umul_high
:
773 bld
.emit(SHADER_OPCODE_MULH
, result
, op
[0], op
[1]);
778 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
781 case nir_op_uadd_carry
:
782 unreachable("Should have been lowered by carry_to_arith().");
784 case nir_op_usub_borrow
:
785 unreachable("Should have been lowered by borrow_to_arith().");
788 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
794 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
800 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
805 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_Z
);
810 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_NZ
);
814 if (devinfo
->gen
>= 8) {
815 op
[0] = resolve_source_modifiers(op
[0]);
817 bld
.NOT(result
, op
[0]);
820 if (devinfo
->gen
>= 8) {
821 op
[0] = resolve_source_modifiers(op
[0]);
822 op
[1] = resolve_source_modifiers(op
[1]);
824 bld
.XOR(result
, op
[0], op
[1]);
827 if (devinfo
->gen
>= 8) {
828 op
[0] = resolve_source_modifiers(op
[0]);
829 op
[1] = resolve_source_modifiers(op
[1]);
831 bld
.OR(result
, op
[0], op
[1]);
834 if (devinfo
->gen
>= 8) {
835 op
[0] = resolve_source_modifiers(op
[0]);
836 op
[1] = resolve_source_modifiers(op
[1]);
838 bld
.AND(result
, op
[0], op
[1]);
850 case nir_op_ball_fequal2
:
851 case nir_op_ball_iequal2
:
852 case nir_op_ball_fequal3
:
853 case nir_op_ball_iequal3
:
854 case nir_op_ball_fequal4
:
855 case nir_op_ball_iequal4
:
856 case nir_op_bany_fnequal2
:
857 case nir_op_bany_inequal2
:
858 case nir_op_bany_fnequal3
:
859 case nir_op_bany_inequal3
:
860 case nir_op_bany_fnequal4
:
861 case nir_op_bany_inequal4
:
862 unreachable("Lowered by nir_lower_alu_reductions");
864 case nir_op_fnoise1_1
:
865 case nir_op_fnoise1_2
:
866 case nir_op_fnoise1_3
:
867 case nir_op_fnoise1_4
:
868 case nir_op_fnoise2_1
:
869 case nir_op_fnoise2_2
:
870 case nir_op_fnoise2_3
:
871 case nir_op_fnoise2_4
:
872 case nir_op_fnoise3_1
:
873 case nir_op_fnoise3_2
:
874 case nir_op_fnoise3_3
:
875 case nir_op_fnoise3_4
:
876 case nir_op_fnoise4_1
:
877 case nir_op_fnoise4_2
:
878 case nir_op_fnoise4_3
:
879 case nir_op_fnoise4_4
:
880 unreachable("not reached: should be handled by lower_noise");
883 unreachable("not reached: should be handled by ldexp_to_arith()");
886 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
887 inst
->saturate
= instr
->dest
.saturate
;
891 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
892 inst
->saturate
= instr
->dest
.saturate
;
897 bld
.MOV(result
, negate(op
[0]));
901 bld
.CMP(result
, op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
904 bld
.CMP(result
, op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
908 inst
= bld
.RNDZ(result
, op
[0]);
909 inst
->saturate
= instr
->dest
.saturate
;
913 op
[0].negate
= !op
[0].negate
;
914 fs_reg temp
= vgrf(glsl_type::float_type
);
915 bld
.RNDD(temp
, op
[0]);
917 inst
= bld
.MOV(result
, temp
);
918 inst
->saturate
= instr
->dest
.saturate
;
922 inst
= bld
.RNDD(result
, op
[0]);
923 inst
->saturate
= instr
->dest
.saturate
;
926 inst
= bld
.FRC(result
, op
[0]);
927 inst
->saturate
= instr
->dest
.saturate
;
929 case nir_op_fround_even
:
930 inst
= bld
.RNDE(result
, op
[0]);
931 inst
->saturate
= instr
->dest
.saturate
;
937 if (devinfo
->gen
>= 6) {
938 inst
= bld
.emit(BRW_OPCODE_SEL
, result
, op
[0], op
[1]);
939 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
941 bld
.CMP(bld
.null_reg_d(), op
[0], op
[1], BRW_CONDITIONAL_L
);
942 inst
= bld
.SEL(result
, op
[0], op
[1]);
943 inst
->predicate
= BRW_PREDICATE_NORMAL
;
945 inst
->saturate
= instr
->dest
.saturate
;
951 if (devinfo
->gen
>= 6) {
952 inst
= bld
.emit(BRW_OPCODE_SEL
, result
, op
[0], op
[1]);
953 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
955 bld
.CMP(bld
.null_reg_d(), op
[0], op
[1], BRW_CONDITIONAL_GE
);
956 inst
= bld
.SEL(result
, op
[0], op
[1]);
957 inst
->predicate
= BRW_PREDICATE_NORMAL
;
959 inst
->saturate
= instr
->dest
.saturate
;
962 case nir_op_pack_snorm_2x16
:
963 case nir_op_pack_snorm_4x8
:
964 case nir_op_pack_unorm_2x16
:
965 case nir_op_pack_unorm_4x8
:
966 case nir_op_unpack_snorm_2x16
:
967 case nir_op_unpack_snorm_4x8
:
968 case nir_op_unpack_unorm_2x16
:
969 case nir_op_unpack_unorm_4x8
:
970 case nir_op_unpack_half_2x16
:
971 case nir_op_pack_half_2x16
:
972 unreachable("not reached: should be handled by lower_packing_builtins");
974 case nir_op_unpack_half_2x16_split_x
:
975 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
, result
, op
[0]);
976 inst
->saturate
= instr
->dest
.saturate
;
978 case nir_op_unpack_half_2x16_split_y
:
979 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
, result
, op
[0]);
980 inst
->saturate
= instr
->dest
.saturate
;
984 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
985 inst
->saturate
= instr
->dest
.saturate
;
988 case nir_op_bitfield_reverse
:
989 bld
.BFREV(result
, op
[0]);
992 case nir_op_bit_count
:
993 bld
.CBIT(result
, op
[0]);
996 case nir_op_ufind_msb
:
997 case nir_op_ifind_msb
: {
998 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
1000 /* FBH counts from the MSB side, while GLSL's findMSB() wants the count
1001 * from the LSB side. If FBH didn't return an error (0xFFFFFFFF), then
1002 * subtract the result from 31 to convert the MSB count into an LSB count.
1004 bld
.CMP(bld
.null_reg_d(), result
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
);
1006 inst
= bld
.ADD(result
, result
, brw_imm_d(31));
1007 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1008 inst
->src
[0].negate
= true;
1012 case nir_op_find_lsb
:
1013 bld
.FBL(result
, op
[0]);
1016 case nir_op_ubitfield_extract
:
1017 case nir_op_ibitfield_extract
:
1018 bld
.BFE(result
, op
[2], op
[1], op
[0]);
1021 bld
.BFI1(result
, op
[0], op
[1]);
1024 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
1027 case nir_op_bitfield_insert
:
1028 unreachable("not reached: should be handled by "
1029 "lower_instructions::bitfield_insert_to_bfm_bfi");
1032 bld
.SHL(result
, op
[0], op
[1]);
1035 bld
.ASR(result
, op
[0], op
[1]);
1038 bld
.SHR(result
, op
[0], op
[1]);
1041 case nir_op_pack_half_2x16_split
:
1042 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1046 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
1047 inst
->saturate
= instr
->dest
.saturate
;
1051 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
1052 inst
->saturate
= instr
->dest
.saturate
;
1056 if (optimize_frontfacing_ternary(instr
, result
))
1059 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1060 inst
= bld
.SEL(result
, op
[1], op
[2]);
1061 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1065 unreachable("unhandled instruction");
1068 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1069 * to sign extend the low bit to 0/~0
1071 if (devinfo
->gen
<= 5 &&
1072 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1073 fs_reg masked
= vgrf(glsl_type::int_type
);
1074 bld
.AND(masked
, result
, brw_imm_d(1));
1075 masked
.negate
= true;
1076 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
1081 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
1082 nir_load_const_instr
*instr
)
1084 fs_reg reg
= bld
.vgrf(BRW_REGISTER_TYPE_D
, instr
->def
.num_components
);
1086 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1087 bld
.MOV(offset(reg
, bld
, i
), brw_imm_d(instr
->value
.i
[i
]));
1089 nir_ssa_values
[instr
->def
.index
] = reg
;
1093 fs_visitor::nir_emit_undef(const fs_builder
&bld
, nir_ssa_undef_instr
*instr
)
1095 nir_ssa_values
[instr
->def
.index
] = bld
.vgrf(BRW_REGISTER_TYPE_D
,
1096 instr
->def
.num_components
);
1100 fs_visitor::get_nir_src(nir_src src
)
1104 reg
= nir_ssa_values
[src
.ssa
->index
];
1106 /* We don't handle indirects on locals */
1107 assert(src
.reg
.indirect
== NULL
);
1108 reg
= offset(nir_locals
[src
.reg
.reg
->index
], bld
,
1109 src
.reg
.base_offset
* src
.reg
.reg
->num_components
);
1112 /* to avoid floating-point denorm flushing problems, set the type by
1113 * default to D - instructions that need floating point semantics will set
1114 * this to F if they need to
1116 return retype(reg
, BRW_REGISTER_TYPE_D
);
1120 fs_visitor::get_nir_dest(nir_dest dest
)
1123 nir_ssa_values
[dest
.ssa
.index
] = bld
.vgrf(BRW_REGISTER_TYPE_F
,
1124 dest
.ssa
.num_components
);
1125 return nir_ssa_values
[dest
.ssa
.index
];
1127 /* We don't handle indirects on locals */
1128 assert(dest
.reg
.indirect
== NULL
);
1129 return offset(nir_locals
[dest
.reg
.reg
->index
], bld
,
1130 dest
.reg
.base_offset
* dest
.reg
.reg
->num_components
);
1135 fs_visitor::get_nir_image_deref(const nir_deref_var
*deref
)
1137 fs_reg
image(UNIFORM
, deref
->var
->data
.driver_location
/ 4,
1138 BRW_REGISTER_TYPE_UD
);
1140 for (const nir_deref
*tail
= &deref
->deref
; tail
->child
;
1141 tail
= tail
->child
) {
1142 const nir_deref_array
*deref_array
= nir_deref_as_array(tail
->child
);
1143 assert(tail
->child
->deref_type
== nir_deref_type_array
);
1144 const unsigned size
= glsl_get_length(tail
->type
);
1145 const unsigned element_size
= type_size_scalar(deref_array
->deref
.type
);
1146 const unsigned base
= MIN2(deref_array
->base_offset
, size
- 1);
1147 image
= offset(image
, bld
, base
* element_size
);
1149 if (deref_array
->deref_array_type
== nir_deref_array_type_indirect
) {
1150 fs_reg tmp
= vgrf(glsl_type::int_type
);
1152 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
) {
1153 /* IVB hangs when trying to access an invalid surface index with
1154 * the dataport. According to the spec "if the index used to
1155 * select an individual element is negative or greater than or
1156 * equal to the size of the array, the results of the operation
1157 * are undefined but may not lead to termination" -- which is one
1158 * of the possible outcomes of the hang. Clamp the index to
1159 * prevent access outside of the array bounds.
1161 bld
.emit_minmax(tmp
, retype(get_nir_src(deref_array
->indirect
),
1162 BRW_REGISTER_TYPE_UD
),
1163 brw_imm_ud(size
- base
- 1), BRW_CONDITIONAL_L
);
1165 bld
.MOV(tmp
, get_nir_src(deref_array
->indirect
));
1168 bld
.MUL(tmp
, tmp
, brw_imm_ud(element_size
* 4));
1170 bld
.ADD(*image
.reladdr
, *image
.reladdr
, tmp
);
1172 image
.reladdr
= new(mem_ctx
) fs_reg(tmp
);
1180 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
1183 for (unsigned i
= 0; i
< 4; i
++) {
1184 if (!((wr_mask
>> i
) & 1))
1187 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
1188 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
1189 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1190 if (new_inst
->src
[j
].file
== VGRF
)
1191 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
1198 * Get the matching channel register datatype for an image intrinsic of the
1199 * specified GLSL image type.
1202 get_image_base_type(const glsl_type
*type
)
1204 switch ((glsl_base_type
)type
->sampler_type
) {
1205 case GLSL_TYPE_UINT
:
1206 return BRW_REGISTER_TYPE_UD
;
1208 return BRW_REGISTER_TYPE_D
;
1209 case GLSL_TYPE_FLOAT
:
1210 return BRW_REGISTER_TYPE_F
;
1212 unreachable("Not reached.");
1217 * Get the appropriate atomic op for an image atomic intrinsic.
1220 get_image_atomic_op(nir_intrinsic_op op
, const glsl_type
*type
)
1223 case nir_intrinsic_image_atomic_add
:
1225 case nir_intrinsic_image_atomic_min
:
1226 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1227 BRW_AOP_IMIN
: BRW_AOP_UMIN
);
1228 case nir_intrinsic_image_atomic_max
:
1229 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1230 BRW_AOP_IMAX
: BRW_AOP_UMAX
);
1231 case nir_intrinsic_image_atomic_and
:
1233 case nir_intrinsic_image_atomic_or
:
1235 case nir_intrinsic_image_atomic_xor
:
1237 case nir_intrinsic_image_atomic_exchange
:
1239 case nir_intrinsic_image_atomic_comp_swap
:
1240 return BRW_AOP_CMPWR
;
1242 unreachable("Not reachable.");
1247 emit_pixel_interpolater_send(const fs_builder
&bld
,
1252 glsl_interp_qualifier interpolation
)
1258 if (src
.file
== BAD_FILE
) {
1260 payload
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 1);
1264 mlen
= 2 * bld
.dispatch_width() / 8;
1267 inst
= bld
.emit(opcode
, dst
, payload
, desc
);
1269 /* 2 floats per slot returned */
1270 inst
->regs_written
= 2 * bld
.dispatch_width() / 8;
1271 inst
->pi_noperspective
= interpolation
== INTERP_QUALIFIER_NOPERSPECTIVE
;
1277 * Computes 1 << x, given a D/UD register containing some value x.
1280 intexp2(const fs_builder
&bld
, const fs_reg
&x
)
1282 assert(x
.type
== BRW_REGISTER_TYPE_UD
|| x
.type
== BRW_REGISTER_TYPE_D
);
1284 fs_reg result
= bld
.vgrf(x
.type
, 1);
1285 fs_reg one
= bld
.vgrf(x
.type
, 1);
1287 bld
.MOV(one
, retype(brw_imm_d(1), one
.type
));
1288 bld
.SHL(result
, one
, x
);
1293 fs_visitor::emit_gs_end_primitive(const nir_src
&vertex_count_nir_src
)
1295 assert(stage
== MESA_SHADER_GEOMETRY
);
1297 struct brw_gs_prog_data
*gs_prog_data
=
1298 (struct brw_gs_prog_data
*) prog_data
;
1300 /* We can only do EndPrimitive() functionality when the control data
1301 * consists of cut bits. Fortunately, the only time it isn't is when the
1302 * output type is points, in which case EndPrimitive() is a no-op.
1304 if (gs_prog_data
->control_data_format
!=
1305 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT
) {
1309 /* Cut bits use one bit per vertex. */
1310 assert(gs_compile
->control_data_bits_per_vertex
== 1);
1312 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1313 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1315 /* Cut bit n should be set to 1 if EndPrimitive() was called after emitting
1316 * vertex n, 0 otherwise. So all we need to do here is mark bit
1317 * (vertex_count - 1) % 32 in the cut_bits register to indicate that
1318 * EndPrimitive() was called after emitting vertex (vertex_count - 1);
1319 * vec4_gs_visitor::emit_control_data_bits() will take care of the rest.
1321 * Note that if EndPrimitive() is called before emitting any vertices, this
1322 * will cause us to set bit 31 of the control_data_bits register to 1.
1323 * That's fine because:
1325 * - If max_vertices < 32, then vertex number 31 (zero-based) will never be
1326 * output, so the hardware will ignore cut bit 31.
1328 * - If max_vertices == 32, then vertex number 31 is guaranteed to be the
1329 * last vertex, so setting cut bit 31 has no effect (since the primitive
1330 * is automatically ended when the GS terminates).
1332 * - If max_vertices > 32, then the ir_emit_vertex visitor will reset the
1333 * control_data_bits register to 0 when the first vertex is emitted.
1336 const fs_builder abld
= bld
.annotate("end primitive");
1338 /* control_data_bits |= 1 << ((vertex_count - 1) % 32) */
1339 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1340 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1341 fs_reg mask
= intexp2(abld
, prev_count
);
1342 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1343 * attention to the lower 5 bits of its second source argument, so on this
1344 * architecture, 1 << (vertex_count - 1) is equivalent to 1 <<
1345 * ((vertex_count - 1) % 32).
1347 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1351 fs_visitor::emit_gs_control_data_bits(const fs_reg
&vertex_count
)
1353 assert(stage
== MESA_SHADER_GEOMETRY
);
1354 assert(gs_compile
->control_data_bits_per_vertex
!= 0);
1356 struct brw_gs_prog_data
*gs_prog_data
=
1357 (struct brw_gs_prog_data
*) prog_data
;
1359 const fs_builder abld
= bld
.annotate("emit control data bits");
1360 const fs_builder fwa_bld
= bld
.exec_all();
1362 /* We use a single UD register to accumulate control data bits (32 bits
1363 * for each of the SIMD8 channels). So we need to write a DWord (32 bits)
1366 * Unfortunately, the URB_WRITE_SIMD8 message uses 128-bit (OWord) offsets.
1367 * We have select a 128-bit group via the Global and Per-Slot Offsets, then
1368 * use the Channel Mask phase to enable/disable which DWord within that
1369 * group to write. (Remember, different SIMD8 channels may have emitted
1370 * different numbers of vertices, so we may need per-slot offsets.)
1372 * Channel masking presents an annoying problem: we may have to replicate
1373 * the data up to 4 times:
1375 * Msg = Handles, Per-Slot Offsets, Channel Masks, Data, Data, Data, Data.
1377 * To avoid penalizing shaders that emit a small number of vertices, we
1378 * can avoid these sometimes: if the size of the control data header is
1379 * <= 128 bits, then there is only 1 OWord. All SIMD8 channels will land
1380 * land in the same 128-bit group, so we can skip per-slot offsets.
1382 * Similarly, if the control data header is <= 32 bits, there is only one
1383 * DWord, so we can skip channel masks.
1385 enum opcode opcode
= SHADER_OPCODE_URB_WRITE_SIMD8
;
1387 fs_reg channel_mask
, per_slot_offset
;
1389 if (gs_compile
->control_data_header_size_bits
> 32) {
1390 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
1391 channel_mask
= vgrf(glsl_type::uint_type
);
1394 if (gs_compile
->control_data_header_size_bits
> 128) {
1395 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
;
1396 per_slot_offset
= vgrf(glsl_type::uint_type
);
1399 /* Figure out which DWord we're trying to write to using the formula:
1401 * dword_index = (vertex_count - 1) * bits_per_vertex / 32
1403 * Since bits_per_vertex is a power of two, and is known at compile
1404 * time, this can be optimized to:
1406 * dword_index = (vertex_count - 1) >> (6 - log2(bits_per_vertex))
1408 if (opcode
!= SHADER_OPCODE_URB_WRITE_SIMD8
) {
1409 fs_reg dword_index
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1410 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1411 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1412 unsigned log2_bits_per_vertex
=
1413 _mesa_fls(gs_compile
->control_data_bits_per_vertex
);
1414 abld
.SHR(dword_index
, prev_count
, brw_imm_ud(6u - log2_bits_per_vertex
));
1416 if (per_slot_offset
.file
!= BAD_FILE
) {
1417 /* Set the per-slot offset to dword_index / 4, so that we'll write to
1418 * the appropriate OWord within the control data header.
1420 abld
.SHR(per_slot_offset
, dword_index
, brw_imm_ud(2u));
1423 /* Set the channel masks to 1 << (dword_index % 4), so that we'll
1424 * write to the appropriate DWORD within the OWORD.
1426 fs_reg channel
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1427 fwa_bld
.AND(channel
, dword_index
, brw_imm_ud(3u));
1428 channel_mask
= intexp2(fwa_bld
, channel
);
1429 /* Then the channel masks need to be in bits 23:16. */
1430 fwa_bld
.SHL(channel_mask
, channel_mask
, brw_imm_ud(16u));
1433 /* Store the control data bits in the message payload and send it. */
1435 if (channel_mask
.file
!= BAD_FILE
)
1436 mlen
+= 4; /* channel masks, plus 3 extra copies of the data */
1437 if (per_slot_offset
.file
!= BAD_FILE
)
1440 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
1441 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, mlen
);
1443 sources
[i
++] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1444 if (per_slot_offset
.file
!= BAD_FILE
)
1445 sources
[i
++] = per_slot_offset
;
1446 if (channel_mask
.file
!= BAD_FILE
)
1447 sources
[i
++] = channel_mask
;
1449 sources
[i
++] = this->control_data_bits
;
1452 abld
.LOAD_PAYLOAD(payload
, sources
, mlen
, mlen
);
1453 fs_inst
*inst
= abld
.emit(opcode
, reg_undef
, payload
);
1455 /* We need to increment Global Offset by 256-bits to make room for
1456 * Broadwell's extra "Vertex Count" payload at the beginning of the
1457 * URB entry. Since this is an OWord message, Global Offset is counted
1458 * in 128-bit units, so we must set it to 2.
1460 if (gs_prog_data
->static_vertex_count
== -1)
1465 fs_visitor::set_gs_stream_control_data_bits(const fs_reg
&vertex_count
,
1468 /* control_data_bits |= stream_id << ((2 * (vertex_count - 1)) % 32) */
1470 /* Note: we are calling this *before* increasing vertex_count, so
1471 * this->vertex_count == vertex_count - 1 in the formula above.
1474 /* Stream mode uses 2 bits per vertex */
1475 assert(gs_compile
->control_data_bits_per_vertex
== 2);
1477 /* Must be a valid stream */
1478 assert(stream_id
>= 0 && stream_id
< MAX_VERTEX_STREAMS
);
1480 /* Control data bits are initialized to 0 so we don't have to set any
1481 * bits when sending vertices to stream 0.
1486 const fs_builder abld
= bld
.annotate("set stream control data bits", NULL
);
1488 /* reg::sid = stream_id */
1489 fs_reg sid
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1490 abld
.MOV(sid
, brw_imm_ud(stream_id
));
1492 /* reg:shift_count = 2 * (vertex_count - 1) */
1493 fs_reg shift_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1494 abld
.SHL(shift_count
, vertex_count
, brw_imm_ud(1u));
1496 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1497 * attention to the lower 5 bits of its second source argument, so on this
1498 * architecture, stream_id << 2 * (vertex_count - 1) is equivalent to
1499 * stream_id << ((2 * (vertex_count - 1)) % 32).
1501 fs_reg mask
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1502 abld
.SHL(mask
, sid
, shift_count
);
1503 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1507 fs_visitor::emit_gs_vertex(const nir_src
&vertex_count_nir_src
,
1510 assert(stage
== MESA_SHADER_GEOMETRY
);
1512 struct brw_gs_prog_data
*gs_prog_data
=
1513 (struct brw_gs_prog_data
*) prog_data
;
1515 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1516 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1518 /* Haswell and later hardware ignores the "Render Stream Select" bits
1519 * from the 3DSTATE_STREAMOUT packet when the SOL stage is disabled,
1520 * and instead sends all primitives down the pipeline for rasterization.
1521 * If the SOL stage is enabled, "Render Stream Select" is honored and
1522 * primitives bound to non-zero streams are discarded after stream output.
1524 * Since the only purpose of primives sent to non-zero streams is to
1525 * be recorded by transform feedback, we can simply discard all geometry
1526 * bound to these streams when transform feedback is disabled.
1528 if (stream_id
> 0 && !nir
->info
.has_transform_feedback_varyings
)
1531 /* If we're outputting 32 control data bits or less, then we can wait
1532 * until the shader is over to output them all. Otherwise we need to
1533 * output them as we go. Now is the time to do it, since we're about to
1534 * output the vertex_count'th vertex, so it's guaranteed that the
1535 * control data bits associated with the (vertex_count - 1)th vertex are
1538 if (gs_compile
->control_data_header_size_bits
> 32) {
1539 const fs_builder abld
=
1540 bld
.annotate("emit vertex: emit control data bits");
1542 /* Only emit control data bits if we've finished accumulating a batch
1543 * of 32 bits. This is the case when:
1545 * (vertex_count * bits_per_vertex) % 32 == 0
1547 * (in other words, when the last 5 bits of vertex_count *
1548 * bits_per_vertex are 0). Assuming bits_per_vertex == 2^n for some
1549 * integer n (which is always the case, since bits_per_vertex is
1550 * always 1 or 2), this is equivalent to requiring that the last 5-n
1551 * bits of vertex_count are 0:
1553 * vertex_count & (2^(5-n) - 1) == 0
1555 * 2^(5-n) == 2^5 / 2^n == 32 / bits_per_vertex, so this is
1558 * vertex_count & (32 / bits_per_vertex - 1) == 0
1560 * TODO: If vertex_count is an immediate, we could do some of this math
1561 * at compile time...
1564 abld
.AND(bld
.null_reg_d(), vertex_count
,
1565 brw_imm_ud(32u / gs_compile
->control_data_bits_per_vertex
- 1u));
1566 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1568 abld
.IF(BRW_PREDICATE_NORMAL
);
1569 /* If vertex_count is 0, then no control data bits have been
1570 * accumulated yet, so we can skip emitting them.
1572 abld
.CMP(bld
.null_reg_d(), vertex_count
, brw_imm_ud(0u),
1573 BRW_CONDITIONAL_NEQ
);
1574 abld
.IF(BRW_PREDICATE_NORMAL
);
1575 emit_gs_control_data_bits(vertex_count
);
1576 abld
.emit(BRW_OPCODE_ENDIF
);
1578 /* Reset control_data_bits to 0 so we can start accumulating a new
1581 * Note: in the case where vertex_count == 0, this neutralizes the
1582 * effect of any call to EndPrimitive() that the shader may have
1583 * made before outputting its first vertex.
1585 inst
= abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
1586 inst
->force_writemask_all
= true;
1587 abld
.emit(BRW_OPCODE_ENDIF
);
1590 emit_urb_writes(vertex_count
);
1592 /* In stream mode we have to set control data bits for all vertices
1593 * unless we have disabled control data bits completely (which we do
1594 * do for GL_POINTS outputs that don't use streams).
1596 if (gs_compile
->control_data_header_size_bits
> 0 &&
1597 gs_prog_data
->control_data_format
==
1598 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
) {
1599 set_gs_stream_control_data_bits(vertex_count
, stream_id
);
1604 fs_visitor::emit_gs_input_load(const fs_reg
&dst
,
1605 const nir_src
&vertex_src
,
1606 unsigned base_offset
,
1607 const nir_src
&offset_src
,
1608 unsigned num_components
)
1610 struct brw_gs_prog_data
*gs_prog_data
= (struct brw_gs_prog_data
*) prog_data
;
1612 nir_const_value
*vertex_const
= nir_src_as_const_value(vertex_src
);
1613 nir_const_value
*offset_const
= nir_src_as_const_value(offset_src
);
1614 const unsigned push_reg_count
= gs_prog_data
->base
.urb_read_length
* 8;
1616 /* Offset 0 is the VUE header, which contains VARYING_SLOT_LAYER [.y],
1617 * VARYING_SLOT_VIEWPORT [.z], and VARYING_SLOT_PSIZ [.w]. Only
1618 * gl_PointSize is available as a GS input, however, so it must be that.
1620 const bool is_point_size
= (base_offset
== 0);
1622 if (offset_const
!= NULL
&& vertex_const
!= NULL
&&
1623 4 * (base_offset
+ offset_const
->u
[0]) < push_reg_count
) {
1624 int imm_offset
= (base_offset
+ offset_const
->u
[0]) * 4 +
1625 vertex_const
->u
[0] * push_reg_count
;
1626 /* This input was pushed into registers. */
1627 if (is_point_size
) {
1628 /* gl_PointSize comes in .w */
1629 assert(imm_offset
== 0);
1630 bld
.MOV(dst
, fs_reg(ATTR
, imm_offset
+ 3, dst
.type
));
1632 for (unsigned i
= 0; i
< num_components
; i
++) {
1633 bld
.MOV(offset(dst
, bld
, i
),
1634 fs_reg(ATTR
, imm_offset
+ i
, dst
.type
));
1638 /* Resort to the pull model. Ensure the VUE handles are provided. */
1639 gs_prog_data
->base
.include_vue_handles
= true;
1641 unsigned first_icp_handle
= gs_prog_data
->include_primitive_id
? 3 : 2;
1645 /* The vertex index is constant; just select the proper URB handle. */
1647 retype(brw_vec8_grf(first_icp_handle
+ vertex_const
->i
[0], 0),
1648 BRW_REGISTER_TYPE_UD
);
1650 /* The vertex index is non-constant. We need to use indirect
1651 * addressing to fetch the proper URB handle.
1653 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
1654 * indicating that channel <n> should read the handle from
1655 * DWord <n>. We convert that to bytes by multiplying by 4.
1657 * Next, we convert the vertex index to bytes by multiplying
1658 * by 32 (shifting by 5), and add the two together. This is
1659 * the final indirect byte offset.
1661 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_W
, 1);
1662 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1663 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1664 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1665 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1667 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
1668 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
1669 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
1670 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
1671 /* Convert vertex_index to bytes (multiply by 32) */
1672 bld
.SHL(vertex_offset_bytes
,
1673 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
1675 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
1677 /* Use first_icp_handle as the base offset. There is one register
1678 * of URB handles per vertex, so inform the register allocator that
1679 * we might read up to nir->info.gs.vertices_in registers.
1681 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
1682 fs_reg(brw_vec8_grf(first_icp_handle
, 0)),
1683 fs_reg(icp_offset_bytes
),
1684 brw_imm_ud(nir
->info
.gs
.vertices_in
* REG_SIZE
));
1689 /* Constant indexing - use global offset. */
1690 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
1691 inst
->offset
= base_offset
+ offset_const
->u
[0];
1692 inst
->base_mrf
= -1;
1694 inst
->regs_written
= num_components
;
1696 /* Indirect indexing - use per-slot offsets as well. */
1697 const fs_reg srcs
[] = { icp_handle
, get_nir_src(offset_src
) };
1698 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
1699 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
1701 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
, payload
);
1702 inst
->offset
= base_offset
;
1703 inst
->base_mrf
= -1;
1705 inst
->regs_written
= num_components
;
1708 if (is_point_size
) {
1709 /* Read the whole VUE header (because of alignment) and read .w. */
1710 fs_reg tmp
= bld
.vgrf(dst
.type
, 4);
1712 inst
->regs_written
= 4;
1713 bld
.MOV(dst
, offset(tmp
, bld
, 3));
1719 fs_visitor::nir_emit_vs_intrinsic(const fs_builder
&bld
,
1720 nir_intrinsic_instr
*instr
)
1722 assert(stage
== MESA_SHADER_VERTEX
);
1725 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
1726 dest
= get_nir_dest(instr
->dest
);
1728 switch (instr
->intrinsic
) {
1729 case nir_intrinsic_load_vertex_id
:
1730 unreachable("should be lowered by lower_vertex_id()");
1732 case nir_intrinsic_load_vertex_id_zero_base
:
1733 case nir_intrinsic_load_base_vertex
:
1734 case nir_intrinsic_load_instance_id
: {
1735 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
1736 fs_reg val
= nir_system_values
[sv
];
1737 assert(val
.file
!= BAD_FILE
);
1738 dest
.type
= val
.type
;
1744 nir_emit_intrinsic(bld
, instr
);
1750 fs_visitor::nir_emit_gs_intrinsic(const fs_builder
&bld
,
1751 nir_intrinsic_instr
*instr
)
1753 assert(stage
== MESA_SHADER_GEOMETRY
);
1754 fs_reg indirect_offset
;
1757 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
1758 dest
= get_nir_dest(instr
->dest
);
1760 switch (instr
->intrinsic
) {
1761 case nir_intrinsic_load_primitive_id
:
1762 assert(stage
== MESA_SHADER_GEOMETRY
);
1763 assert(((struct brw_gs_prog_data
*)prog_data
)->include_primitive_id
);
1764 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
1765 retype(fs_reg(brw_vec8_grf(2, 0)), BRW_REGISTER_TYPE_UD
));
1768 case nir_intrinsic_load_input
:
1769 unreachable("load_input intrinsics are invalid for the GS stage");
1771 case nir_intrinsic_load_per_vertex_input
:
1772 emit_gs_input_load(dest
, instr
->src
[0], instr
->const_index
[0],
1773 instr
->src
[1], instr
->num_components
);
1776 case nir_intrinsic_emit_vertex_with_counter
:
1777 emit_gs_vertex(instr
->src
[0], instr
->const_index
[0]);
1780 case nir_intrinsic_end_primitive_with_counter
:
1781 emit_gs_end_primitive(instr
->src
[0]);
1784 case nir_intrinsic_set_vertex_count
:
1785 bld
.MOV(this->final_gs_vertex_count
, get_nir_src(instr
->src
[0]));
1788 case nir_intrinsic_load_invocation_id
: {
1789 fs_reg val
= nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
1790 assert(val
.file
!= BAD_FILE
);
1791 dest
.type
= val
.type
;
1797 nir_emit_intrinsic(bld
, instr
);
1803 fs_visitor::nir_emit_fs_intrinsic(const fs_builder
&bld
,
1804 nir_intrinsic_instr
*instr
)
1806 assert(stage
== MESA_SHADER_FRAGMENT
);
1807 struct brw_wm_prog_data
*wm_prog_data
=
1808 (struct brw_wm_prog_data
*) prog_data
;
1811 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
1812 dest
= get_nir_dest(instr
->dest
);
1814 switch (instr
->intrinsic
) {
1815 case nir_intrinsic_load_front_face
:
1816 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
1817 *emit_frontfacing_interpolation());
1820 case nir_intrinsic_load_sample_pos
: {
1821 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
1822 assert(sample_pos
.file
!= BAD_FILE
);
1823 dest
.type
= sample_pos
.type
;
1824 bld
.MOV(dest
, sample_pos
);
1825 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
1829 case nir_intrinsic_load_helper_invocation
:
1830 case nir_intrinsic_load_sample_mask_in
:
1831 case nir_intrinsic_load_sample_id
: {
1832 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
1833 fs_reg val
= nir_system_values
[sv
];
1834 assert(val
.file
!= BAD_FILE
);
1835 dest
.type
= val
.type
;
1840 case nir_intrinsic_discard
:
1841 case nir_intrinsic_discard_if
: {
1842 /* We track our discarded pixels in f0.1. By predicating on it, we can
1843 * update just the flag bits that aren't yet discarded. If there's no
1844 * condition, we emit a CMP of g0 != g0, so all currently executing
1845 * channels will get turned off.
1848 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
1849 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
1850 brw_imm_d(0), BRW_CONDITIONAL_Z
);
1852 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
1853 BRW_REGISTER_TYPE_UW
));
1854 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
1856 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
1857 cmp
->flag_subreg
= 1;
1859 if (devinfo
->gen
>= 6) {
1860 emit_discard_jump();
1865 case nir_intrinsic_interp_var_at_centroid
:
1866 case nir_intrinsic_interp_var_at_sample
:
1867 case nir_intrinsic_interp_var_at_offset
: {
1868 /* Handle ARB_gpu_shader5 interpolation intrinsics
1870 * It's worth a quick word of explanation as to why we handle the full
1871 * variable-based interpolation intrinsic rather than a lowered version
1872 * with like we do for other inputs. We have to do that because the way
1873 * we set up inputs doesn't allow us to use the already setup inputs for
1874 * interpolation. At the beginning of the shader, we go through all of
1875 * the input variables and do the initial interpolation and put it in
1876 * the nir_inputs array based on its location as determined in
1877 * nir_lower_io. If the input isn't used, dead code cleans up and
1878 * everything works fine. However, when we get to the ARB_gpu_shader5
1879 * interpolation intrinsics, we need to reinterpolate the input
1880 * differently. If we used an intrinsic that just had an index it would
1881 * only give us the offset into the nir_inputs array. However, this is
1882 * useless because that value is post-interpolation and we need
1883 * pre-interpolation. In order to get the actual location of the bits
1884 * we get from the vertex fetching hardware, we need the variable.
1886 wm_prog_data
->pulls_bary
= true;
1888 fs_reg dst_xy
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 2);
1889 const glsl_interp_qualifier interpolation
=
1890 (glsl_interp_qualifier
) instr
->variables
[0]->var
->data
.interpolation
;
1892 switch (instr
->intrinsic
) {
1893 case nir_intrinsic_interp_var_at_centroid
:
1894 emit_pixel_interpolater_send(bld
,
1895 FS_OPCODE_INTERPOLATE_AT_CENTROID
,
1902 case nir_intrinsic_interp_var_at_sample
: {
1903 nir_const_value
*const_sample
= nir_src_as_const_value(instr
->src
[0]);
1906 unsigned msg_data
= const_sample
->i
[0] << 4;
1908 emit_pixel_interpolater_send(bld
,
1909 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
1912 brw_imm_ud(msg_data
),
1915 const fs_reg sample_src
= retype(get_nir_src(instr
->src
[0]),
1916 BRW_REGISTER_TYPE_UD
);
1918 if (nir_src_is_dynamically_uniform(instr
->src
[0])) {
1919 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
1920 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
1921 bld
.exec_all().group(1, 0)
1922 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
1923 emit_pixel_interpolater_send(bld
,
1924 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
1930 /* Make a loop that sends a message to the pixel interpolater
1931 * for the sample number in each live channel. If there are
1932 * multiple channels with the same sample number then these
1933 * will be handled simultaneously with a single interation of
1936 bld
.emit(BRW_OPCODE_DO
);
1938 /* Get the next live sample number into sample_id_reg */
1939 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
1941 /* Set the flag register so that we can perform the send
1942 * message on all channels that have the same sample number
1944 bld
.CMP(bld
.null_reg_ud(),
1945 sample_src
, sample_id
,
1946 BRW_CONDITIONAL_EQ
);
1947 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
1948 bld
.exec_all().group(1, 0)
1949 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
1951 emit_pixel_interpolater_send(bld
,
1952 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
1957 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
1959 /* Continue the loop if there are any live channels left */
1960 set_predicate_inv(BRW_PREDICATE_NORMAL
,
1962 bld
.emit(BRW_OPCODE_WHILE
));
1969 case nir_intrinsic_interp_var_at_offset
: {
1970 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
1973 unsigned off_x
= MIN2((int)(const_offset
->f
[0] * 16), 7) & 0xf;
1974 unsigned off_y
= MIN2((int)(const_offset
->f
[1] * 16), 7) & 0xf;
1976 emit_pixel_interpolater_send(bld
,
1977 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
,
1980 brw_imm_ud(off_x
| (off_y
<< 4)),
1983 fs_reg src
= vgrf(glsl_type::ivec2_type
);
1984 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
1985 BRW_REGISTER_TYPE_F
);
1986 for (int i
= 0; i
< 2; i
++) {
1987 fs_reg temp
= vgrf(glsl_type::float_type
);
1988 bld
.MUL(temp
, offset(offset_src
, bld
, i
), brw_imm_f(16.0f
));
1989 fs_reg itemp
= vgrf(glsl_type::int_type
);
1990 bld
.MOV(itemp
, temp
); /* float to int */
1992 /* Clamp the upper end of the range to +7/16.
1993 * ARB_gpu_shader5 requires that we support a maximum offset
1994 * of +0.5, which isn't representable in a S0.4 value -- if
1995 * we didn't clamp it, we'd end up with -8/16, which is the
1996 * opposite of what the shader author wanted.
1998 * This is legal due to ARB_gpu_shader5's quantization
2001 * "Not all values of <offset> may be supported; x and y
2002 * offsets may be rounded to fixed-point values with the
2003 * number of fraction bits given by the
2004 * implementation-dependent constant
2005 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
2007 set_condmod(BRW_CONDITIONAL_L
,
2008 bld
.SEL(offset(src
, bld
, i
), itemp
, brw_imm_d(7)));
2011 const enum opcode opcode
= FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
;
2012 emit_pixel_interpolater_send(bld
,
2023 unreachable("Invalid intrinsic");
2026 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
2027 fs_reg src
= interp_reg(instr
->variables
[0]->var
->data
.location
, j
);
2028 src
.type
= dest
.type
;
2030 bld
.emit(FS_OPCODE_LINTERP
, dest
, dst_xy
, src
);
2031 dest
= offset(dest
, bld
, 1);
2036 nir_emit_intrinsic(bld
, instr
);
2042 fs_visitor::nir_emit_cs_intrinsic(const fs_builder
&bld
,
2043 nir_intrinsic_instr
*instr
)
2045 assert(stage
== MESA_SHADER_COMPUTE
);
2046 struct brw_cs_prog_data
*cs_prog_data
=
2047 (struct brw_cs_prog_data
*) prog_data
;
2050 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2051 dest
= get_nir_dest(instr
->dest
);
2053 switch (instr
->intrinsic
) {
2054 case nir_intrinsic_barrier
:
2056 cs_prog_data
->uses_barrier
= true;
2059 case nir_intrinsic_load_local_invocation_id
:
2060 case nir_intrinsic_load_work_group_id
: {
2061 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
2062 fs_reg val
= nir_system_values
[sv
];
2063 assert(val
.file
!= BAD_FILE
);
2064 dest
.type
= val
.type
;
2065 for (unsigned i
= 0; i
< 3; i
++)
2066 bld
.MOV(offset(dest
, bld
, i
), offset(val
, bld
, i
));
2070 case nir_intrinsic_load_num_work_groups
: {
2071 const unsigned surface
=
2072 cs_prog_data
->binding_table
.work_groups_start
;
2074 cs_prog_data
->uses_num_work_groups
= true;
2076 fs_reg surf_index
= brw_imm_ud(surface
);
2077 brw_mark_surface_used(prog_data
, surface
);
2079 /* Read the 3 GLuint components of gl_NumWorkGroups */
2080 for (unsigned i
= 0; i
< 3; i
++) {
2081 fs_reg read_result
=
2082 emit_untyped_read(bld
, surf_index
,
2084 1 /* dims */, 1 /* size */,
2085 BRW_PREDICATE_NONE
);
2086 read_result
.type
= dest
.type
;
2087 bld
.MOV(dest
, read_result
);
2088 dest
= offset(dest
, bld
, 1);
2093 case nir_intrinsic_shared_atomic_add
:
2094 nir_emit_shared_atomic(bld
, BRW_AOP_ADD
, instr
);
2096 case nir_intrinsic_shared_atomic_imin
:
2097 nir_emit_shared_atomic(bld
, BRW_AOP_IMIN
, instr
);
2099 case nir_intrinsic_shared_atomic_umin
:
2100 nir_emit_shared_atomic(bld
, BRW_AOP_UMIN
, instr
);
2102 case nir_intrinsic_shared_atomic_imax
:
2103 nir_emit_shared_atomic(bld
, BRW_AOP_IMAX
, instr
);
2105 case nir_intrinsic_shared_atomic_umax
:
2106 nir_emit_shared_atomic(bld
, BRW_AOP_UMAX
, instr
);
2108 case nir_intrinsic_shared_atomic_and
:
2109 nir_emit_shared_atomic(bld
, BRW_AOP_AND
, instr
);
2111 case nir_intrinsic_shared_atomic_or
:
2112 nir_emit_shared_atomic(bld
, BRW_AOP_OR
, instr
);
2114 case nir_intrinsic_shared_atomic_xor
:
2115 nir_emit_shared_atomic(bld
, BRW_AOP_XOR
, instr
);
2117 case nir_intrinsic_shared_atomic_exchange
:
2118 nir_emit_shared_atomic(bld
, BRW_AOP_MOV
, instr
);
2120 case nir_intrinsic_shared_atomic_comp_swap
:
2121 nir_emit_shared_atomic(bld
, BRW_AOP_CMPWR
, instr
);
2125 nir_emit_intrinsic(bld
, instr
);
2131 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
2134 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2135 dest
= get_nir_dest(instr
->dest
);
2137 switch (instr
->intrinsic
) {
2138 case nir_intrinsic_atomic_counter_inc
:
2139 case nir_intrinsic_atomic_counter_dec
:
2140 case nir_intrinsic_atomic_counter_read
: {
2141 using namespace surface_access
;
2143 /* Get the arguments of the atomic intrinsic. */
2144 const fs_reg offset
= get_nir_src(instr
->src
[0]);
2145 const unsigned surface
= (stage_prog_data
->binding_table
.abo_start
+
2146 instr
->const_index
[0]);
2149 /* Emit a surface read or atomic op. */
2150 switch (instr
->intrinsic
) {
2151 case nir_intrinsic_atomic_counter_read
:
2152 tmp
= emit_untyped_read(bld
, brw_imm_ud(surface
), offset
, 1, 1);
2155 case nir_intrinsic_atomic_counter_inc
:
2156 tmp
= emit_untyped_atomic(bld
, brw_imm_ud(surface
), offset
, fs_reg(),
2157 fs_reg(), 1, 1, BRW_AOP_INC
);
2160 case nir_intrinsic_atomic_counter_dec
:
2161 tmp
= emit_untyped_atomic(bld
, brw_imm_ud(surface
), offset
, fs_reg(),
2162 fs_reg(), 1, 1, BRW_AOP_PREDEC
);
2166 unreachable("Unreachable");
2169 /* Assign the result. */
2170 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), tmp
);
2172 /* Mark the surface as used. */
2173 brw_mark_surface_used(stage_prog_data
, surface
);
2177 case nir_intrinsic_image_load
:
2178 case nir_intrinsic_image_store
:
2179 case nir_intrinsic_image_atomic_add
:
2180 case nir_intrinsic_image_atomic_min
:
2181 case nir_intrinsic_image_atomic_max
:
2182 case nir_intrinsic_image_atomic_and
:
2183 case nir_intrinsic_image_atomic_or
:
2184 case nir_intrinsic_image_atomic_xor
:
2185 case nir_intrinsic_image_atomic_exchange
:
2186 case nir_intrinsic_image_atomic_comp_swap
: {
2187 using namespace image_access
;
2189 /* Get the referenced image variable and type. */
2190 const nir_variable
*var
= instr
->variables
[0]->var
;
2191 const glsl_type
*type
= var
->type
->without_array();
2192 const brw_reg_type base_type
= get_image_base_type(type
);
2194 /* Get some metadata from the image intrinsic. */
2195 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
2196 const unsigned arr_dims
= type
->sampler_array
? 1 : 0;
2197 const unsigned surf_dims
= type
->coordinate_components() - arr_dims
;
2198 const mesa_format format
=
2199 (var
->data
.image
.write_only
? MESA_FORMAT_NONE
:
2200 _mesa_get_shader_image_format(var
->data
.image
.format
));
2202 /* Get the arguments of the image intrinsic. */
2203 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
2204 const fs_reg addr
= retype(get_nir_src(instr
->src
[0]),
2205 BRW_REGISTER_TYPE_UD
);
2206 const fs_reg src0
= (info
->num_srcs
>= 3 ?
2207 retype(get_nir_src(instr
->src
[2]), base_type
) :
2209 const fs_reg src1
= (info
->num_srcs
>= 4 ?
2210 retype(get_nir_src(instr
->src
[3]), base_type
) :
2214 /* Emit an image load, store or atomic op. */
2215 if (instr
->intrinsic
== nir_intrinsic_image_load
)
2216 tmp
= emit_image_load(bld
, image
, addr
, surf_dims
, arr_dims
, format
);
2218 else if (instr
->intrinsic
== nir_intrinsic_image_store
)
2219 emit_image_store(bld
, image
, addr
, src0
, surf_dims
, arr_dims
, format
);
2222 tmp
= emit_image_atomic(bld
, image
, addr
, src0
, src1
,
2223 surf_dims
, arr_dims
, info
->dest_components
,
2224 get_image_atomic_op(instr
->intrinsic
, type
));
2226 /* Assign the result. */
2227 for (unsigned c
= 0; c
< info
->dest_components
; ++c
)
2228 bld
.MOV(offset(retype(dest
, base_type
), bld
, c
),
2229 offset(tmp
, bld
, c
));
2233 case nir_intrinsic_memory_barrier_atomic_counter
:
2234 case nir_intrinsic_memory_barrier_buffer
:
2235 case nir_intrinsic_memory_barrier_image
:
2236 case nir_intrinsic_memory_barrier
: {
2237 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 16 / dispatch_width
);
2238 bld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
)
2243 case nir_intrinsic_group_memory_barrier
:
2244 case nir_intrinsic_memory_barrier_shared
:
2245 /* We treat these workgroup-level barriers as no-ops. This should be
2246 * safe at present and as long as:
2248 * - Memory access instructions are not subsequently reordered by the
2249 * compiler back-end.
2251 * - All threads from a given compute shader workgroup fit within a
2252 * single subslice and therefore talk to the same HDC shared unit
2253 * what supposedly guarantees ordering and coherency between threads
2254 * from the same workgroup. This may change in the future when we
2255 * start splitting workgroups across multiple subslices.
2257 * - The context is not in fault-and-stream mode, which could cause
2258 * memory transactions (including to SLM) prior to the barrier to be
2259 * replayed after the barrier if a pagefault occurs. This shouldn't
2260 * be a problem up to and including SKL because fault-and-stream is
2261 * not usable due to hardware issues, but that's likely to change in
2266 case nir_intrinsic_shader_clock
: {
2267 /* We cannot do anything if there is an event, so ignore it for now */
2268 fs_reg shader_clock
= get_timestamp(bld
);
2269 const fs_reg srcs
[] = { shader_clock
.set_smear(0), shader_clock
.set_smear(1) };
2271 bld
.LOAD_PAYLOAD(dest
, srcs
, ARRAY_SIZE(srcs
), 0);
2275 case nir_intrinsic_image_size
: {
2276 /* Get the referenced image variable and type. */
2277 const nir_variable
*var
= instr
->variables
[0]->var
;
2278 const glsl_type
*type
= var
->type
->without_array();
2280 /* Get the size of the image. */
2281 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
2282 const fs_reg size
= offset(image
, bld
, BRW_IMAGE_PARAM_SIZE_OFFSET
);
2284 /* For 1DArray image types, the array index is stored in the Z component.
2285 * Fix this by swizzling the Z component to the Y component.
2287 const bool is_1d_array_image
=
2288 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_1D
&&
2289 type
->sampler_array
;
2291 /* For CubeArray images, we should count the number of cubes instead
2292 * of the number of faces. Fix it by dividing the (Z component) by 6.
2294 const bool is_cube_array_image
=
2295 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
2296 type
->sampler_array
;
2298 /* Copy all the components. */
2299 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
2300 for (unsigned c
= 0; c
< info
->dest_components
; ++c
) {
2301 if ((int)c
>= type
->coordinate_components()) {
2302 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
2304 } else if (c
== 1 && is_1d_array_image
) {
2305 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
2306 offset(size
, bld
, 2));
2307 } else if (c
== 2 && is_cube_array_image
) {
2308 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
,
2309 offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
2310 offset(size
, bld
, c
), brw_imm_d(6));
2312 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
2313 offset(size
, bld
, c
));
2320 case nir_intrinsic_image_samples
:
2321 /* The driver does not support multi-sampled images. */
2322 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(1));
2325 case nir_intrinsic_load_uniform
: {
2326 /* Offsets are in bytes but they should always be multiples of 4 */
2327 assert(instr
->const_index
[0] % 4 == 0);
2329 fs_reg
src(UNIFORM
, instr
->const_index
[0] / 4, dest
.type
);
2331 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
2333 /* Offsets are in bytes but they should always be multiples of 4 */
2334 assert(const_offset
->u
[0] % 4 == 0);
2335 src
.reg_offset
= const_offset
->u
[0] / 4;
2337 src
.reladdr
= new(mem_ctx
) fs_reg(get_nir_src(instr
->src
[0]));
2340 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
2341 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
2346 case nir_intrinsic_load_ubo
: {
2347 nir_const_value
*const_index
= nir_src_as_const_value(instr
->src
[0]);
2351 const unsigned index
= stage_prog_data
->binding_table
.ubo_start
+
2353 surf_index
= brw_imm_ud(index
);
2354 brw_mark_surface_used(prog_data
, index
);
2356 /* The block index is not a constant. Evaluate the index expression
2357 * per-channel and add the base UBO index; we have to select a value
2358 * from any live channel.
2360 surf_index
= vgrf(glsl_type::uint_type
);
2361 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
2362 brw_imm_ud(stage_prog_data
->binding_table
.ubo_start
));
2363 surf_index
= bld
.emit_uniformize(surf_index
);
2365 /* Assume this may touch any UBO. It would be nice to provide
2366 * a tighter bound, but the array information is already lowered away.
2368 brw_mark_surface_used(prog_data
,
2369 stage_prog_data
->binding_table
.ubo_start
+
2370 nir
->info
.num_ubos
- 1);
2373 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
2374 if (const_offset
== NULL
) {
2375 fs_reg base_offset
= retype(get_nir_src(instr
->src
[1]),
2376 BRW_REGISTER_TYPE_D
);
2378 for (int i
= 0; i
< instr
->num_components
; i
++)
2379 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
2380 base_offset
, i
* 4);
2382 fs_reg packed_consts
= vgrf(glsl_type::float_type
);
2383 packed_consts
.type
= dest
.type
;
2385 struct brw_reg const_offset_reg
= brw_imm_ud(const_offset
->u
[0] & ~15);
2386 bld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
, packed_consts
,
2387 surf_index
, const_offset_reg
);
2389 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2390 packed_consts
.set_smear(const_offset
->u
[0] % 16 / 4 + i
);
2392 /* The std140 packing rules don't allow vectors to cross 16-byte
2393 * boundaries, and a reg is 32 bytes.
2395 assert(packed_consts
.subreg_offset
< 32);
2397 bld
.MOV(dest
, packed_consts
);
2398 dest
= offset(dest
, bld
, 1);
2404 case nir_intrinsic_load_ssbo
: {
2405 assert(devinfo
->gen
>= 7);
2407 nir_const_value
*const_uniform_block
=
2408 nir_src_as_const_value(instr
->src
[0]);
2411 if (const_uniform_block
) {
2412 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
2413 const_uniform_block
->u
[0];
2414 surf_index
= brw_imm_ud(index
);
2415 brw_mark_surface_used(prog_data
, index
);
2417 surf_index
= vgrf(glsl_type::uint_type
);
2418 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
2419 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
2421 /* Assume this may touch any UBO. It would be nice to provide
2422 * a tighter bound, but the array information is already lowered away.
2424 brw_mark_surface_used(prog_data
,
2425 stage_prog_data
->binding_table
.ssbo_start
+
2426 nir
->info
.num_ssbos
- 1);
2430 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
2432 offset_reg
= brw_imm_ud(const_offset
->u
[0]);
2434 offset_reg
= get_nir_src(instr
->src
[1]);
2437 /* Read the vector */
2438 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, offset_reg
,
2440 instr
->num_components
,
2441 BRW_PREDICATE_NONE
);
2442 read_result
.type
= dest
.type
;
2443 for (int i
= 0; i
< instr
->num_components
; i
++)
2444 bld
.MOV(offset(dest
, bld
, i
), offset(read_result
, bld
, i
));
2449 case nir_intrinsic_load_shared
: {
2450 assert(devinfo
->gen
>= 7);
2452 fs_reg surf_index
= brw_imm_ud(GEN7_BTI_SLM
);
2454 /* Get the offset to read from */
2456 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
2458 offset_reg
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u
[0]);
2460 offset_reg
= vgrf(glsl_type::uint_type
);
2462 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
2463 brw_imm_ud(instr
->const_index
[0]));
2466 /* Read the vector */
2467 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, offset_reg
,
2469 instr
->num_components
,
2470 BRW_PREDICATE_NONE
);
2471 read_result
.type
= dest
.type
;
2472 for (int i
= 0; i
< instr
->num_components
; i
++)
2473 bld
.MOV(offset(dest
, bld
, i
), offset(read_result
, bld
, i
));
2478 case nir_intrinsic_store_shared
: {
2479 assert(devinfo
->gen
>= 7);
2482 fs_reg surf_index
= brw_imm_ud(GEN7_BTI_SLM
);
2485 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
2488 unsigned writemask
= instr
->const_index
[1];
2490 /* Combine groups of consecutive enabled channels in one write
2491 * message. We use ffs to find the first enabled channel and then ffs on
2492 * the bit-inverse, down-shifted writemask to determine the length of
2493 * the block of enabled bits.
2496 unsigned first_component
= ffs(writemask
) - 1;
2497 unsigned length
= ffs(~(writemask
>> first_component
)) - 1;
2500 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
2502 offset_reg
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u
[0] +
2503 4 * first_component
);
2505 offset_reg
= vgrf(glsl_type::uint_type
);
2507 retype(get_nir_src(instr
->src
[1]), BRW_REGISTER_TYPE_UD
),
2508 brw_imm_ud(instr
->const_index
[0] + 4 * first_component
));
2511 emit_untyped_write(bld
, surf_index
, offset_reg
,
2512 offset(val_reg
, bld
, first_component
),
2513 1 /* dims */, length
,
2514 BRW_PREDICATE_NONE
);
2516 /* Clear the bits in the writemask that we just wrote, then try
2517 * again to see if more channels are left.
2519 writemask
&= (15 << (first_component
+ length
));
2525 case nir_intrinsic_load_input
: {
2527 if (stage
== MESA_SHADER_VERTEX
) {
2528 src
= fs_reg(ATTR
, instr
->const_index
[0], dest
.type
);
2530 src
= offset(retype(nir_inputs
, dest
.type
), bld
,
2531 instr
->const_index
[0]);
2534 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
2535 assert(const_offset
&& "Indirect input loads not allowed");
2536 src
= offset(src
, bld
, const_offset
->u
[0]);
2538 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
2539 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
2544 case nir_intrinsic_store_ssbo
: {
2545 assert(devinfo
->gen
>= 7);
2549 nir_const_value
*const_uniform_block
=
2550 nir_src_as_const_value(instr
->src
[1]);
2551 if (const_uniform_block
) {
2552 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
2553 const_uniform_block
->u
[0];
2554 surf_index
= brw_imm_ud(index
);
2555 brw_mark_surface_used(prog_data
, index
);
2557 surf_index
= vgrf(glsl_type::uint_type
);
2558 bld
.ADD(surf_index
, get_nir_src(instr
->src
[1]),
2559 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
2561 brw_mark_surface_used(prog_data
,
2562 stage_prog_data
->binding_table
.ssbo_start
+
2563 nir
->info
.num_ssbos
- 1);
2567 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
2570 unsigned writemask
= instr
->const_index
[0];
2572 /* Combine groups of consecutive enabled channels in one write
2573 * message. We use ffs to find the first enabled channel and then ffs on
2574 * the bit-inverse, down-shifted writemask to determine the length of
2575 * the block of enabled bits.
2578 unsigned first_component
= ffs(writemask
) - 1;
2579 unsigned length
= ffs(~(writemask
>> first_component
)) - 1;
2582 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[2]);
2584 offset_reg
= brw_imm_ud(const_offset
->u
[0] + 4 * first_component
);
2586 offset_reg
= vgrf(glsl_type::uint_type
);
2588 retype(get_nir_src(instr
->src
[2]), BRW_REGISTER_TYPE_UD
),
2589 brw_imm_ud(4 * first_component
));
2592 emit_untyped_write(bld
, surf_index
, offset_reg
,
2593 offset(val_reg
, bld
, first_component
),
2594 1 /* dims */, length
,
2595 BRW_PREDICATE_NONE
);
2597 /* Clear the bits in the writemask that we just wrote, then try
2598 * again to see if more channels are left.
2600 writemask
&= (15 << (first_component
+ length
));
2605 case nir_intrinsic_store_output
: {
2606 fs_reg src
= get_nir_src(instr
->src
[0]);
2607 fs_reg new_dest
= offset(retype(nir_outputs
, src
.type
), bld
,
2608 instr
->const_index
[0]);
2610 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
2611 assert(const_offset
&& "Indirect output stores not allowed");
2612 new_dest
= offset(new_dest
, bld
, const_offset
->u
[0]);
2614 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
2615 bld
.MOV(offset(new_dest
, bld
, j
), offset(src
, bld
, j
));
2620 case nir_intrinsic_ssbo_atomic_add
:
2621 nir_emit_ssbo_atomic(bld
, BRW_AOP_ADD
, instr
);
2623 case nir_intrinsic_ssbo_atomic_imin
:
2624 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMIN
, instr
);
2626 case nir_intrinsic_ssbo_atomic_umin
:
2627 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMIN
, instr
);
2629 case nir_intrinsic_ssbo_atomic_imax
:
2630 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMAX
, instr
);
2632 case nir_intrinsic_ssbo_atomic_umax
:
2633 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMAX
, instr
);
2635 case nir_intrinsic_ssbo_atomic_and
:
2636 nir_emit_ssbo_atomic(bld
, BRW_AOP_AND
, instr
);
2638 case nir_intrinsic_ssbo_atomic_or
:
2639 nir_emit_ssbo_atomic(bld
, BRW_AOP_OR
, instr
);
2641 case nir_intrinsic_ssbo_atomic_xor
:
2642 nir_emit_ssbo_atomic(bld
, BRW_AOP_XOR
, instr
);
2644 case nir_intrinsic_ssbo_atomic_exchange
:
2645 nir_emit_ssbo_atomic(bld
, BRW_AOP_MOV
, instr
);
2647 case nir_intrinsic_ssbo_atomic_comp_swap
:
2648 nir_emit_ssbo_atomic(bld
, BRW_AOP_CMPWR
, instr
);
2651 case nir_intrinsic_get_buffer_size
: {
2652 nir_const_value
*const_uniform_block
= nir_src_as_const_value(instr
->src
[0]);
2653 unsigned ssbo_index
= const_uniform_block
? const_uniform_block
->u
[0] : 0;
2654 int reg_width
= dispatch_width
/ 8;
2657 fs_reg source
= brw_imm_d(0);
2659 int mlen
= 1 * reg_width
;
2661 /* A resinfo's sampler message is used to get the buffer size.
2662 * The SIMD8's writeback message consists of four registers and
2663 * SIMD16's writeback message consists of 8 destination registers
2664 * (two per each component), although we are only interested on the
2665 * first component, where resinfo returns the buffer size for
2668 int regs_written
= 4 * mlen
;
2669 fs_reg src_payload
= fs_reg(VGRF
, alloc
.allocate(mlen
),
2670 BRW_REGISTER_TYPE_UD
);
2671 bld
.LOAD_PAYLOAD(src_payload
, &source
, 1, 0);
2672 fs_reg buffer_size
= fs_reg(VGRF
, alloc
.allocate(regs_written
),
2673 BRW_REGISTER_TYPE_UD
);
2674 const unsigned index
= prog_data
->binding_table
.ssbo_start
+ ssbo_index
;
2675 fs_inst
*inst
= bld
.emit(FS_OPCODE_GET_BUFFER_SIZE
, buffer_size
,
2676 src_payload
, brw_imm_ud(index
));
2677 inst
->header_size
= 0;
2679 inst
->regs_written
= regs_written
;
2681 bld
.MOV(retype(dest
, buffer_size
.type
), buffer_size
);
2683 brw_mark_surface_used(prog_data
, index
);
2688 unreachable("unknown intrinsic");
2693 fs_visitor::nir_emit_ssbo_atomic(const fs_builder
&bld
,
2694 int op
, nir_intrinsic_instr
*instr
)
2697 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2698 dest
= get_nir_dest(instr
->dest
);
2701 nir_const_value
*const_surface
= nir_src_as_const_value(instr
->src
[0]);
2702 if (const_surface
) {
2703 unsigned surf_index
= stage_prog_data
->binding_table
.ssbo_start
+
2704 const_surface
->u
[0];
2705 surface
= brw_imm_ud(surf_index
);
2706 brw_mark_surface_used(prog_data
, surf_index
);
2708 surface
= vgrf(glsl_type::uint_type
);
2709 bld
.ADD(surface
, get_nir_src(instr
->src
[0]),
2710 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
2712 /* Assume this may touch any SSBO. This is the same we do for other
2713 * UBO/SSBO accesses with non-constant surface.
2715 brw_mark_surface_used(prog_data
,
2716 stage_prog_data
->binding_table
.ssbo_start
+
2717 nir
->info
.num_ssbos
- 1);
2720 fs_reg offset
= get_nir_src(instr
->src
[1]);
2721 fs_reg data1
= get_nir_src(instr
->src
[2]);
2723 if (op
== BRW_AOP_CMPWR
)
2724 data2
= get_nir_src(instr
->src
[3]);
2726 /* Emit the actual atomic operation operation */
2728 fs_reg atomic_result
=
2729 surface_access::emit_untyped_atomic(bld
, surface
, offset
,
2731 1 /* dims */, 1 /* rsize */,
2733 BRW_PREDICATE_NONE
);
2734 dest
.type
= atomic_result
.type
;
2735 bld
.MOV(dest
, atomic_result
);
2739 fs_visitor::nir_emit_shared_atomic(const fs_builder
&bld
,
2740 int op
, nir_intrinsic_instr
*instr
)
2743 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2744 dest
= get_nir_dest(instr
->dest
);
2746 fs_reg surface
= brw_imm_ud(GEN7_BTI_SLM
);
2747 fs_reg offset
= get_nir_src(instr
->src
[0]);
2748 fs_reg data1
= get_nir_src(instr
->src
[1]);
2750 if (op
== BRW_AOP_CMPWR
)
2751 data2
= get_nir_src(instr
->src
[2]);
2753 /* Emit the actual atomic operation operation */
2755 fs_reg atomic_result
=
2756 surface_access::emit_untyped_atomic(bld
, surface
, offset
,
2758 1 /* dims */, 1 /* rsize */,
2760 BRW_PREDICATE_NONE
);
2761 dest
.type
= atomic_result
.type
;
2762 bld
.MOV(dest
, atomic_result
);
2766 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
2768 unsigned texture
= instr
->texture_index
;
2769 unsigned sampler
= instr
->sampler_index
;
2770 fs_reg
texture_reg(brw_imm_ud(texture
));
2771 fs_reg
sampler_reg(brw_imm_ud(sampler
));
2773 int gather_component
= instr
->component
;
2775 bool is_cube_array
= instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
2778 int lod_components
= 0;
2779 int UNUSED offset_components
= 0;
2781 fs_reg coordinate
, shadow_comparitor
, lod
, lod2
, sample_index
, mcs
, tex_offset
;
2783 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
2784 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
2785 switch (instr
->src
[i
].src_type
) {
2786 case nir_tex_src_bias
:
2787 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
2789 case nir_tex_src_comparitor
:
2790 shadow_comparitor
= retype(src
, BRW_REGISTER_TYPE_F
);
2792 case nir_tex_src_coord
:
2793 switch (instr
->op
) {
2795 case nir_texop_txf_ms
:
2796 case nir_texop_samples_identical
:
2797 coordinate
= retype(src
, BRW_REGISTER_TYPE_D
);
2800 coordinate
= retype(src
, BRW_REGISTER_TYPE_F
);
2804 case nir_tex_src_ddx
:
2805 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
2806 lod_components
= nir_tex_instr_src_size(instr
, i
);
2808 case nir_tex_src_ddy
:
2809 lod2
= retype(src
, BRW_REGISTER_TYPE_F
);
2811 case nir_tex_src_lod
:
2812 switch (instr
->op
) {
2814 lod
= retype(src
, BRW_REGISTER_TYPE_UD
);
2817 lod
= retype(src
, BRW_REGISTER_TYPE_D
);
2820 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
2824 case nir_tex_src_ms_index
:
2825 sample_index
= retype(src
, BRW_REGISTER_TYPE_UD
);
2827 case nir_tex_src_offset
:
2828 tex_offset
= retype(src
, BRW_REGISTER_TYPE_D
);
2829 if (instr
->is_array
)
2830 offset_components
= instr
->coord_components
- 1;
2832 offset_components
= instr
->coord_components
;
2834 case nir_tex_src_projector
:
2835 unreachable("should be lowered");
2837 case nir_tex_src_texture_offset
: {
2838 /* Figure out the highest possible texture index and mark it as used */
2839 uint32_t max_used
= texture
+ instr
->texture_array_size
- 1;
2840 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
< 8) {
2841 max_used
+= stage_prog_data
->binding_table
.gather_texture_start
;
2843 max_used
+= stage_prog_data
->binding_table
.texture_start
;
2845 brw_mark_surface_used(prog_data
, max_used
);
2847 /* Emit code to evaluate the actual indexing expression */
2848 texture_reg
= vgrf(glsl_type::uint_type
);
2849 bld
.ADD(texture_reg
, src
, brw_imm_ud(texture
));
2850 texture_reg
= bld
.emit_uniformize(texture_reg
);
2854 case nir_tex_src_sampler_offset
: {
2855 /* Emit code to evaluate the actual indexing expression */
2856 sampler_reg
= vgrf(glsl_type::uint_type
);
2857 bld
.ADD(sampler_reg
, src
, brw_imm_ud(sampler
));
2858 sampler_reg
= bld
.emit_uniformize(sampler_reg
);
2863 unreachable("unknown texture source");
2867 if (instr
->op
== nir_texop_txf_ms
||
2868 instr
->op
== nir_texop_samples_identical
) {
2869 if (devinfo
->gen
>= 7 &&
2870 key_tex
->compressed_multisample_layout_mask
& (1 << texture
)) {
2871 mcs
= emit_mcs_fetch(coordinate
, instr
->coord_components
, texture_reg
);
2873 mcs
= brw_imm_ud(0u);
2877 for (unsigned i
= 0; i
< 3; i
++) {
2878 if (instr
->const_offset
[i
] != 0) {
2879 assert(offset_components
== 0);
2880 tex_offset
= brw_imm_ud(brw_texture_offset(instr
->const_offset
, 3));
2885 enum glsl_base_type dest_base_type
=
2886 brw_glsl_base_type_for_nir_type (instr
->dest_type
);
2888 const glsl_type
*dest_type
=
2889 glsl_type::get_instance(dest_base_type
, nir_tex_instr_dest_size(instr
),
2892 ir_texture_opcode op
;
2893 switch (instr
->op
) {
2894 case nir_texop_lod
: op
= ir_lod
; break;
2895 case nir_texop_query_levels
: op
= ir_query_levels
; break;
2896 case nir_texop_tex
: op
= ir_tex
; break;
2897 case nir_texop_tg4
: op
= ir_tg4
; break;
2898 case nir_texop_txb
: op
= ir_txb
; break;
2899 case nir_texop_txd
: op
= ir_txd
; break;
2900 case nir_texop_txf
: op
= ir_txf
; break;
2901 case nir_texop_txf_ms
: op
= ir_txf_ms
; break;
2902 case nir_texop_txl
: op
= ir_txl
; break;
2903 case nir_texop_txs
: op
= ir_txs
; break;
2904 case nir_texop_texture_samples
: {
2905 fs_reg dst
= retype(get_nir_dest(instr
->dest
), BRW_REGISTER_TYPE_D
);
2906 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_SAMPLEINFO
, dst
,
2907 bld
.vgrf(BRW_REGISTER_TYPE_D
, 1),
2908 texture_reg
, texture_reg
);
2910 inst
->header_size
= 1;
2911 inst
->base_mrf
= -1;
2914 case nir_texop_samples_identical
: op
= ir_samples_identical
; break;
2916 unreachable("unknown texture opcode");
2919 emit_texture(op
, dest_type
, coordinate
, instr
->coord_components
,
2920 shadow_comparitor
, lod
, lod2
, lod_components
, sample_index
,
2921 tex_offset
, mcs
, gather_component
,
2922 is_cube_array
, texture
, texture_reg
, sampler
, sampler_reg
);
2924 fs_reg dest
= get_nir_dest(instr
->dest
);
2925 dest
.type
= this->result
.type
;
2926 unsigned num_components
= nir_tex_instr_dest_size(instr
);
2927 emit_percomp(bld
, fs_inst(BRW_OPCODE_MOV
, bld
.dispatch_width(),
2928 dest
, this->result
),
2929 (1 << num_components
) - 1);
2933 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
2935 switch (instr
->type
) {
2936 case nir_jump_break
:
2937 bld
.emit(BRW_OPCODE_BREAK
);
2939 case nir_jump_continue
:
2940 bld
.emit(BRW_OPCODE_CONTINUE
);
2942 case nir_jump_return
:
2943 /* This has to be the last block in the shader. We don't handle
2946 assert(nir_cf_node_next(&instr
->instr
.block
->cf_node
) == NULL
&&
2947 instr
->instr
.block
->cf_node
.parent
->type
== nir_cf_node_function
);
2950 unreachable("unknown jump");