2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "main/shaderimage.h"
27 #include "brw_fs_surface_builder.h"
29 #include "brw_program.h"
32 using namespace brw::surface_access
;
35 fs_visitor::emit_nir_code()
37 /* emit the arrays used for inputs and outputs - load/store intrinsics will
38 * be converted to reads/writes of these arrays
43 nir_emit_system_values();
45 /* get the main function and emit it */
46 nir_foreach_function(nir
, function
) {
47 assert(strcmp(function
->name
, "main") == 0);
48 assert(function
->impl
);
49 nir_emit_impl(function
->impl
);
54 fs_visitor::nir_setup_inputs()
56 if (stage
!= MESA_SHADER_FRAGMENT
)
59 nir_inputs
= bld
.vgrf(BRW_REGISTER_TYPE_F
, nir
->num_inputs
);
61 nir_foreach_variable(var
, &nir
->inputs
) {
62 fs_reg input
= offset(nir_inputs
, bld
, var
->data
.driver_location
);
65 if (var
->data
.location
== VARYING_SLOT_POS
) {
66 reg
= *emit_fragcoord_interpolation(var
->data
.pixel_center_integer
,
67 var
->data
.origin_upper_left
);
68 emit_percomp(bld
, fs_inst(BRW_OPCODE_MOV
, bld
.dispatch_width(),
70 } else if (var
->data
.location
== VARYING_SLOT_LAYER
) {
71 struct brw_reg reg
= suboffset(interp_reg(VARYING_SLOT_LAYER
, 1), 3);
72 reg
.type
= BRW_REGISTER_TYPE_D
;
73 bld
.emit(FS_OPCODE_CINTERP
, retype(input
, BRW_REGISTER_TYPE_D
), reg
);
74 } else if (var
->data
.location
== VARYING_SLOT_VIEWPORT
) {
75 struct brw_reg reg
= suboffset(interp_reg(VARYING_SLOT_VIEWPORT
, 2), 3);
76 reg
.type
= BRW_REGISTER_TYPE_D
;
77 bld
.emit(FS_OPCODE_CINTERP
, retype(input
, BRW_REGISTER_TYPE_D
), reg
);
79 int location
= var
->data
.location
;
80 emit_general_interpolation(&input
, var
->name
, var
->type
,
81 (glsl_interp_qualifier
) var
->data
.interpolation
,
82 &location
, var
->data
.centroid
,
89 fs_visitor::nir_setup_single_output_varying(fs_reg
*reg
,
90 const glsl_type
*type
,
93 if (type
->is_array() || type
->is_matrix()) {
94 const struct glsl_type
*elem_type
= glsl_get_array_element(type
);
95 const unsigned length
= glsl_get_length(type
);
97 for (unsigned i
= 0; i
< length
; i
++) {
98 nir_setup_single_output_varying(reg
, elem_type
, location
);
100 } else if (type
->is_record()) {
101 for (unsigned i
= 0; i
< type
->length
; i
++) {
102 const struct glsl_type
*field_type
= type
->fields
.structure
[i
].type
;
103 nir_setup_single_output_varying(reg
, field_type
, location
);
106 assert(type
->is_scalar() || type
->is_vector());
107 this->outputs
[*location
] = *reg
;
108 this->output_components
[*location
] = type
->vector_elements
;
109 *reg
= offset(*reg
, bld
, 4);
115 fs_visitor::nir_setup_outputs()
117 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
119 nir_outputs
= bld
.vgrf(BRW_REGISTER_TYPE_F
, nir
->num_outputs
);
121 nir_foreach_variable(var
, &nir
->outputs
) {
122 fs_reg reg
= offset(nir_outputs
, bld
, var
->data
.driver_location
);
125 case MESA_SHADER_VERTEX
:
126 case MESA_SHADER_TESS_EVAL
:
127 case MESA_SHADER_GEOMETRY
: {
128 unsigned location
= var
->data
.location
;
129 nir_setup_single_output_varying(®
, var
->type
, &location
);
132 case MESA_SHADER_FRAGMENT
:
133 if (var
->data
.index
> 0) {
134 assert(var
->data
.location
== FRAG_RESULT_DATA0
);
135 assert(var
->data
.index
== 1);
136 this->dual_src_output
= reg
;
137 this->do_dual_src
= true;
138 } else if (var
->data
.location
== FRAG_RESULT_COLOR
) {
139 /* Writing gl_FragColor outputs to all color regions. */
140 for (unsigned int i
= 0; i
< MAX2(key
->nr_color_regions
, 1); i
++) {
141 this->outputs
[i
] = reg
;
142 this->output_components
[i
] = 4;
144 } else if (var
->data
.location
== FRAG_RESULT_DEPTH
) {
145 this->frag_depth
= reg
;
146 } else if (var
->data
.location
== FRAG_RESULT_STENCIL
) {
147 this->frag_stencil
= reg
;
148 } else if (var
->data
.location
== FRAG_RESULT_SAMPLE_MASK
) {
149 this->sample_mask
= reg
;
151 int vector_elements
= var
->type
->without_array()->vector_elements
;
153 /* gl_FragData or a user-defined FS output */
154 assert(var
->data
.location
>= FRAG_RESULT_DATA0
&&
155 var
->data
.location
< FRAG_RESULT_DATA0
+BRW_MAX_DRAW_BUFFERS
);
157 /* General color output. */
158 for (unsigned int i
= 0; i
< MAX2(1, var
->type
->length
); i
++) {
159 int output
= var
->data
.location
- FRAG_RESULT_DATA0
+ i
;
160 this->outputs
[output
] = offset(reg
, bld
, vector_elements
* i
);
161 this->output_components
[output
] = vector_elements
;
166 unreachable("unhandled shader stage");
172 fs_visitor::nir_setup_uniforms()
174 if (dispatch_width
!= 8)
177 uniforms
= nir
->num_uniforms
/ 4;
179 nir_foreach_variable(var
, &nir
->uniforms
) {
180 /* UBO's and atomics don't take up space in the uniform file */
181 if (var
->interface_type
!= NULL
|| var
->type
->contains_atomic())
184 if (type_size_scalar(var
->type
) > 0)
185 param_size
[var
->data
.driver_location
/ 4] = type_size_scalar(var
->type
);
190 emit_system_values_block(nir_block
*block
, void *void_visitor
)
192 fs_visitor
*v
= (fs_visitor
*)void_visitor
;
195 nir_foreach_instr(block
, instr
) {
196 if (instr
->type
!= nir_instr_type_intrinsic
)
199 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
200 switch (intrin
->intrinsic
) {
201 case nir_intrinsic_load_vertex_id
:
202 unreachable("should be lowered by lower_vertex_id().");
204 case nir_intrinsic_load_vertex_id_zero_base
:
205 assert(v
->stage
== MESA_SHADER_VERTEX
);
206 reg
= &v
->nir_system_values
[SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
];
207 if (reg
->file
== BAD_FILE
)
208 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
);
211 case nir_intrinsic_load_base_vertex
:
212 assert(v
->stage
== MESA_SHADER_VERTEX
);
213 reg
= &v
->nir_system_values
[SYSTEM_VALUE_BASE_VERTEX
];
214 if (reg
->file
== BAD_FILE
)
215 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_BASE_VERTEX
);
218 case nir_intrinsic_load_instance_id
:
219 assert(v
->stage
== MESA_SHADER_VERTEX
);
220 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INSTANCE_ID
];
221 if (reg
->file
== BAD_FILE
)
222 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_INSTANCE_ID
);
225 case nir_intrinsic_load_base_instance
:
226 assert(v
->stage
== MESA_SHADER_VERTEX
);
227 reg
= &v
->nir_system_values
[SYSTEM_VALUE_BASE_INSTANCE
];
228 if (reg
->file
== BAD_FILE
)
229 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_BASE_INSTANCE
);
232 case nir_intrinsic_load_draw_id
:
233 assert(v
->stage
== MESA_SHADER_VERTEX
);
234 reg
= &v
->nir_system_values
[SYSTEM_VALUE_DRAW_ID
];
235 if (reg
->file
== BAD_FILE
)
236 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_DRAW_ID
);
239 case nir_intrinsic_load_invocation_id
:
240 assert(v
->stage
== MESA_SHADER_GEOMETRY
);
241 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
242 if (reg
->file
== BAD_FILE
) {
243 const fs_builder abld
= v
->bld
.annotate("gl_InvocationID", NULL
);
244 fs_reg
g1(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
245 fs_reg iid
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
246 abld
.SHR(iid
, g1
, brw_imm_ud(27u));
251 case nir_intrinsic_load_sample_pos
:
252 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
253 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
254 if (reg
->file
== BAD_FILE
)
255 *reg
= *v
->emit_samplepos_setup();
258 case nir_intrinsic_load_sample_id
:
259 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
260 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
261 if (reg
->file
== BAD_FILE
)
262 *reg
= *v
->emit_sampleid_setup();
265 case nir_intrinsic_load_sample_mask_in
:
266 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
267 assert(v
->devinfo
->gen
>= 7);
268 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
269 if (reg
->file
== BAD_FILE
)
270 *reg
= fs_reg(retype(brw_vec8_grf(v
->payload
.sample_mask_in_reg
, 0),
271 BRW_REGISTER_TYPE_D
));
274 case nir_intrinsic_load_local_invocation_id
:
275 assert(v
->stage
== MESA_SHADER_COMPUTE
);
276 reg
= &v
->nir_system_values
[SYSTEM_VALUE_LOCAL_INVOCATION_ID
];
277 if (reg
->file
== BAD_FILE
)
278 *reg
= *v
->emit_cs_local_invocation_id_setup();
281 case nir_intrinsic_load_work_group_id
:
282 assert(v
->stage
== MESA_SHADER_COMPUTE
);
283 reg
= &v
->nir_system_values
[SYSTEM_VALUE_WORK_GROUP_ID
];
284 if (reg
->file
== BAD_FILE
)
285 *reg
= *v
->emit_cs_work_group_id_setup();
288 case nir_intrinsic_load_helper_invocation
:
289 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
290 reg
= &v
->nir_system_values
[SYSTEM_VALUE_HELPER_INVOCATION
];
291 if (reg
->file
== BAD_FILE
) {
292 const fs_builder abld
=
293 v
->bld
.annotate("gl_HelperInvocation", NULL
);
295 /* On Gen6+ (gl_HelperInvocation is only exposed on Gen7+) the
296 * pixel mask is in g1.7 of the thread payload.
298 * We move the per-channel pixel enable bit to the low bit of each
299 * channel by shifting the byte containing the pixel mask by the
300 * vector immediate 0x76543210UV.
302 * The region of <1,8,0> reads only 1 byte (the pixel masks for
303 * subspans 0 and 1) in SIMD8 and an additional byte (the pixel
304 * masks for 2 and 3) in SIMD16.
306 fs_reg shifted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
308 stride(byte_offset(retype(brw_vec1_grf(1, 0),
309 BRW_REGISTER_TYPE_UB
), 28),
311 brw_imm_uv(0x76543210));
313 /* A set bit in the pixel mask means the channel is enabled, but
314 * that is the opposite of gl_HelperInvocation so we need to invert
317 * The negate source-modifier bit of logical instructions on Gen8+
318 * performs 1's complement negation, so we can use that instead of
321 fs_reg inverted
= negate(shifted
);
322 if (v
->devinfo
->gen
< 8) {
323 inverted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
324 abld
.NOT(inverted
, shifted
);
327 /* We then resolve the 0/1 result to 0/~0 boolean values by ANDing
328 * with 1 and negating.
330 fs_reg anded
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
331 abld
.AND(anded
, inverted
, brw_imm_uw(1));
333 fs_reg dst
= abld
.vgrf(BRW_REGISTER_TYPE_D
, 1);
334 abld
.MOV(dst
, negate(retype(anded
, BRW_REGISTER_TYPE_D
)));
348 fs_visitor::nir_emit_system_values()
350 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
351 for (unsigned i
= 0; i
< SYSTEM_VALUE_MAX
; i
++) {
352 nir_system_values
[i
] = fs_reg();
355 nir_foreach_function(nir
, function
) {
356 assert(strcmp(function
->name
, "main") == 0);
357 assert(function
->impl
);
358 nir_foreach_block(function
->impl
, emit_system_values_block
, this);
363 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
365 nir_locals
= ralloc_array(mem_ctx
, fs_reg
, impl
->reg_alloc
);
366 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
367 nir_locals
[i
] = fs_reg();
370 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
371 unsigned array_elems
=
372 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
373 unsigned size
= array_elems
* reg
->num_components
;
374 nir_locals
[reg
->index
] = bld
.vgrf(BRW_REGISTER_TYPE_F
, size
);
377 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
380 nir_emit_cf_list(&impl
->body
);
384 fs_visitor::nir_emit_cf_list(exec_list
*list
)
386 exec_list_validate(list
);
387 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
388 switch (node
->type
) {
390 nir_emit_if(nir_cf_node_as_if(node
));
393 case nir_cf_node_loop
:
394 nir_emit_loop(nir_cf_node_as_loop(node
));
397 case nir_cf_node_block
:
398 nir_emit_block(nir_cf_node_as_block(node
));
402 unreachable("Invalid CFG node block");
408 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
410 /* first, put the condition into f0 */
411 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
412 retype(get_nir_src(if_stmt
->condition
),
413 BRW_REGISTER_TYPE_D
));
414 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
416 bld
.IF(BRW_PREDICATE_NORMAL
);
418 nir_emit_cf_list(&if_stmt
->then_list
);
420 /* note: if the else is empty, dead CF elimination will remove it */
421 bld
.emit(BRW_OPCODE_ELSE
);
423 nir_emit_cf_list(&if_stmt
->else_list
);
425 bld
.emit(BRW_OPCODE_ENDIF
);
429 fs_visitor::nir_emit_loop(nir_loop
*loop
)
431 bld
.emit(BRW_OPCODE_DO
);
433 nir_emit_cf_list(&loop
->body
);
435 bld
.emit(BRW_OPCODE_WHILE
);
439 fs_visitor::nir_emit_block(nir_block
*block
)
441 nir_foreach_instr(block
, instr
) {
442 nir_emit_instr(instr
);
447 fs_visitor::nir_emit_instr(nir_instr
*instr
)
449 const fs_builder abld
= bld
.annotate(NULL
, instr
);
451 switch (instr
->type
) {
452 case nir_instr_type_alu
:
453 nir_emit_alu(abld
, nir_instr_as_alu(instr
));
456 case nir_instr_type_intrinsic
:
458 case MESA_SHADER_VERTEX
:
459 nir_emit_vs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
461 case MESA_SHADER_TESS_EVAL
:
462 nir_emit_tes_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
464 case MESA_SHADER_GEOMETRY
:
465 nir_emit_gs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
467 case MESA_SHADER_FRAGMENT
:
468 nir_emit_fs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
470 case MESA_SHADER_COMPUTE
:
471 nir_emit_cs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
474 unreachable("unsupported shader stage");
478 case nir_instr_type_tex
:
479 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
482 case nir_instr_type_load_const
:
483 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
486 case nir_instr_type_ssa_undef
:
487 nir_emit_undef(abld
, nir_instr_as_ssa_undef(instr
));
490 case nir_instr_type_jump
:
491 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
495 unreachable("unknown instruction type");
500 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
501 const fs_reg
&result
)
503 if (!instr
->src
[0].src
.is_ssa
||
504 instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_intrinsic
)
507 nir_intrinsic_instr
*src0
=
508 nir_instr_as_intrinsic(instr
->src
[0].src
.ssa
->parent_instr
);
510 if (src0
->intrinsic
!= nir_intrinsic_load_front_face
)
513 nir_const_value
*value1
= nir_src_as_const_value(instr
->src
[1].src
);
514 if (!value1
|| fabsf(value1
->f
[0]) != 1.0f
)
517 nir_const_value
*value2
= nir_src_as_const_value(instr
->src
[2].src
);
518 if (!value2
|| fabsf(value2
->f
[0]) != 1.0f
)
521 fs_reg tmp
= vgrf(glsl_type::int_type
);
523 if (devinfo
->gen
>= 6) {
524 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
525 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
527 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
529 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
530 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
532 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
534 * This negation looks like it's safe in practice, because bits 0:4 will
535 * surely be TRIANGLES
538 if (value1
->f
[0] == -1.0f
) {
542 tmp
.type
= BRW_REGISTER_TYPE_W
;
543 tmp
.subreg_offset
= 2;
546 bld
.OR(tmp
, g0
, brw_imm_uw(0x3f80));
548 tmp
.type
= BRW_REGISTER_TYPE_D
;
549 tmp
.subreg_offset
= 0;
552 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
553 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
555 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
557 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
558 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
560 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
562 * This negation looks like it's safe in practice, because bits 0:4 will
563 * surely be TRIANGLES
566 if (value1
->f
[0] == -1.0f
) {
570 bld
.OR(tmp
, g1_6
, brw_imm_d(0x3f800000));
572 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, brw_imm_d(0xbf800000));
578 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
)
580 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
583 fs_reg result
= get_nir_dest(instr
->dest
.dest
);
584 result
.type
= brw_type_for_nir_type(nir_op_infos
[instr
->op
].output_type
);
587 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
588 op
[i
] = get_nir_src(instr
->src
[i
].src
);
589 op
[i
].type
= brw_type_for_nir_type(nir_op_infos
[instr
->op
].input_types
[i
]);
590 op
[i
].abs
= instr
->src
[i
].abs
;
591 op
[i
].negate
= instr
->src
[i
].negate
;
594 /* We get a bunch of mov's out of the from_ssa pass and they may still
595 * be vectorized. We'll handle them as a special-case. We'll also
596 * handle vecN here because it's basically the same thing.
604 fs_reg temp
= result
;
605 bool need_extra_copy
= false;
606 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
607 if (!instr
->src
[i
].src
.is_ssa
&&
608 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
609 need_extra_copy
= true;
610 temp
= bld
.vgrf(result
.type
, 4);
615 for (unsigned i
= 0; i
< 4; i
++) {
616 if (!(instr
->dest
.write_mask
& (1 << i
)))
619 if (instr
->op
== nir_op_imov
|| instr
->op
== nir_op_fmov
) {
620 inst
= bld
.MOV(offset(temp
, bld
, i
),
621 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
623 inst
= bld
.MOV(offset(temp
, bld
, i
),
624 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
626 inst
->saturate
= instr
->dest
.saturate
;
629 /* In this case the source and destination registers were the same,
630 * so we need to insert an extra set of moves in order to deal with
633 if (need_extra_copy
) {
634 for (unsigned i
= 0; i
< 4; i
++) {
635 if (!(instr
->dest
.write_mask
& (1 << i
)))
638 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
647 /* At this point, we have dealt with any instruction that operates on
648 * more than a single channel. Therefore, we can just adjust the source
649 * and destination registers for that channel and emit the instruction.
651 unsigned channel
= 0;
652 if (nir_op_infos
[instr
->op
].output_size
== 0) {
653 /* Since NIR is doing the scalarizing for us, we should only ever see
654 * vectorized operations with a single channel.
656 assert(_mesa_bitcount(instr
->dest
.write_mask
) == 1);
657 channel
= ffs(instr
->dest
.write_mask
) - 1;
659 result
= offset(result
, bld
, channel
);
662 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
663 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
664 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
670 inst
= bld
.MOV(result
, op
[0]);
671 inst
->saturate
= instr
->dest
.saturate
;
676 bld
.MOV(result
, op
[0]);
680 /* AND(val, 0x80000000) gives the sign bit.
682 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
685 bld
.CMP(bld
.null_reg_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
687 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
688 op
[0].type
= BRW_REGISTER_TYPE_UD
;
689 result
.type
= BRW_REGISTER_TYPE_UD
;
690 bld
.AND(result_int
, op
[0], brw_imm_ud(0x80000000u
));
692 inst
= bld
.OR(result_int
, result_int
, brw_imm_ud(0x3f800000u
));
693 inst
->predicate
= BRW_PREDICATE_NORMAL
;
694 if (instr
->dest
.saturate
) {
695 inst
= bld
.MOV(result
, result
);
696 inst
->saturate
= true;
702 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
703 * -> non-negative val generates 0x00000000.
704 * Predicated OR sets 1 if val is positive.
706 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_G
);
707 bld
.ASR(result
, op
[0], brw_imm_d(31));
708 inst
= bld
.OR(result
, result
, brw_imm_d(1));
709 inst
->predicate
= BRW_PREDICATE_NORMAL
;
713 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
714 inst
->saturate
= instr
->dest
.saturate
;
718 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
719 inst
->saturate
= instr
->dest
.saturate
;
723 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
724 inst
->saturate
= instr
->dest
.saturate
;
728 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
729 inst
->saturate
= instr
->dest
.saturate
;
733 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
734 inst
->saturate
= instr
->dest
.saturate
;
738 if (fs_key
->high_quality_derivatives
) {
739 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
741 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
743 inst
->saturate
= instr
->dest
.saturate
;
745 case nir_op_fddx_fine
:
746 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
747 inst
->saturate
= instr
->dest
.saturate
;
749 case nir_op_fddx_coarse
:
750 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
751 inst
->saturate
= instr
->dest
.saturate
;
754 if (fs_key
->high_quality_derivatives
) {
755 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0],
756 brw_imm_d(fs_key
->render_to_fbo
));
758 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0],
759 brw_imm_d(fs_key
->render_to_fbo
));
761 inst
->saturate
= instr
->dest
.saturate
;
763 case nir_op_fddy_fine
:
764 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0],
765 brw_imm_d(fs_key
->render_to_fbo
));
766 inst
->saturate
= instr
->dest
.saturate
;
768 case nir_op_fddy_coarse
:
769 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0],
770 brw_imm_d(fs_key
->render_to_fbo
));
771 inst
->saturate
= instr
->dest
.saturate
;
776 inst
= bld
.ADD(result
, op
[0], op
[1]);
777 inst
->saturate
= instr
->dest
.saturate
;
781 inst
= bld
.MUL(result
, op
[0], op
[1]);
782 inst
->saturate
= instr
->dest
.saturate
;
786 bld
.MUL(result
, op
[0], op
[1]);
789 case nir_op_imul_high
:
790 case nir_op_umul_high
:
791 bld
.emit(SHADER_OPCODE_MULH
, result
, op
[0], op
[1]);
796 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
799 case nir_op_uadd_carry
:
800 unreachable("Should have been lowered by carry_to_arith().");
802 case nir_op_usub_borrow
:
803 unreachable("Should have been lowered by borrow_to_arith().");
806 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
812 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
818 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
823 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_Z
);
828 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_NZ
);
832 if (devinfo
->gen
>= 8) {
833 op
[0] = resolve_source_modifiers(op
[0]);
835 bld
.NOT(result
, op
[0]);
838 if (devinfo
->gen
>= 8) {
839 op
[0] = resolve_source_modifiers(op
[0]);
840 op
[1] = resolve_source_modifiers(op
[1]);
842 bld
.XOR(result
, op
[0], op
[1]);
845 if (devinfo
->gen
>= 8) {
846 op
[0] = resolve_source_modifiers(op
[0]);
847 op
[1] = resolve_source_modifiers(op
[1]);
849 bld
.OR(result
, op
[0], op
[1]);
852 if (devinfo
->gen
>= 8) {
853 op
[0] = resolve_source_modifiers(op
[0]);
854 op
[1] = resolve_source_modifiers(op
[1]);
856 bld
.AND(result
, op
[0], op
[1]);
862 case nir_op_ball_fequal2
:
863 case nir_op_ball_iequal2
:
864 case nir_op_ball_fequal3
:
865 case nir_op_ball_iequal3
:
866 case nir_op_ball_fequal4
:
867 case nir_op_ball_iequal4
:
868 case nir_op_bany_fnequal2
:
869 case nir_op_bany_inequal2
:
870 case nir_op_bany_fnequal3
:
871 case nir_op_bany_inequal3
:
872 case nir_op_bany_fnequal4
:
873 case nir_op_bany_inequal4
:
874 unreachable("Lowered by nir_lower_alu_reductions");
876 case nir_op_fnoise1_1
:
877 case nir_op_fnoise1_2
:
878 case nir_op_fnoise1_3
:
879 case nir_op_fnoise1_4
:
880 case nir_op_fnoise2_1
:
881 case nir_op_fnoise2_2
:
882 case nir_op_fnoise2_3
:
883 case nir_op_fnoise2_4
:
884 case nir_op_fnoise3_1
:
885 case nir_op_fnoise3_2
:
886 case nir_op_fnoise3_3
:
887 case nir_op_fnoise3_4
:
888 case nir_op_fnoise4_1
:
889 case nir_op_fnoise4_2
:
890 case nir_op_fnoise4_3
:
891 case nir_op_fnoise4_4
:
892 unreachable("not reached: should be handled by lower_noise");
895 unreachable("not reached: should be handled by ldexp_to_arith()");
898 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
899 inst
->saturate
= instr
->dest
.saturate
;
903 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
904 inst
->saturate
= instr
->dest
.saturate
;
909 bld
.MOV(result
, negate(op
[0]));
913 bld
.CMP(result
, op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
916 bld
.CMP(result
, op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
920 inst
= bld
.RNDZ(result
, op
[0]);
921 inst
->saturate
= instr
->dest
.saturate
;
925 op
[0].negate
= !op
[0].negate
;
926 fs_reg temp
= vgrf(glsl_type::float_type
);
927 bld
.RNDD(temp
, op
[0]);
929 inst
= bld
.MOV(result
, temp
);
930 inst
->saturate
= instr
->dest
.saturate
;
934 inst
= bld
.RNDD(result
, op
[0]);
935 inst
->saturate
= instr
->dest
.saturate
;
938 inst
= bld
.FRC(result
, op
[0]);
939 inst
->saturate
= instr
->dest
.saturate
;
941 case nir_op_fround_even
:
942 inst
= bld
.RNDE(result
, op
[0]);
943 inst
->saturate
= instr
->dest
.saturate
;
946 case nir_op_fquantize2f16
: {
947 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
949 /* The destination stride must be at least as big as the source stride. */
950 tmp
.type
= BRW_REGISTER_TYPE_W
;
953 bld
.emit(BRW_OPCODE_F32TO16
, tmp
, op
[0]);
954 inst
= bld
.emit(BRW_OPCODE_F16TO32
, result
, tmp
);
955 inst
->saturate
= instr
->dest
.saturate
;
962 if (devinfo
->gen
>= 6) {
963 inst
= bld
.emit(BRW_OPCODE_SEL
, result
, op
[0], op
[1]);
964 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
966 bld
.CMP(bld
.null_reg_d(), op
[0], op
[1], BRW_CONDITIONAL_L
);
967 inst
= bld
.SEL(result
, op
[0], op
[1]);
968 inst
->predicate
= BRW_PREDICATE_NORMAL
;
970 inst
->saturate
= instr
->dest
.saturate
;
976 if (devinfo
->gen
>= 6) {
977 inst
= bld
.emit(BRW_OPCODE_SEL
, result
, op
[0], op
[1]);
978 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
980 bld
.CMP(bld
.null_reg_d(), op
[0], op
[1], BRW_CONDITIONAL_GE
);
981 inst
= bld
.SEL(result
, op
[0], op
[1]);
982 inst
->predicate
= BRW_PREDICATE_NORMAL
;
984 inst
->saturate
= instr
->dest
.saturate
;
987 case nir_op_pack_snorm_2x16
:
988 case nir_op_pack_snorm_4x8
:
989 case nir_op_pack_unorm_2x16
:
990 case nir_op_pack_unorm_4x8
:
991 case nir_op_unpack_snorm_2x16
:
992 case nir_op_unpack_snorm_4x8
:
993 case nir_op_unpack_unorm_2x16
:
994 case nir_op_unpack_unorm_4x8
:
995 case nir_op_unpack_half_2x16
:
996 case nir_op_pack_half_2x16
:
997 unreachable("not reached: should be handled by lower_packing_builtins");
999 case nir_op_unpack_half_2x16_split_x
:
1000 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
, result
, op
[0]);
1001 inst
->saturate
= instr
->dest
.saturate
;
1003 case nir_op_unpack_half_2x16_split_y
:
1004 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
, result
, op
[0]);
1005 inst
->saturate
= instr
->dest
.saturate
;
1009 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
1010 inst
->saturate
= instr
->dest
.saturate
;
1013 case nir_op_bitfield_reverse
:
1014 bld
.BFREV(result
, op
[0]);
1017 case nir_op_bit_count
:
1018 bld
.CBIT(result
, op
[0]);
1021 case nir_op_ufind_msb
:
1022 case nir_op_ifind_msb
: {
1023 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
1025 /* FBH counts from the MSB side, while GLSL's findMSB() wants the count
1026 * from the LSB side. If FBH didn't return an error (0xFFFFFFFF), then
1027 * subtract the result from 31 to convert the MSB count into an LSB count.
1029 bld
.CMP(bld
.null_reg_d(), result
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
);
1031 inst
= bld
.ADD(result
, result
, brw_imm_d(31));
1032 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1033 inst
->src
[0].negate
= true;
1037 case nir_op_find_lsb
:
1038 bld
.FBL(result
, op
[0]);
1041 case nir_op_ubitfield_extract
:
1042 case nir_op_ibitfield_extract
:
1043 bld
.BFE(result
, op
[2], op
[1], op
[0]);
1046 bld
.BFI1(result
, op
[0], op
[1]);
1049 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
1052 case nir_op_bitfield_insert
:
1053 unreachable("not reached: should be handled by "
1054 "lower_instructions::bitfield_insert_to_bfm_bfi");
1057 bld
.SHL(result
, op
[0], op
[1]);
1060 bld
.ASR(result
, op
[0], op
[1]);
1063 bld
.SHR(result
, op
[0], op
[1]);
1066 case nir_op_pack_half_2x16_split
:
1067 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1071 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
1072 inst
->saturate
= instr
->dest
.saturate
;
1076 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
1077 inst
->saturate
= instr
->dest
.saturate
;
1081 if (optimize_frontfacing_ternary(instr
, result
))
1084 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1085 inst
= bld
.SEL(result
, op
[1], op
[2]);
1086 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1090 unreachable("unhandled instruction");
1093 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1094 * to sign extend the low bit to 0/~0
1096 if (devinfo
->gen
<= 5 &&
1097 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1098 fs_reg masked
= vgrf(glsl_type::int_type
);
1099 bld
.AND(masked
, result
, brw_imm_d(1));
1100 masked
.negate
= true;
1101 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
1106 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
1107 nir_load_const_instr
*instr
)
1109 fs_reg reg
= bld
.vgrf(BRW_REGISTER_TYPE_D
, instr
->def
.num_components
);
1111 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1112 bld
.MOV(offset(reg
, bld
, i
), brw_imm_d(instr
->value
.i
[i
]));
1114 nir_ssa_values
[instr
->def
.index
] = reg
;
1118 fs_visitor::nir_emit_undef(const fs_builder
&bld
, nir_ssa_undef_instr
*instr
)
1120 nir_ssa_values
[instr
->def
.index
] = bld
.vgrf(BRW_REGISTER_TYPE_D
,
1121 instr
->def
.num_components
);
1125 fs_visitor::get_nir_src(nir_src src
)
1129 reg
= nir_ssa_values
[src
.ssa
->index
];
1131 /* We don't handle indirects on locals */
1132 assert(src
.reg
.indirect
== NULL
);
1133 reg
= offset(nir_locals
[src
.reg
.reg
->index
], bld
,
1134 src
.reg
.base_offset
* src
.reg
.reg
->num_components
);
1137 /* to avoid floating-point denorm flushing problems, set the type by
1138 * default to D - instructions that need floating point semantics will set
1139 * this to F if they need to
1141 return retype(reg
, BRW_REGISTER_TYPE_D
);
1145 fs_visitor::get_nir_dest(nir_dest dest
)
1148 nir_ssa_values
[dest
.ssa
.index
] = bld
.vgrf(BRW_REGISTER_TYPE_F
,
1149 dest
.ssa
.num_components
);
1150 return nir_ssa_values
[dest
.ssa
.index
];
1152 /* We don't handle indirects on locals */
1153 assert(dest
.reg
.indirect
== NULL
);
1154 return offset(nir_locals
[dest
.reg
.reg
->index
], bld
,
1155 dest
.reg
.base_offset
* dest
.reg
.reg
->num_components
);
1160 fs_visitor::get_nir_image_deref(const nir_deref_var
*deref
)
1162 fs_reg
image(UNIFORM
, deref
->var
->data
.driver_location
/ 4,
1163 BRW_REGISTER_TYPE_UD
);
1165 for (const nir_deref
*tail
= &deref
->deref
; tail
->child
;
1166 tail
= tail
->child
) {
1167 const nir_deref_array
*deref_array
= nir_deref_as_array(tail
->child
);
1168 assert(tail
->child
->deref_type
== nir_deref_type_array
);
1169 const unsigned size
= glsl_get_length(tail
->type
);
1170 const unsigned element_size
= type_size_scalar(deref_array
->deref
.type
);
1171 const unsigned base
= MIN2(deref_array
->base_offset
, size
- 1);
1172 image
= offset(image
, bld
, base
* element_size
);
1174 if (deref_array
->deref_array_type
== nir_deref_array_type_indirect
) {
1175 fs_reg tmp
= vgrf(glsl_type::int_type
);
1177 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
) {
1178 /* IVB hangs when trying to access an invalid surface index with
1179 * the dataport. According to the spec "if the index used to
1180 * select an individual element is negative or greater than or
1181 * equal to the size of the array, the results of the operation
1182 * are undefined but may not lead to termination" -- which is one
1183 * of the possible outcomes of the hang. Clamp the index to
1184 * prevent access outside of the array bounds.
1186 bld
.emit_minmax(tmp
, retype(get_nir_src(deref_array
->indirect
),
1187 BRW_REGISTER_TYPE_UD
),
1188 brw_imm_ud(size
- base
- 1), BRW_CONDITIONAL_L
);
1190 bld
.MOV(tmp
, get_nir_src(deref_array
->indirect
));
1193 bld
.MUL(tmp
, tmp
, brw_imm_ud(element_size
* 4));
1195 bld
.ADD(*image
.reladdr
, *image
.reladdr
, tmp
);
1197 image
.reladdr
= new(mem_ctx
) fs_reg(tmp
);
1205 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
1208 for (unsigned i
= 0; i
< 4; i
++) {
1209 if (!((wr_mask
>> i
) & 1))
1212 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
1213 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
1214 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1215 if (new_inst
->src
[j
].file
== VGRF
)
1216 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
1223 * Get the matching channel register datatype for an image intrinsic of the
1224 * specified GLSL image type.
1227 get_image_base_type(const glsl_type
*type
)
1229 switch ((glsl_base_type
)type
->sampler_type
) {
1230 case GLSL_TYPE_UINT
:
1231 return BRW_REGISTER_TYPE_UD
;
1233 return BRW_REGISTER_TYPE_D
;
1234 case GLSL_TYPE_FLOAT
:
1235 return BRW_REGISTER_TYPE_F
;
1237 unreachable("Not reached.");
1242 * Get the appropriate atomic op for an image atomic intrinsic.
1245 get_image_atomic_op(nir_intrinsic_op op
, const glsl_type
*type
)
1248 case nir_intrinsic_image_atomic_add
:
1250 case nir_intrinsic_image_atomic_min
:
1251 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1252 BRW_AOP_IMIN
: BRW_AOP_UMIN
);
1253 case nir_intrinsic_image_atomic_max
:
1254 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1255 BRW_AOP_IMAX
: BRW_AOP_UMAX
);
1256 case nir_intrinsic_image_atomic_and
:
1258 case nir_intrinsic_image_atomic_or
:
1260 case nir_intrinsic_image_atomic_xor
:
1262 case nir_intrinsic_image_atomic_exchange
:
1264 case nir_intrinsic_image_atomic_comp_swap
:
1265 return BRW_AOP_CMPWR
;
1267 unreachable("Not reachable.");
1272 emit_pixel_interpolater_send(const fs_builder
&bld
,
1277 glsl_interp_qualifier interpolation
)
1283 if (src
.file
== BAD_FILE
) {
1285 payload
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 1);
1289 mlen
= 2 * bld
.dispatch_width() / 8;
1292 inst
= bld
.emit(opcode
, dst
, payload
, desc
);
1294 /* 2 floats per slot returned */
1295 inst
->regs_written
= 2 * bld
.dispatch_width() / 8;
1296 inst
->pi_noperspective
= interpolation
== INTERP_QUALIFIER_NOPERSPECTIVE
;
1302 * Computes 1 << x, given a D/UD register containing some value x.
1305 intexp2(const fs_builder
&bld
, const fs_reg
&x
)
1307 assert(x
.type
== BRW_REGISTER_TYPE_UD
|| x
.type
== BRW_REGISTER_TYPE_D
);
1309 fs_reg result
= bld
.vgrf(x
.type
, 1);
1310 fs_reg one
= bld
.vgrf(x
.type
, 1);
1312 bld
.MOV(one
, retype(brw_imm_d(1), one
.type
));
1313 bld
.SHL(result
, one
, x
);
1318 fs_visitor::emit_gs_end_primitive(const nir_src
&vertex_count_nir_src
)
1320 assert(stage
== MESA_SHADER_GEOMETRY
);
1322 struct brw_gs_prog_data
*gs_prog_data
=
1323 (struct brw_gs_prog_data
*) prog_data
;
1325 /* We can only do EndPrimitive() functionality when the control data
1326 * consists of cut bits. Fortunately, the only time it isn't is when the
1327 * output type is points, in which case EndPrimitive() is a no-op.
1329 if (gs_prog_data
->control_data_format
!=
1330 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT
) {
1334 /* Cut bits use one bit per vertex. */
1335 assert(gs_compile
->control_data_bits_per_vertex
== 1);
1337 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1338 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1340 /* Cut bit n should be set to 1 if EndPrimitive() was called after emitting
1341 * vertex n, 0 otherwise. So all we need to do here is mark bit
1342 * (vertex_count - 1) % 32 in the cut_bits register to indicate that
1343 * EndPrimitive() was called after emitting vertex (vertex_count - 1);
1344 * vec4_gs_visitor::emit_control_data_bits() will take care of the rest.
1346 * Note that if EndPrimitive() is called before emitting any vertices, this
1347 * will cause us to set bit 31 of the control_data_bits register to 1.
1348 * That's fine because:
1350 * - If max_vertices < 32, then vertex number 31 (zero-based) will never be
1351 * output, so the hardware will ignore cut bit 31.
1353 * - If max_vertices == 32, then vertex number 31 is guaranteed to be the
1354 * last vertex, so setting cut bit 31 has no effect (since the primitive
1355 * is automatically ended when the GS terminates).
1357 * - If max_vertices > 32, then the ir_emit_vertex visitor will reset the
1358 * control_data_bits register to 0 when the first vertex is emitted.
1361 const fs_builder abld
= bld
.annotate("end primitive");
1363 /* control_data_bits |= 1 << ((vertex_count - 1) % 32) */
1364 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1365 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1366 fs_reg mask
= intexp2(abld
, prev_count
);
1367 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1368 * attention to the lower 5 bits of its second source argument, so on this
1369 * architecture, 1 << (vertex_count - 1) is equivalent to 1 <<
1370 * ((vertex_count - 1) % 32).
1372 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1376 fs_visitor::emit_gs_control_data_bits(const fs_reg
&vertex_count
)
1378 assert(stage
== MESA_SHADER_GEOMETRY
);
1379 assert(gs_compile
->control_data_bits_per_vertex
!= 0);
1381 struct brw_gs_prog_data
*gs_prog_data
=
1382 (struct brw_gs_prog_data
*) prog_data
;
1384 const fs_builder abld
= bld
.annotate("emit control data bits");
1385 const fs_builder fwa_bld
= bld
.exec_all();
1387 /* We use a single UD register to accumulate control data bits (32 bits
1388 * for each of the SIMD8 channels). So we need to write a DWord (32 bits)
1391 * Unfortunately, the URB_WRITE_SIMD8 message uses 128-bit (OWord) offsets.
1392 * We have select a 128-bit group via the Global and Per-Slot Offsets, then
1393 * use the Channel Mask phase to enable/disable which DWord within that
1394 * group to write. (Remember, different SIMD8 channels may have emitted
1395 * different numbers of vertices, so we may need per-slot offsets.)
1397 * Channel masking presents an annoying problem: we may have to replicate
1398 * the data up to 4 times:
1400 * Msg = Handles, Per-Slot Offsets, Channel Masks, Data, Data, Data, Data.
1402 * To avoid penalizing shaders that emit a small number of vertices, we
1403 * can avoid these sometimes: if the size of the control data header is
1404 * <= 128 bits, then there is only 1 OWord. All SIMD8 channels will land
1405 * land in the same 128-bit group, so we can skip per-slot offsets.
1407 * Similarly, if the control data header is <= 32 bits, there is only one
1408 * DWord, so we can skip channel masks.
1410 enum opcode opcode
= SHADER_OPCODE_URB_WRITE_SIMD8
;
1412 fs_reg channel_mask
, per_slot_offset
;
1414 if (gs_compile
->control_data_header_size_bits
> 32) {
1415 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
1416 channel_mask
= vgrf(glsl_type::uint_type
);
1419 if (gs_compile
->control_data_header_size_bits
> 128) {
1420 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
;
1421 per_slot_offset
= vgrf(glsl_type::uint_type
);
1424 /* Figure out which DWord we're trying to write to using the formula:
1426 * dword_index = (vertex_count - 1) * bits_per_vertex / 32
1428 * Since bits_per_vertex is a power of two, and is known at compile
1429 * time, this can be optimized to:
1431 * dword_index = (vertex_count - 1) >> (6 - log2(bits_per_vertex))
1433 if (opcode
!= SHADER_OPCODE_URB_WRITE_SIMD8
) {
1434 fs_reg dword_index
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1435 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1436 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1437 unsigned log2_bits_per_vertex
=
1438 _mesa_fls(gs_compile
->control_data_bits_per_vertex
);
1439 abld
.SHR(dword_index
, prev_count
, brw_imm_ud(6u - log2_bits_per_vertex
));
1441 if (per_slot_offset
.file
!= BAD_FILE
) {
1442 /* Set the per-slot offset to dword_index / 4, so that we'll write to
1443 * the appropriate OWord within the control data header.
1445 abld
.SHR(per_slot_offset
, dword_index
, brw_imm_ud(2u));
1448 /* Set the channel masks to 1 << (dword_index % 4), so that we'll
1449 * write to the appropriate DWORD within the OWORD.
1451 fs_reg channel
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1452 fwa_bld
.AND(channel
, dword_index
, brw_imm_ud(3u));
1453 channel_mask
= intexp2(fwa_bld
, channel
);
1454 /* Then the channel masks need to be in bits 23:16. */
1455 fwa_bld
.SHL(channel_mask
, channel_mask
, brw_imm_ud(16u));
1458 /* Store the control data bits in the message payload and send it. */
1460 if (channel_mask
.file
!= BAD_FILE
)
1461 mlen
+= 4; /* channel masks, plus 3 extra copies of the data */
1462 if (per_slot_offset
.file
!= BAD_FILE
)
1465 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
1466 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, mlen
);
1468 sources
[i
++] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1469 if (per_slot_offset
.file
!= BAD_FILE
)
1470 sources
[i
++] = per_slot_offset
;
1471 if (channel_mask
.file
!= BAD_FILE
)
1472 sources
[i
++] = channel_mask
;
1474 sources
[i
++] = this->control_data_bits
;
1477 abld
.LOAD_PAYLOAD(payload
, sources
, mlen
, mlen
);
1478 fs_inst
*inst
= abld
.emit(opcode
, reg_undef
, payload
);
1480 /* We need to increment Global Offset by 256-bits to make room for
1481 * Broadwell's extra "Vertex Count" payload at the beginning of the
1482 * URB entry. Since this is an OWord message, Global Offset is counted
1483 * in 128-bit units, so we must set it to 2.
1485 if (gs_prog_data
->static_vertex_count
== -1)
1490 fs_visitor::set_gs_stream_control_data_bits(const fs_reg
&vertex_count
,
1493 /* control_data_bits |= stream_id << ((2 * (vertex_count - 1)) % 32) */
1495 /* Note: we are calling this *before* increasing vertex_count, so
1496 * this->vertex_count == vertex_count - 1 in the formula above.
1499 /* Stream mode uses 2 bits per vertex */
1500 assert(gs_compile
->control_data_bits_per_vertex
== 2);
1502 /* Must be a valid stream */
1503 assert(stream_id
>= 0 && stream_id
< MAX_VERTEX_STREAMS
);
1505 /* Control data bits are initialized to 0 so we don't have to set any
1506 * bits when sending vertices to stream 0.
1511 const fs_builder abld
= bld
.annotate("set stream control data bits", NULL
);
1513 /* reg::sid = stream_id */
1514 fs_reg sid
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1515 abld
.MOV(sid
, brw_imm_ud(stream_id
));
1517 /* reg:shift_count = 2 * (vertex_count - 1) */
1518 fs_reg shift_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1519 abld
.SHL(shift_count
, vertex_count
, brw_imm_ud(1u));
1521 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1522 * attention to the lower 5 bits of its second source argument, so on this
1523 * architecture, stream_id << 2 * (vertex_count - 1) is equivalent to
1524 * stream_id << ((2 * (vertex_count - 1)) % 32).
1526 fs_reg mask
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1527 abld
.SHL(mask
, sid
, shift_count
);
1528 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1532 fs_visitor::emit_gs_vertex(const nir_src
&vertex_count_nir_src
,
1535 assert(stage
== MESA_SHADER_GEOMETRY
);
1537 struct brw_gs_prog_data
*gs_prog_data
=
1538 (struct brw_gs_prog_data
*) prog_data
;
1540 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1541 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1543 /* Haswell and later hardware ignores the "Render Stream Select" bits
1544 * from the 3DSTATE_STREAMOUT packet when the SOL stage is disabled,
1545 * and instead sends all primitives down the pipeline for rasterization.
1546 * If the SOL stage is enabled, "Render Stream Select" is honored and
1547 * primitives bound to non-zero streams are discarded after stream output.
1549 * Since the only purpose of primives sent to non-zero streams is to
1550 * be recorded by transform feedback, we can simply discard all geometry
1551 * bound to these streams when transform feedback is disabled.
1553 if (stream_id
> 0 && !nir
->info
.has_transform_feedback_varyings
)
1556 /* If we're outputting 32 control data bits or less, then we can wait
1557 * until the shader is over to output them all. Otherwise we need to
1558 * output them as we go. Now is the time to do it, since we're about to
1559 * output the vertex_count'th vertex, so it's guaranteed that the
1560 * control data bits associated with the (vertex_count - 1)th vertex are
1563 if (gs_compile
->control_data_header_size_bits
> 32) {
1564 const fs_builder abld
=
1565 bld
.annotate("emit vertex: emit control data bits");
1567 /* Only emit control data bits if we've finished accumulating a batch
1568 * of 32 bits. This is the case when:
1570 * (vertex_count * bits_per_vertex) % 32 == 0
1572 * (in other words, when the last 5 bits of vertex_count *
1573 * bits_per_vertex are 0). Assuming bits_per_vertex == 2^n for some
1574 * integer n (which is always the case, since bits_per_vertex is
1575 * always 1 or 2), this is equivalent to requiring that the last 5-n
1576 * bits of vertex_count are 0:
1578 * vertex_count & (2^(5-n) - 1) == 0
1580 * 2^(5-n) == 2^5 / 2^n == 32 / bits_per_vertex, so this is
1583 * vertex_count & (32 / bits_per_vertex - 1) == 0
1585 * TODO: If vertex_count is an immediate, we could do some of this math
1586 * at compile time...
1589 abld
.AND(bld
.null_reg_d(), vertex_count
,
1590 brw_imm_ud(32u / gs_compile
->control_data_bits_per_vertex
- 1u));
1591 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1593 abld
.IF(BRW_PREDICATE_NORMAL
);
1594 /* If vertex_count is 0, then no control data bits have been
1595 * accumulated yet, so we can skip emitting them.
1597 abld
.CMP(bld
.null_reg_d(), vertex_count
, brw_imm_ud(0u),
1598 BRW_CONDITIONAL_NEQ
);
1599 abld
.IF(BRW_PREDICATE_NORMAL
);
1600 emit_gs_control_data_bits(vertex_count
);
1601 abld
.emit(BRW_OPCODE_ENDIF
);
1603 /* Reset control_data_bits to 0 so we can start accumulating a new
1606 * Note: in the case where vertex_count == 0, this neutralizes the
1607 * effect of any call to EndPrimitive() that the shader may have
1608 * made before outputting its first vertex.
1610 inst
= abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
1611 inst
->force_writemask_all
= true;
1612 abld
.emit(BRW_OPCODE_ENDIF
);
1615 emit_urb_writes(vertex_count
);
1617 /* In stream mode we have to set control data bits for all vertices
1618 * unless we have disabled control data bits completely (which we do
1619 * do for GL_POINTS outputs that don't use streams).
1621 if (gs_compile
->control_data_header_size_bits
> 0 &&
1622 gs_prog_data
->control_data_format
==
1623 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
) {
1624 set_gs_stream_control_data_bits(vertex_count
, stream_id
);
1629 fs_visitor::emit_gs_input_load(const fs_reg
&dst
,
1630 const nir_src
&vertex_src
,
1631 unsigned base_offset
,
1632 const nir_src
&offset_src
,
1633 unsigned num_components
)
1635 struct brw_gs_prog_data
*gs_prog_data
= (struct brw_gs_prog_data
*) prog_data
;
1637 nir_const_value
*vertex_const
= nir_src_as_const_value(vertex_src
);
1638 nir_const_value
*offset_const
= nir_src_as_const_value(offset_src
);
1639 const unsigned push_reg_count
= gs_prog_data
->base
.urb_read_length
* 8;
1641 /* Offset 0 is the VUE header, which contains VARYING_SLOT_LAYER [.y],
1642 * VARYING_SLOT_VIEWPORT [.z], and VARYING_SLOT_PSIZ [.w]. Only
1643 * gl_PointSize is available as a GS input, however, so it must be that.
1645 const bool is_point_size
= (base_offset
== 0);
1647 if (offset_const
!= NULL
&& vertex_const
!= NULL
&&
1648 4 * (base_offset
+ offset_const
->u
[0]) < push_reg_count
) {
1649 int imm_offset
= (base_offset
+ offset_const
->u
[0]) * 4 +
1650 vertex_const
->u
[0] * push_reg_count
;
1651 /* This input was pushed into registers. */
1652 if (is_point_size
) {
1653 /* gl_PointSize comes in .w */
1654 assert(imm_offset
== 0);
1655 bld
.MOV(dst
, fs_reg(ATTR
, imm_offset
+ 3, dst
.type
));
1657 for (unsigned i
= 0; i
< num_components
; i
++) {
1658 bld
.MOV(offset(dst
, bld
, i
),
1659 fs_reg(ATTR
, imm_offset
+ i
, dst
.type
));
1663 /* Resort to the pull model. Ensure the VUE handles are provided. */
1664 gs_prog_data
->base
.include_vue_handles
= true;
1666 unsigned first_icp_handle
= gs_prog_data
->include_primitive_id
? 3 : 2;
1670 /* The vertex index is constant; just select the proper URB handle. */
1672 retype(brw_vec8_grf(first_icp_handle
+ vertex_const
->i
[0], 0),
1673 BRW_REGISTER_TYPE_UD
);
1675 /* The vertex index is non-constant. We need to use indirect
1676 * addressing to fetch the proper URB handle.
1678 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
1679 * indicating that channel <n> should read the handle from
1680 * DWord <n>. We convert that to bytes by multiplying by 4.
1682 * Next, we convert the vertex index to bytes by multiplying
1683 * by 32 (shifting by 5), and add the two together. This is
1684 * the final indirect byte offset.
1686 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_W
, 1);
1687 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1688 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1689 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1690 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1692 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
1693 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
1694 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
1695 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
1696 /* Convert vertex_index to bytes (multiply by 32) */
1697 bld
.SHL(vertex_offset_bytes
,
1698 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
1700 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
1702 /* Use first_icp_handle as the base offset. There is one register
1703 * of URB handles per vertex, so inform the register allocator that
1704 * we might read up to nir->info.gs.vertices_in registers.
1706 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
1707 fs_reg(brw_vec8_grf(first_icp_handle
, 0)),
1708 fs_reg(icp_offset_bytes
),
1709 brw_imm_ud(nir
->info
.gs
.vertices_in
* REG_SIZE
));
1714 /* Constant indexing - use global offset. */
1715 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
1716 inst
->offset
= base_offset
+ offset_const
->u
[0];
1717 inst
->base_mrf
= -1;
1719 inst
->regs_written
= num_components
;
1721 /* Indirect indexing - use per-slot offsets as well. */
1722 const fs_reg srcs
[] = { icp_handle
, get_nir_src(offset_src
) };
1723 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
1724 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
1726 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
, payload
);
1727 inst
->offset
= base_offset
;
1728 inst
->base_mrf
= -1;
1730 inst
->regs_written
= num_components
;
1733 if (is_point_size
) {
1734 /* Read the whole VUE header (because of alignment) and read .w. */
1735 fs_reg tmp
= bld
.vgrf(dst
.type
, 4);
1737 inst
->regs_written
= 4;
1738 bld
.MOV(dst
, offset(tmp
, bld
, 3));
1744 fs_visitor::get_indirect_offset(nir_intrinsic_instr
*instr
)
1746 nir_src
*offset_src
= nir_get_io_offset_src(instr
);
1747 nir_const_value
*const_value
= nir_src_as_const_value(*offset_src
);
1750 /* The only constant offset we should find is 0. brw_nir.c's
1751 * add_const_offset_to_base() will fold other constant offsets
1752 * into instr->const_index[0].
1754 assert(const_value
->u
[0] == 0);
1758 return get_nir_src(*offset_src
);
1762 fs_visitor::nir_emit_vs_intrinsic(const fs_builder
&bld
,
1763 nir_intrinsic_instr
*instr
)
1765 assert(stage
== MESA_SHADER_VERTEX
);
1768 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
1769 dest
= get_nir_dest(instr
->dest
);
1771 switch (instr
->intrinsic
) {
1772 case nir_intrinsic_load_vertex_id
:
1773 unreachable("should be lowered by lower_vertex_id()");
1775 case nir_intrinsic_load_vertex_id_zero_base
:
1776 case nir_intrinsic_load_base_vertex
:
1777 case nir_intrinsic_load_instance_id
:
1778 case nir_intrinsic_load_base_instance
:
1779 case nir_intrinsic_load_draw_id
: {
1780 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
1781 fs_reg val
= nir_system_values
[sv
];
1782 assert(val
.file
!= BAD_FILE
);
1783 dest
.type
= val
.type
;
1789 nir_emit_intrinsic(bld
, instr
);
1795 fs_visitor::nir_emit_tes_intrinsic(const fs_builder
&bld
,
1796 nir_intrinsic_instr
*instr
)
1798 assert(stage
== MESA_SHADER_TESS_EVAL
);
1799 struct brw_tes_prog_data
*tes_prog_data
= (struct brw_tes_prog_data
*) prog_data
;
1802 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
1803 dest
= get_nir_dest(instr
->dest
);
1805 switch (instr
->intrinsic
) {
1806 case nir_intrinsic_load_primitive_id
:
1807 bld
.MOV(dest
, fs_reg(brw_vec1_grf(0, 1)));
1809 case nir_intrinsic_load_tess_coord
:
1810 /* gl_TessCoord is part of the payload in g1-3 */
1811 for (unsigned i
= 0; i
< 3; i
++) {
1812 bld
.MOV(offset(dest
, bld
, i
), fs_reg(brw_vec8_grf(1 + i
, 0)));
1816 case nir_intrinsic_load_tess_level_outer
:
1817 /* When the TES reads gl_TessLevelOuter, we ensure that the patch header
1818 * appears as a push-model input. So, we can simply use the ATTR file
1819 * rather than issuing URB read messages. The data is stored in the
1820 * high DWords in reverse order - DWord 7 contains .x, DWord 6 contains
1823 switch (tes_prog_data
->domain
) {
1824 case BRW_TESS_DOMAIN_QUAD
:
1825 for (unsigned i
= 0; i
< 4; i
++)
1826 bld
.MOV(offset(dest
, bld
, i
), component(fs_reg(ATTR
, 0), 7 - i
));
1828 case BRW_TESS_DOMAIN_TRI
:
1829 for (unsigned i
= 0; i
< 3; i
++)
1830 bld
.MOV(offset(dest
, bld
, i
), component(fs_reg(ATTR
, 0), 7 - i
));
1832 case BRW_TESS_DOMAIN_ISOLINE
:
1833 for (unsigned i
= 0; i
< 2; i
++)
1834 bld
.MOV(offset(dest
, bld
, i
), component(fs_reg(ATTR
, 0), 7 - i
));
1839 case nir_intrinsic_load_tess_level_inner
:
1840 /* When the TES reads gl_TessLevelInner, we ensure that the patch header
1841 * appears as a push-model input. So, we can simply use the ATTR file
1842 * rather than issuing URB read messages.
1844 switch (tes_prog_data
->domain
) {
1845 case BRW_TESS_DOMAIN_QUAD
:
1846 bld
.MOV(dest
, component(fs_reg(ATTR
, 0), 3));
1847 bld
.MOV(offset(dest
, bld
, 1), component(fs_reg(ATTR
, 0), 2));
1849 case BRW_TESS_DOMAIN_TRI
:
1850 bld
.MOV(dest
, component(fs_reg(ATTR
, 0), 4));
1852 case BRW_TESS_DOMAIN_ISOLINE
:
1853 /* ignore - value is undefined */
1858 case nir_intrinsic_load_input
:
1859 case nir_intrinsic_load_per_vertex_input
: {
1860 fs_reg indirect_offset
= get_indirect_offset(instr
);
1861 unsigned imm_offset
= instr
->const_index
[0];
1864 if (indirect_offset
.file
== BAD_FILE
) {
1865 /* Arbitrarily only push up to 32 vec4 slots worth of data,
1866 * which is 16 registers (since each holds 2 vec4 slots).
1868 const unsigned max_push_slots
= 32;
1869 if (imm_offset
< max_push_slots
) {
1870 fs_reg src
= fs_reg(ATTR
, imm_offset
/ 2, dest
.type
);
1871 for (int i
= 0; i
< instr
->num_components
; i
++) {
1872 bld
.MOV(offset(dest
, bld
, i
),
1873 component(src
, 4 * (imm_offset
% 2) + i
));
1875 tes_prog_data
->base
.urb_read_length
=
1876 MAX2(tes_prog_data
->base
.urb_read_length
,
1877 DIV_ROUND_UP(imm_offset
+ 1, 2));
1879 /* Replicate the patch handle to all enabled channels */
1880 const fs_reg srcs
[] = {
1881 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)
1883 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1884 bld
.LOAD_PAYLOAD(patch_handle
, srcs
, ARRAY_SIZE(srcs
), 0);
1886 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dest
, patch_handle
);
1888 inst
->offset
= imm_offset
;
1889 inst
->base_mrf
= -1;
1890 inst
->regs_written
= instr
->num_components
;
1893 /* Indirect indexing - use per-slot offsets as well. */
1894 const fs_reg srcs
[] = {
1895 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
1898 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
1899 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
1901 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dest
, payload
);
1903 inst
->offset
= imm_offset
;
1904 inst
->base_mrf
= -1;
1905 inst
->regs_written
= instr
->num_components
;
1910 nir_emit_intrinsic(bld
, instr
);
1916 fs_visitor::nir_emit_gs_intrinsic(const fs_builder
&bld
,
1917 nir_intrinsic_instr
*instr
)
1919 assert(stage
== MESA_SHADER_GEOMETRY
);
1920 fs_reg indirect_offset
;
1923 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
1924 dest
= get_nir_dest(instr
->dest
);
1926 switch (instr
->intrinsic
) {
1927 case nir_intrinsic_load_primitive_id
:
1928 assert(stage
== MESA_SHADER_GEOMETRY
);
1929 assert(((struct brw_gs_prog_data
*)prog_data
)->include_primitive_id
);
1930 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
1931 retype(fs_reg(brw_vec8_grf(2, 0)), BRW_REGISTER_TYPE_UD
));
1934 case nir_intrinsic_load_input
:
1935 unreachable("load_input intrinsics are invalid for the GS stage");
1937 case nir_intrinsic_load_per_vertex_input
:
1938 emit_gs_input_load(dest
, instr
->src
[0], instr
->const_index
[0],
1939 instr
->src
[1], instr
->num_components
);
1942 case nir_intrinsic_emit_vertex_with_counter
:
1943 emit_gs_vertex(instr
->src
[0], instr
->const_index
[0]);
1946 case nir_intrinsic_end_primitive_with_counter
:
1947 emit_gs_end_primitive(instr
->src
[0]);
1950 case nir_intrinsic_set_vertex_count
:
1951 bld
.MOV(this->final_gs_vertex_count
, get_nir_src(instr
->src
[0]));
1954 case nir_intrinsic_load_invocation_id
: {
1955 fs_reg val
= nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
1956 assert(val
.file
!= BAD_FILE
);
1957 dest
.type
= val
.type
;
1963 nir_emit_intrinsic(bld
, instr
);
1969 fs_visitor::nir_emit_fs_intrinsic(const fs_builder
&bld
,
1970 nir_intrinsic_instr
*instr
)
1972 assert(stage
== MESA_SHADER_FRAGMENT
);
1973 struct brw_wm_prog_data
*wm_prog_data
=
1974 (struct brw_wm_prog_data
*) prog_data
;
1977 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
1978 dest
= get_nir_dest(instr
->dest
);
1980 switch (instr
->intrinsic
) {
1981 case nir_intrinsic_load_front_face
:
1982 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
1983 *emit_frontfacing_interpolation());
1986 case nir_intrinsic_load_sample_pos
: {
1987 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
1988 assert(sample_pos
.file
!= BAD_FILE
);
1989 dest
.type
= sample_pos
.type
;
1990 bld
.MOV(dest
, sample_pos
);
1991 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
1995 case nir_intrinsic_load_helper_invocation
:
1996 case nir_intrinsic_load_sample_mask_in
:
1997 case nir_intrinsic_load_sample_id
: {
1998 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
1999 fs_reg val
= nir_system_values
[sv
];
2000 assert(val
.file
!= BAD_FILE
);
2001 dest
.type
= val
.type
;
2006 case nir_intrinsic_discard
:
2007 case nir_intrinsic_discard_if
: {
2008 /* We track our discarded pixels in f0.1. By predicating on it, we can
2009 * update just the flag bits that aren't yet discarded. If there's no
2010 * condition, we emit a CMP of g0 != g0, so all currently executing
2011 * channels will get turned off.
2014 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
2015 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
2016 brw_imm_d(0), BRW_CONDITIONAL_Z
);
2018 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
2019 BRW_REGISTER_TYPE_UW
));
2020 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
2022 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
2023 cmp
->flag_subreg
= 1;
2025 if (devinfo
->gen
>= 6) {
2026 emit_discard_jump();
2031 case nir_intrinsic_interp_var_at_centroid
:
2032 case nir_intrinsic_interp_var_at_sample
:
2033 case nir_intrinsic_interp_var_at_offset
: {
2034 /* Handle ARB_gpu_shader5 interpolation intrinsics
2036 * It's worth a quick word of explanation as to why we handle the full
2037 * variable-based interpolation intrinsic rather than a lowered version
2038 * with like we do for other inputs. We have to do that because the way
2039 * we set up inputs doesn't allow us to use the already setup inputs for
2040 * interpolation. At the beginning of the shader, we go through all of
2041 * the input variables and do the initial interpolation and put it in
2042 * the nir_inputs array based on its location as determined in
2043 * nir_lower_io. If the input isn't used, dead code cleans up and
2044 * everything works fine. However, when we get to the ARB_gpu_shader5
2045 * interpolation intrinsics, we need to reinterpolate the input
2046 * differently. If we used an intrinsic that just had an index it would
2047 * only give us the offset into the nir_inputs array. However, this is
2048 * useless because that value is post-interpolation and we need
2049 * pre-interpolation. In order to get the actual location of the bits
2050 * we get from the vertex fetching hardware, we need the variable.
2052 wm_prog_data
->pulls_bary
= true;
2054 fs_reg dst_xy
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 2);
2055 const glsl_interp_qualifier interpolation
=
2056 (glsl_interp_qualifier
) instr
->variables
[0]->var
->data
.interpolation
;
2058 switch (instr
->intrinsic
) {
2059 case nir_intrinsic_interp_var_at_centroid
:
2060 emit_pixel_interpolater_send(bld
,
2061 FS_OPCODE_INTERPOLATE_AT_CENTROID
,
2068 case nir_intrinsic_interp_var_at_sample
: {
2069 nir_const_value
*const_sample
= nir_src_as_const_value(instr
->src
[0]);
2072 unsigned msg_data
= const_sample
->i
[0] << 4;
2074 emit_pixel_interpolater_send(bld
,
2075 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
2078 brw_imm_ud(msg_data
),
2081 const fs_reg sample_src
= retype(get_nir_src(instr
->src
[0]),
2082 BRW_REGISTER_TYPE_UD
);
2084 if (nir_src_is_dynamically_uniform(instr
->src
[0])) {
2085 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
2086 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
2087 bld
.exec_all().group(1, 0)
2088 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
2089 emit_pixel_interpolater_send(bld
,
2090 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
2096 /* Make a loop that sends a message to the pixel interpolater
2097 * for the sample number in each live channel. If there are
2098 * multiple channels with the same sample number then these
2099 * will be handled simultaneously with a single interation of
2102 bld
.emit(BRW_OPCODE_DO
);
2104 /* Get the next live sample number into sample_id_reg */
2105 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
2107 /* Set the flag register so that we can perform the send
2108 * message on all channels that have the same sample number
2110 bld
.CMP(bld
.null_reg_ud(),
2111 sample_src
, sample_id
,
2112 BRW_CONDITIONAL_EQ
);
2113 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
2114 bld
.exec_all().group(1, 0)
2115 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
2117 emit_pixel_interpolater_send(bld
,
2118 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
2123 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
2125 /* Continue the loop if there are any live channels left */
2126 set_predicate_inv(BRW_PREDICATE_NORMAL
,
2128 bld
.emit(BRW_OPCODE_WHILE
));
2135 case nir_intrinsic_interp_var_at_offset
: {
2136 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
2139 unsigned off_x
= MIN2((int)(const_offset
->f
[0] * 16), 7) & 0xf;
2140 unsigned off_y
= MIN2((int)(const_offset
->f
[1] * 16), 7) & 0xf;
2142 emit_pixel_interpolater_send(bld
,
2143 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
,
2146 brw_imm_ud(off_x
| (off_y
<< 4)),
2149 fs_reg src
= vgrf(glsl_type::ivec2_type
);
2150 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
2151 BRW_REGISTER_TYPE_F
);
2152 for (int i
= 0; i
< 2; i
++) {
2153 fs_reg temp
= vgrf(glsl_type::float_type
);
2154 bld
.MUL(temp
, offset(offset_src
, bld
, i
), brw_imm_f(16.0f
));
2155 fs_reg itemp
= vgrf(glsl_type::int_type
);
2156 bld
.MOV(itemp
, temp
); /* float to int */
2158 /* Clamp the upper end of the range to +7/16.
2159 * ARB_gpu_shader5 requires that we support a maximum offset
2160 * of +0.5, which isn't representable in a S0.4 value -- if
2161 * we didn't clamp it, we'd end up with -8/16, which is the
2162 * opposite of what the shader author wanted.
2164 * This is legal due to ARB_gpu_shader5's quantization
2167 * "Not all values of <offset> may be supported; x and y
2168 * offsets may be rounded to fixed-point values with the
2169 * number of fraction bits given by the
2170 * implementation-dependent constant
2171 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
2173 set_condmod(BRW_CONDITIONAL_L
,
2174 bld
.SEL(offset(src
, bld
, i
), itemp
, brw_imm_d(7)));
2177 const enum opcode opcode
= FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
;
2178 emit_pixel_interpolater_send(bld
,
2189 unreachable("Invalid intrinsic");
2192 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
2193 fs_reg src
= interp_reg(instr
->variables
[0]->var
->data
.location
, j
);
2194 src
.type
= dest
.type
;
2196 bld
.emit(FS_OPCODE_LINTERP
, dest
, dst_xy
, src
);
2197 dest
= offset(dest
, bld
, 1);
2202 nir_emit_intrinsic(bld
, instr
);
2208 fs_visitor::nir_emit_cs_intrinsic(const fs_builder
&bld
,
2209 nir_intrinsic_instr
*instr
)
2211 assert(stage
== MESA_SHADER_COMPUTE
);
2212 struct brw_cs_prog_data
*cs_prog_data
=
2213 (struct brw_cs_prog_data
*) prog_data
;
2216 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2217 dest
= get_nir_dest(instr
->dest
);
2219 switch (instr
->intrinsic
) {
2220 case nir_intrinsic_barrier
:
2222 cs_prog_data
->uses_barrier
= true;
2225 case nir_intrinsic_load_local_invocation_id
:
2226 case nir_intrinsic_load_work_group_id
: {
2227 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
2228 fs_reg val
= nir_system_values
[sv
];
2229 assert(val
.file
!= BAD_FILE
);
2230 dest
.type
= val
.type
;
2231 for (unsigned i
= 0; i
< 3; i
++)
2232 bld
.MOV(offset(dest
, bld
, i
), offset(val
, bld
, i
));
2236 case nir_intrinsic_load_num_work_groups
: {
2237 const unsigned surface
=
2238 cs_prog_data
->binding_table
.work_groups_start
;
2240 cs_prog_data
->uses_num_work_groups
= true;
2242 fs_reg surf_index
= brw_imm_ud(surface
);
2243 brw_mark_surface_used(prog_data
, surface
);
2245 /* Read the 3 GLuint components of gl_NumWorkGroups */
2246 for (unsigned i
= 0; i
< 3; i
++) {
2247 fs_reg read_result
=
2248 emit_untyped_read(bld
, surf_index
,
2250 1 /* dims */, 1 /* size */,
2251 BRW_PREDICATE_NONE
);
2252 read_result
.type
= dest
.type
;
2253 bld
.MOV(dest
, read_result
);
2254 dest
= offset(dest
, bld
, 1);
2259 case nir_intrinsic_shared_atomic_add
:
2260 nir_emit_shared_atomic(bld
, BRW_AOP_ADD
, instr
);
2262 case nir_intrinsic_shared_atomic_imin
:
2263 nir_emit_shared_atomic(bld
, BRW_AOP_IMIN
, instr
);
2265 case nir_intrinsic_shared_atomic_umin
:
2266 nir_emit_shared_atomic(bld
, BRW_AOP_UMIN
, instr
);
2268 case nir_intrinsic_shared_atomic_imax
:
2269 nir_emit_shared_atomic(bld
, BRW_AOP_IMAX
, instr
);
2271 case nir_intrinsic_shared_atomic_umax
:
2272 nir_emit_shared_atomic(bld
, BRW_AOP_UMAX
, instr
);
2274 case nir_intrinsic_shared_atomic_and
:
2275 nir_emit_shared_atomic(bld
, BRW_AOP_AND
, instr
);
2277 case nir_intrinsic_shared_atomic_or
:
2278 nir_emit_shared_atomic(bld
, BRW_AOP_OR
, instr
);
2280 case nir_intrinsic_shared_atomic_xor
:
2281 nir_emit_shared_atomic(bld
, BRW_AOP_XOR
, instr
);
2283 case nir_intrinsic_shared_atomic_exchange
:
2284 nir_emit_shared_atomic(bld
, BRW_AOP_MOV
, instr
);
2286 case nir_intrinsic_shared_atomic_comp_swap
:
2287 nir_emit_shared_atomic(bld
, BRW_AOP_CMPWR
, instr
);
2291 nir_emit_intrinsic(bld
, instr
);
2297 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
2300 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2301 dest
= get_nir_dest(instr
->dest
);
2303 switch (instr
->intrinsic
) {
2304 case nir_intrinsic_atomic_counter_inc
:
2305 case nir_intrinsic_atomic_counter_dec
:
2306 case nir_intrinsic_atomic_counter_read
: {
2307 using namespace surface_access
;
2309 /* Get the arguments of the atomic intrinsic. */
2310 const fs_reg offset
= get_nir_src(instr
->src
[0]);
2311 const unsigned surface
= (stage_prog_data
->binding_table
.abo_start
+
2312 instr
->const_index
[0]);
2315 /* Emit a surface read or atomic op. */
2316 switch (instr
->intrinsic
) {
2317 case nir_intrinsic_atomic_counter_read
:
2318 tmp
= emit_untyped_read(bld
, brw_imm_ud(surface
), offset
, 1, 1);
2321 case nir_intrinsic_atomic_counter_inc
:
2322 tmp
= emit_untyped_atomic(bld
, brw_imm_ud(surface
), offset
, fs_reg(),
2323 fs_reg(), 1, 1, BRW_AOP_INC
);
2326 case nir_intrinsic_atomic_counter_dec
:
2327 tmp
= emit_untyped_atomic(bld
, brw_imm_ud(surface
), offset
, fs_reg(),
2328 fs_reg(), 1, 1, BRW_AOP_PREDEC
);
2332 unreachable("Unreachable");
2335 /* Assign the result. */
2336 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), tmp
);
2338 /* Mark the surface as used. */
2339 brw_mark_surface_used(stage_prog_data
, surface
);
2343 case nir_intrinsic_image_load
:
2344 case nir_intrinsic_image_store
:
2345 case nir_intrinsic_image_atomic_add
:
2346 case nir_intrinsic_image_atomic_min
:
2347 case nir_intrinsic_image_atomic_max
:
2348 case nir_intrinsic_image_atomic_and
:
2349 case nir_intrinsic_image_atomic_or
:
2350 case nir_intrinsic_image_atomic_xor
:
2351 case nir_intrinsic_image_atomic_exchange
:
2352 case nir_intrinsic_image_atomic_comp_swap
: {
2353 using namespace image_access
;
2355 /* Get the referenced image variable and type. */
2356 const nir_variable
*var
= instr
->variables
[0]->var
;
2357 const glsl_type
*type
= var
->type
->without_array();
2358 const brw_reg_type base_type
= get_image_base_type(type
);
2360 /* Get some metadata from the image intrinsic. */
2361 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
2362 const unsigned arr_dims
= type
->sampler_array
? 1 : 0;
2363 const unsigned surf_dims
= type
->coordinate_components() - arr_dims
;
2364 const mesa_format format
=
2365 (var
->data
.image
.write_only
? MESA_FORMAT_NONE
:
2366 _mesa_get_shader_image_format(var
->data
.image
.format
));
2368 /* Get the arguments of the image intrinsic. */
2369 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
2370 const fs_reg addr
= retype(get_nir_src(instr
->src
[0]),
2371 BRW_REGISTER_TYPE_UD
);
2372 const fs_reg src0
= (info
->num_srcs
>= 3 ?
2373 retype(get_nir_src(instr
->src
[2]), base_type
) :
2375 const fs_reg src1
= (info
->num_srcs
>= 4 ?
2376 retype(get_nir_src(instr
->src
[3]), base_type
) :
2380 /* Emit an image load, store or atomic op. */
2381 if (instr
->intrinsic
== nir_intrinsic_image_load
)
2382 tmp
= emit_image_load(bld
, image
, addr
, surf_dims
, arr_dims
, format
);
2384 else if (instr
->intrinsic
== nir_intrinsic_image_store
)
2385 emit_image_store(bld
, image
, addr
, src0
, surf_dims
, arr_dims
, format
);
2388 tmp
= emit_image_atomic(bld
, image
, addr
, src0
, src1
,
2389 surf_dims
, arr_dims
, info
->dest_components
,
2390 get_image_atomic_op(instr
->intrinsic
, type
));
2392 /* Assign the result. */
2393 for (unsigned c
= 0; c
< info
->dest_components
; ++c
)
2394 bld
.MOV(offset(retype(dest
, base_type
), bld
, c
),
2395 offset(tmp
, bld
, c
));
2399 case nir_intrinsic_memory_barrier_atomic_counter
:
2400 case nir_intrinsic_memory_barrier_buffer
:
2401 case nir_intrinsic_memory_barrier_image
:
2402 case nir_intrinsic_memory_barrier
: {
2403 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 16 / dispatch_width
);
2404 bld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
)
2409 case nir_intrinsic_group_memory_barrier
:
2410 case nir_intrinsic_memory_barrier_shared
:
2411 /* We treat these workgroup-level barriers as no-ops. This should be
2412 * safe at present and as long as:
2414 * - Memory access instructions are not subsequently reordered by the
2415 * compiler back-end.
2417 * - All threads from a given compute shader workgroup fit within a
2418 * single subslice and therefore talk to the same HDC shared unit
2419 * what supposedly guarantees ordering and coherency between threads
2420 * from the same workgroup. This may change in the future when we
2421 * start splitting workgroups across multiple subslices.
2423 * - The context is not in fault-and-stream mode, which could cause
2424 * memory transactions (including to SLM) prior to the barrier to be
2425 * replayed after the barrier if a pagefault occurs. This shouldn't
2426 * be a problem up to and including SKL because fault-and-stream is
2427 * not usable due to hardware issues, but that's likely to change in
2432 case nir_intrinsic_shader_clock
: {
2433 /* We cannot do anything if there is an event, so ignore it for now */
2434 fs_reg shader_clock
= get_timestamp(bld
);
2435 const fs_reg srcs
[] = { shader_clock
.set_smear(0), shader_clock
.set_smear(1) };
2437 bld
.LOAD_PAYLOAD(dest
, srcs
, ARRAY_SIZE(srcs
), 0);
2441 case nir_intrinsic_image_size
: {
2442 /* Get the referenced image variable and type. */
2443 const nir_variable
*var
= instr
->variables
[0]->var
;
2444 const glsl_type
*type
= var
->type
->without_array();
2446 /* Get the size of the image. */
2447 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
2448 const fs_reg size
= offset(image
, bld
, BRW_IMAGE_PARAM_SIZE_OFFSET
);
2450 /* For 1DArray image types, the array index is stored in the Z component.
2451 * Fix this by swizzling the Z component to the Y component.
2453 const bool is_1d_array_image
=
2454 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_1D
&&
2455 type
->sampler_array
;
2457 /* For CubeArray images, we should count the number of cubes instead
2458 * of the number of faces. Fix it by dividing the (Z component) by 6.
2460 const bool is_cube_array_image
=
2461 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
2462 type
->sampler_array
;
2464 /* Copy all the components. */
2465 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
2466 for (unsigned c
= 0; c
< info
->dest_components
; ++c
) {
2467 if ((int)c
>= type
->coordinate_components()) {
2468 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
2470 } else if (c
== 1 && is_1d_array_image
) {
2471 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
2472 offset(size
, bld
, 2));
2473 } else if (c
== 2 && is_cube_array_image
) {
2474 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
,
2475 offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
2476 offset(size
, bld
, c
), brw_imm_d(6));
2478 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
2479 offset(size
, bld
, c
));
2486 case nir_intrinsic_image_samples
:
2487 /* The driver does not support multi-sampled images. */
2488 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(1));
2491 case nir_intrinsic_load_uniform
: {
2492 /* Offsets are in bytes but they should always be multiples of 4 */
2493 assert(instr
->const_index
[0] % 4 == 0);
2495 fs_reg
src(UNIFORM
, instr
->const_index
[0] / 4, dest
.type
);
2497 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
2499 /* Offsets are in bytes but they should always be multiples of 4 */
2500 assert(const_offset
->u
[0] % 4 == 0);
2501 src
.reg_offset
= const_offset
->u
[0] / 4;
2503 src
.reladdr
= new(mem_ctx
) fs_reg(get_nir_src(instr
->src
[0]));
2506 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
2507 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
2512 case nir_intrinsic_load_ubo
: {
2513 nir_const_value
*const_index
= nir_src_as_const_value(instr
->src
[0]);
2517 const unsigned index
= stage_prog_data
->binding_table
.ubo_start
+
2519 surf_index
= brw_imm_ud(index
);
2520 brw_mark_surface_used(prog_data
, index
);
2522 /* The block index is not a constant. Evaluate the index expression
2523 * per-channel and add the base UBO index; we have to select a value
2524 * from any live channel.
2526 surf_index
= vgrf(glsl_type::uint_type
);
2527 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
2528 brw_imm_ud(stage_prog_data
->binding_table
.ubo_start
));
2529 surf_index
= bld
.emit_uniformize(surf_index
);
2531 /* Assume this may touch any UBO. It would be nice to provide
2532 * a tighter bound, but the array information is already lowered away.
2534 brw_mark_surface_used(prog_data
,
2535 stage_prog_data
->binding_table
.ubo_start
+
2536 nir
->info
.num_ubos
- 1);
2539 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
2540 if (const_offset
== NULL
) {
2541 fs_reg base_offset
= retype(get_nir_src(instr
->src
[1]),
2542 BRW_REGISTER_TYPE_D
);
2544 for (int i
= 0; i
< instr
->num_components
; i
++)
2545 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
2546 base_offset
, i
* 4);
2548 fs_reg packed_consts
= vgrf(glsl_type::float_type
);
2549 packed_consts
.type
= dest
.type
;
2551 struct brw_reg const_offset_reg
= brw_imm_ud(const_offset
->u
[0] & ~15);
2552 bld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
, packed_consts
,
2553 surf_index
, const_offset_reg
);
2555 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2556 packed_consts
.set_smear(const_offset
->u
[0] % 16 / 4 + i
);
2558 /* The std140 packing rules don't allow vectors to cross 16-byte
2559 * boundaries, and a reg is 32 bytes.
2561 assert(packed_consts
.subreg_offset
< 32);
2563 bld
.MOV(dest
, packed_consts
);
2564 dest
= offset(dest
, bld
, 1);
2570 case nir_intrinsic_load_ssbo
: {
2571 assert(devinfo
->gen
>= 7);
2573 nir_const_value
*const_uniform_block
=
2574 nir_src_as_const_value(instr
->src
[0]);
2577 if (const_uniform_block
) {
2578 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
2579 const_uniform_block
->u
[0];
2580 surf_index
= brw_imm_ud(index
);
2581 brw_mark_surface_used(prog_data
, index
);
2583 surf_index
= vgrf(glsl_type::uint_type
);
2584 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
2585 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
2587 /* Assume this may touch any UBO. It would be nice to provide
2588 * a tighter bound, but the array information is already lowered away.
2590 brw_mark_surface_used(prog_data
,
2591 stage_prog_data
->binding_table
.ssbo_start
+
2592 nir
->info
.num_ssbos
- 1);
2596 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
2598 offset_reg
= brw_imm_ud(const_offset
->u
[0]);
2600 offset_reg
= get_nir_src(instr
->src
[1]);
2603 /* Read the vector */
2604 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, offset_reg
,
2606 instr
->num_components
,
2607 BRW_PREDICATE_NONE
);
2608 read_result
.type
= dest
.type
;
2609 for (int i
= 0; i
< instr
->num_components
; i
++)
2610 bld
.MOV(offset(dest
, bld
, i
), offset(read_result
, bld
, i
));
2615 case nir_intrinsic_load_shared
: {
2616 assert(devinfo
->gen
>= 7);
2618 fs_reg surf_index
= brw_imm_ud(GEN7_BTI_SLM
);
2620 /* Get the offset to read from */
2622 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
2624 offset_reg
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u
[0]);
2626 offset_reg
= vgrf(glsl_type::uint_type
);
2628 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
2629 brw_imm_ud(instr
->const_index
[0]));
2632 /* Read the vector */
2633 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, offset_reg
,
2635 instr
->num_components
,
2636 BRW_PREDICATE_NONE
);
2637 read_result
.type
= dest
.type
;
2638 for (int i
= 0; i
< instr
->num_components
; i
++)
2639 bld
.MOV(offset(dest
, bld
, i
), offset(read_result
, bld
, i
));
2644 case nir_intrinsic_store_shared
: {
2645 assert(devinfo
->gen
>= 7);
2648 fs_reg surf_index
= brw_imm_ud(GEN7_BTI_SLM
);
2651 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
2654 unsigned writemask
= instr
->const_index
[1];
2656 /* Combine groups of consecutive enabled channels in one write
2657 * message. We use ffs to find the first enabled channel and then ffs on
2658 * the bit-inverse, down-shifted writemask to determine the length of
2659 * the block of enabled bits.
2662 unsigned first_component
= ffs(writemask
) - 1;
2663 unsigned length
= ffs(~(writemask
>> first_component
)) - 1;
2666 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
2668 offset_reg
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u
[0] +
2669 4 * first_component
);
2671 offset_reg
= vgrf(glsl_type::uint_type
);
2673 retype(get_nir_src(instr
->src
[1]), BRW_REGISTER_TYPE_UD
),
2674 brw_imm_ud(instr
->const_index
[0] + 4 * first_component
));
2677 emit_untyped_write(bld
, surf_index
, offset_reg
,
2678 offset(val_reg
, bld
, first_component
),
2679 1 /* dims */, length
,
2680 BRW_PREDICATE_NONE
);
2682 /* Clear the bits in the writemask that we just wrote, then try
2683 * again to see if more channels are left.
2685 writemask
&= (15 << (first_component
+ length
));
2691 case nir_intrinsic_load_input
: {
2693 if (stage
== MESA_SHADER_VERTEX
) {
2694 src
= fs_reg(ATTR
, instr
->const_index
[0], dest
.type
);
2696 src
= offset(retype(nir_inputs
, dest
.type
), bld
,
2697 instr
->const_index
[0]);
2700 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
2701 assert(const_offset
&& "Indirect input loads not allowed");
2702 src
= offset(src
, bld
, const_offset
->u
[0]);
2704 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
2705 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
2710 case nir_intrinsic_store_ssbo
: {
2711 assert(devinfo
->gen
>= 7);
2715 nir_const_value
*const_uniform_block
=
2716 nir_src_as_const_value(instr
->src
[1]);
2717 if (const_uniform_block
) {
2718 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
2719 const_uniform_block
->u
[0];
2720 surf_index
= brw_imm_ud(index
);
2721 brw_mark_surface_used(prog_data
, index
);
2723 surf_index
= vgrf(glsl_type::uint_type
);
2724 bld
.ADD(surf_index
, get_nir_src(instr
->src
[1]),
2725 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
2727 brw_mark_surface_used(prog_data
,
2728 stage_prog_data
->binding_table
.ssbo_start
+
2729 nir
->info
.num_ssbos
- 1);
2733 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
2736 unsigned writemask
= instr
->const_index
[0];
2738 /* Combine groups of consecutive enabled channels in one write
2739 * message. We use ffs to find the first enabled channel and then ffs on
2740 * the bit-inverse, down-shifted writemask to determine the length of
2741 * the block of enabled bits.
2744 unsigned first_component
= ffs(writemask
) - 1;
2745 unsigned length
= ffs(~(writemask
>> first_component
)) - 1;
2748 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[2]);
2750 offset_reg
= brw_imm_ud(const_offset
->u
[0] + 4 * first_component
);
2752 offset_reg
= vgrf(glsl_type::uint_type
);
2754 retype(get_nir_src(instr
->src
[2]), BRW_REGISTER_TYPE_UD
),
2755 brw_imm_ud(4 * first_component
));
2758 emit_untyped_write(bld
, surf_index
, offset_reg
,
2759 offset(val_reg
, bld
, first_component
),
2760 1 /* dims */, length
,
2761 BRW_PREDICATE_NONE
);
2763 /* Clear the bits in the writemask that we just wrote, then try
2764 * again to see if more channels are left.
2766 writemask
&= (15 << (first_component
+ length
));
2771 case nir_intrinsic_store_output
: {
2772 fs_reg src
= get_nir_src(instr
->src
[0]);
2773 fs_reg new_dest
= offset(retype(nir_outputs
, src
.type
), bld
,
2774 instr
->const_index
[0]);
2776 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
2777 assert(const_offset
&& "Indirect output stores not allowed");
2778 new_dest
= offset(new_dest
, bld
, const_offset
->u
[0]);
2780 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
2781 bld
.MOV(offset(new_dest
, bld
, j
), offset(src
, bld
, j
));
2786 case nir_intrinsic_ssbo_atomic_add
:
2787 nir_emit_ssbo_atomic(bld
, BRW_AOP_ADD
, instr
);
2789 case nir_intrinsic_ssbo_atomic_imin
:
2790 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMIN
, instr
);
2792 case nir_intrinsic_ssbo_atomic_umin
:
2793 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMIN
, instr
);
2795 case nir_intrinsic_ssbo_atomic_imax
:
2796 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMAX
, instr
);
2798 case nir_intrinsic_ssbo_atomic_umax
:
2799 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMAX
, instr
);
2801 case nir_intrinsic_ssbo_atomic_and
:
2802 nir_emit_ssbo_atomic(bld
, BRW_AOP_AND
, instr
);
2804 case nir_intrinsic_ssbo_atomic_or
:
2805 nir_emit_ssbo_atomic(bld
, BRW_AOP_OR
, instr
);
2807 case nir_intrinsic_ssbo_atomic_xor
:
2808 nir_emit_ssbo_atomic(bld
, BRW_AOP_XOR
, instr
);
2810 case nir_intrinsic_ssbo_atomic_exchange
:
2811 nir_emit_ssbo_atomic(bld
, BRW_AOP_MOV
, instr
);
2813 case nir_intrinsic_ssbo_atomic_comp_swap
:
2814 nir_emit_ssbo_atomic(bld
, BRW_AOP_CMPWR
, instr
);
2817 case nir_intrinsic_get_buffer_size
: {
2818 nir_const_value
*const_uniform_block
= nir_src_as_const_value(instr
->src
[0]);
2819 unsigned ssbo_index
= const_uniform_block
? const_uniform_block
->u
[0] : 0;
2820 int reg_width
= dispatch_width
/ 8;
2823 fs_reg source
= brw_imm_d(0);
2825 int mlen
= 1 * reg_width
;
2827 /* A resinfo's sampler message is used to get the buffer size.
2828 * The SIMD8's writeback message consists of four registers and
2829 * SIMD16's writeback message consists of 8 destination registers
2830 * (two per each component), although we are only interested on the
2831 * first component, where resinfo returns the buffer size for
2834 int regs_written
= 4 * mlen
;
2835 fs_reg src_payload
= fs_reg(VGRF
, alloc
.allocate(mlen
),
2836 BRW_REGISTER_TYPE_UD
);
2837 bld
.LOAD_PAYLOAD(src_payload
, &source
, 1, 0);
2838 fs_reg buffer_size
= fs_reg(VGRF
, alloc
.allocate(regs_written
),
2839 BRW_REGISTER_TYPE_UD
);
2840 const unsigned index
= prog_data
->binding_table
.ssbo_start
+ ssbo_index
;
2841 fs_inst
*inst
= bld
.emit(FS_OPCODE_GET_BUFFER_SIZE
, buffer_size
,
2842 src_payload
, brw_imm_ud(index
));
2843 inst
->header_size
= 0;
2845 inst
->regs_written
= regs_written
;
2847 bld
.MOV(retype(dest
, buffer_size
.type
), buffer_size
);
2849 brw_mark_surface_used(prog_data
, index
);
2854 unreachable("unknown intrinsic");
2859 fs_visitor::nir_emit_ssbo_atomic(const fs_builder
&bld
,
2860 int op
, nir_intrinsic_instr
*instr
)
2863 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2864 dest
= get_nir_dest(instr
->dest
);
2867 nir_const_value
*const_surface
= nir_src_as_const_value(instr
->src
[0]);
2868 if (const_surface
) {
2869 unsigned surf_index
= stage_prog_data
->binding_table
.ssbo_start
+
2870 const_surface
->u
[0];
2871 surface
= brw_imm_ud(surf_index
);
2872 brw_mark_surface_used(prog_data
, surf_index
);
2874 surface
= vgrf(glsl_type::uint_type
);
2875 bld
.ADD(surface
, get_nir_src(instr
->src
[0]),
2876 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
2878 /* Assume this may touch any SSBO. This is the same we do for other
2879 * UBO/SSBO accesses with non-constant surface.
2881 brw_mark_surface_used(prog_data
,
2882 stage_prog_data
->binding_table
.ssbo_start
+
2883 nir
->info
.num_ssbos
- 1);
2886 fs_reg offset
= get_nir_src(instr
->src
[1]);
2887 fs_reg data1
= get_nir_src(instr
->src
[2]);
2889 if (op
== BRW_AOP_CMPWR
)
2890 data2
= get_nir_src(instr
->src
[3]);
2892 /* Emit the actual atomic operation operation */
2894 fs_reg atomic_result
=
2895 surface_access::emit_untyped_atomic(bld
, surface
, offset
,
2897 1 /* dims */, 1 /* rsize */,
2899 BRW_PREDICATE_NONE
);
2900 dest
.type
= atomic_result
.type
;
2901 bld
.MOV(dest
, atomic_result
);
2905 fs_visitor::nir_emit_shared_atomic(const fs_builder
&bld
,
2906 int op
, nir_intrinsic_instr
*instr
)
2909 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2910 dest
= get_nir_dest(instr
->dest
);
2912 fs_reg surface
= brw_imm_ud(GEN7_BTI_SLM
);
2913 fs_reg offset
= get_nir_src(instr
->src
[0]);
2914 fs_reg data1
= get_nir_src(instr
->src
[1]);
2916 if (op
== BRW_AOP_CMPWR
)
2917 data2
= get_nir_src(instr
->src
[2]);
2919 /* Emit the actual atomic operation operation */
2921 fs_reg atomic_result
=
2922 surface_access::emit_untyped_atomic(bld
, surface
, offset
,
2924 1 /* dims */, 1 /* rsize */,
2926 BRW_PREDICATE_NONE
);
2927 dest
.type
= atomic_result
.type
;
2928 bld
.MOV(dest
, atomic_result
);
2932 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
2934 unsigned texture
= instr
->texture_index
;
2935 unsigned sampler
= instr
->sampler_index
;
2936 fs_reg
texture_reg(brw_imm_ud(texture
));
2937 fs_reg
sampler_reg(brw_imm_ud(sampler
));
2939 int gather_component
= instr
->component
;
2941 bool is_cube_array
= instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
2944 int lod_components
= 0;
2945 int UNUSED offset_components
= 0;
2947 fs_reg coordinate
, shadow_comparitor
, lod
, lod2
, sample_index
, mcs
, tex_offset
;
2949 /* Our hardware requires a LOD for buffer textures */
2950 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
2953 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
2954 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
2955 switch (instr
->src
[i
].src_type
) {
2956 case nir_tex_src_bias
:
2957 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
2959 case nir_tex_src_comparitor
:
2960 shadow_comparitor
= retype(src
, BRW_REGISTER_TYPE_F
);
2962 case nir_tex_src_coord
:
2963 switch (instr
->op
) {
2965 case nir_texop_txf_ms
:
2966 case nir_texop_samples_identical
:
2967 coordinate
= retype(src
, BRW_REGISTER_TYPE_D
);
2970 coordinate
= retype(src
, BRW_REGISTER_TYPE_F
);
2974 case nir_tex_src_ddx
:
2975 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
2976 lod_components
= nir_tex_instr_src_size(instr
, i
);
2978 case nir_tex_src_ddy
:
2979 lod2
= retype(src
, BRW_REGISTER_TYPE_F
);
2981 case nir_tex_src_lod
:
2982 switch (instr
->op
) {
2984 lod
= retype(src
, BRW_REGISTER_TYPE_UD
);
2987 lod
= retype(src
, BRW_REGISTER_TYPE_D
);
2990 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
2994 case nir_tex_src_ms_index
:
2995 sample_index
= retype(src
, BRW_REGISTER_TYPE_UD
);
2997 case nir_tex_src_offset
:
2998 tex_offset
= retype(src
, BRW_REGISTER_TYPE_D
);
2999 if (instr
->is_array
)
3000 offset_components
= instr
->coord_components
- 1;
3002 offset_components
= instr
->coord_components
;
3004 case nir_tex_src_projector
:
3005 unreachable("should be lowered");
3007 case nir_tex_src_texture_offset
: {
3008 /* Figure out the highest possible texture index and mark it as used */
3009 uint32_t max_used
= texture
+ instr
->texture_array_size
- 1;
3010 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
< 8) {
3011 max_used
+= stage_prog_data
->binding_table
.gather_texture_start
;
3013 max_used
+= stage_prog_data
->binding_table
.texture_start
;
3015 brw_mark_surface_used(prog_data
, max_used
);
3017 /* Emit code to evaluate the actual indexing expression */
3018 texture_reg
= vgrf(glsl_type::uint_type
);
3019 bld
.ADD(texture_reg
, src
, brw_imm_ud(texture
));
3020 texture_reg
= bld
.emit_uniformize(texture_reg
);
3024 case nir_tex_src_sampler_offset
: {
3025 /* Emit code to evaluate the actual indexing expression */
3026 sampler_reg
= vgrf(glsl_type::uint_type
);
3027 bld
.ADD(sampler_reg
, src
, brw_imm_ud(sampler
));
3028 sampler_reg
= bld
.emit_uniformize(sampler_reg
);
3033 unreachable("unknown texture source");
3037 if (instr
->op
== nir_texop_txf_ms
||
3038 instr
->op
== nir_texop_samples_identical
) {
3039 if (devinfo
->gen
>= 7 &&
3040 key_tex
->compressed_multisample_layout_mask
& (1 << texture
)) {
3041 mcs
= emit_mcs_fetch(coordinate
, instr
->coord_components
, texture_reg
);
3043 mcs
= brw_imm_ud(0u);
3047 for (unsigned i
= 0; i
< 3; i
++) {
3048 if (instr
->const_offset
[i
] != 0) {
3049 assert(offset_components
== 0);
3050 tex_offset
= brw_imm_ud(brw_texture_offset(instr
->const_offset
, 3));
3055 enum glsl_base_type dest_base_type
=
3056 brw_glsl_base_type_for_nir_type (instr
->dest_type
);
3058 const glsl_type
*dest_type
=
3059 glsl_type::get_instance(dest_base_type
, nir_tex_instr_dest_size(instr
),
3062 ir_texture_opcode op
;
3063 switch (instr
->op
) {
3064 case nir_texop_lod
: op
= ir_lod
; break;
3065 case nir_texop_query_levels
: op
= ir_query_levels
; break;
3066 case nir_texop_tex
: op
= ir_tex
; break;
3067 case nir_texop_tg4
: op
= ir_tg4
; break;
3068 case nir_texop_txb
: op
= ir_txb
; break;
3069 case nir_texop_txd
: op
= ir_txd
; break;
3070 case nir_texop_txf
: op
= ir_txf
; break;
3071 case nir_texop_txf_ms
: op
= ir_txf_ms
; break;
3072 case nir_texop_txl
: op
= ir_txl
; break;
3073 case nir_texop_txs
: op
= ir_txs
; break;
3074 case nir_texop_texture_samples
: {
3075 fs_reg dst
= retype(get_nir_dest(instr
->dest
), BRW_REGISTER_TYPE_D
);
3076 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_SAMPLEINFO
, dst
,
3077 bld
.vgrf(BRW_REGISTER_TYPE_D
, 1),
3078 texture_reg
, texture_reg
);
3080 inst
->header_size
= 1;
3081 inst
->base_mrf
= -1;
3084 case nir_texop_samples_identical
: op
= ir_samples_identical
; break;
3086 unreachable("unknown texture opcode");
3089 emit_texture(op
, dest_type
, coordinate
, instr
->coord_components
,
3090 shadow_comparitor
, lod
, lod2
, lod_components
, sample_index
,
3091 tex_offset
, mcs
, gather_component
,
3092 is_cube_array
, texture
, texture_reg
, sampler
, sampler_reg
);
3094 fs_reg dest
= get_nir_dest(instr
->dest
);
3095 dest
.type
= this->result
.type
;
3096 unsigned num_components
= nir_tex_instr_dest_size(instr
);
3097 emit_percomp(bld
, fs_inst(BRW_OPCODE_MOV
, bld
.dispatch_width(),
3098 dest
, this->result
),
3099 (1 << num_components
) - 1);
3103 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
3105 switch (instr
->type
) {
3106 case nir_jump_break
:
3107 bld
.emit(BRW_OPCODE_BREAK
);
3109 case nir_jump_continue
:
3110 bld
.emit(BRW_OPCODE_CONTINUE
);
3112 case nir_jump_return
:
3114 unreachable("unknown jump");