2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "main/shaderimage.h"
27 #include "brw_fs_surface_builder.h"
29 #include "brw_program.h"
32 using namespace brw::surface_access
;
35 fs_visitor::emit_nir_code()
37 /* emit the arrays used for inputs and outputs - load/store intrinsics will
38 * be converted to reads/writes of these arrays
43 nir_emit_system_values();
45 /* get the main function and emit it */
46 nir_foreach_overload(nir
, overload
) {
47 assert(strcmp(overload
->function
->name
, "main") == 0);
48 assert(overload
->impl
);
49 nir_emit_impl(overload
->impl
);
54 fs_visitor::nir_setup_inputs()
56 if (stage
!= MESA_SHADER_FRAGMENT
)
59 nir_inputs
= bld
.vgrf(BRW_REGISTER_TYPE_F
, nir
->num_inputs
);
61 nir_foreach_variable(var
, &nir
->inputs
) {
62 fs_reg input
= offset(nir_inputs
, bld
, var
->data
.driver_location
);
65 if (var
->data
.location
== VARYING_SLOT_POS
) {
66 reg
= *emit_fragcoord_interpolation(var
->data
.pixel_center_integer
,
67 var
->data
.origin_upper_left
);
68 emit_percomp(bld
, fs_inst(BRW_OPCODE_MOV
, bld
.dispatch_width(),
70 } else if (var
->data
.location
== VARYING_SLOT_LAYER
) {
71 struct brw_reg reg
= suboffset(interp_reg(VARYING_SLOT_LAYER
, 1), 3);
72 reg
.type
= BRW_REGISTER_TYPE_D
;
73 bld
.emit(FS_OPCODE_CINTERP
, retype(input
, BRW_REGISTER_TYPE_D
), reg
);
74 } else if (var
->data
.location
== VARYING_SLOT_VIEWPORT
) {
75 struct brw_reg reg
= suboffset(interp_reg(VARYING_SLOT_VIEWPORT
, 2), 3);
76 reg
.type
= BRW_REGISTER_TYPE_D
;
77 bld
.emit(FS_OPCODE_CINTERP
, retype(input
, BRW_REGISTER_TYPE_D
), reg
);
79 int location
= var
->data
.location
;
80 emit_general_interpolation(&input
, var
->name
, var
->type
,
81 (glsl_interp_qualifier
) var
->data
.interpolation
,
82 &location
, var
->data
.centroid
,
89 fs_visitor::nir_setup_outputs()
91 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
93 nir_outputs
= bld
.vgrf(BRW_REGISTER_TYPE_F
, nir
->num_outputs
);
95 nir_foreach_variable(var
, &nir
->outputs
) {
96 fs_reg reg
= offset(nir_outputs
, bld
, var
->data
.driver_location
);
98 int vector_elements
= var
->type
->without_array()->vector_elements
;
101 case MESA_SHADER_VERTEX
:
102 case MESA_SHADER_GEOMETRY
:
103 for (int i
= 0; i
< type_size_vec4(var
->type
); i
++) {
104 int output
= var
->data
.location
+ i
;
105 this->outputs
[output
] = offset(reg
, bld
, 4 * i
);
106 this->output_components
[output
] = vector_elements
;
109 case MESA_SHADER_FRAGMENT
:
110 if (var
->data
.index
> 0) {
111 assert(var
->data
.location
== FRAG_RESULT_DATA0
);
112 assert(var
->data
.index
== 1);
113 this->dual_src_output
= reg
;
114 this->do_dual_src
= true;
115 } else if (var
->data
.location
== FRAG_RESULT_COLOR
) {
116 /* Writing gl_FragColor outputs to all color regions. */
117 for (unsigned int i
= 0; i
< MAX2(key
->nr_color_regions
, 1); i
++) {
118 this->outputs
[i
] = reg
;
119 this->output_components
[i
] = 4;
121 } else if (var
->data
.location
== FRAG_RESULT_DEPTH
) {
122 this->frag_depth
= reg
;
123 } else if (var
->data
.location
== FRAG_RESULT_STENCIL
) {
124 this->frag_stencil
= reg
;
125 } else if (var
->data
.location
== FRAG_RESULT_SAMPLE_MASK
) {
126 this->sample_mask
= reg
;
128 /* gl_FragData or a user-defined FS output */
129 assert(var
->data
.location
>= FRAG_RESULT_DATA0
&&
130 var
->data
.location
< FRAG_RESULT_DATA0
+BRW_MAX_DRAW_BUFFERS
);
132 /* General color output. */
133 for (unsigned int i
= 0; i
< MAX2(1, var
->type
->length
); i
++) {
134 int output
= var
->data
.location
- FRAG_RESULT_DATA0
+ i
;
135 this->outputs
[output
] = offset(reg
, bld
, vector_elements
* i
);
136 this->output_components
[output
] = vector_elements
;
141 unreachable("unhandled shader stage");
147 fs_visitor::nir_setup_uniforms()
149 if (dispatch_width
!= 8)
152 uniforms
= nir
->num_uniforms
;
154 nir_foreach_variable(var
, &nir
->uniforms
) {
155 /* UBO's and atomics don't take up space in the uniform file */
156 if (var
->interface_type
!= NULL
|| var
->type
->contains_atomic())
159 if (type_size_scalar(var
->type
) > 0)
160 param_size
[var
->data
.driver_location
] = type_size_scalar(var
->type
);
165 emit_system_values_block(nir_block
*block
, void *void_visitor
)
167 fs_visitor
*v
= (fs_visitor
*)void_visitor
;
170 nir_foreach_instr(block
, instr
) {
171 if (instr
->type
!= nir_instr_type_intrinsic
)
174 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
175 switch (intrin
->intrinsic
) {
176 case nir_intrinsic_load_vertex_id
:
177 unreachable("should be lowered by lower_vertex_id().");
179 case nir_intrinsic_load_vertex_id_zero_base
:
180 assert(v
->stage
== MESA_SHADER_VERTEX
);
181 reg
= &v
->nir_system_values
[SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
];
182 if (reg
->file
== BAD_FILE
)
183 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
);
186 case nir_intrinsic_load_base_vertex
:
187 assert(v
->stage
== MESA_SHADER_VERTEX
);
188 reg
= &v
->nir_system_values
[SYSTEM_VALUE_BASE_VERTEX
];
189 if (reg
->file
== BAD_FILE
)
190 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_BASE_VERTEX
);
193 case nir_intrinsic_load_instance_id
:
194 assert(v
->stage
== MESA_SHADER_VERTEX
);
195 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INSTANCE_ID
];
196 if (reg
->file
== BAD_FILE
)
197 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_INSTANCE_ID
);
200 case nir_intrinsic_load_invocation_id
:
201 assert(v
->stage
== MESA_SHADER_GEOMETRY
);
202 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
203 if (reg
->file
== BAD_FILE
) {
204 const fs_builder abld
= v
->bld
.annotate("gl_InvocationID", NULL
);
205 fs_reg
g1(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
206 fs_reg iid
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
207 abld
.SHR(iid
, g1
, brw_imm_ud(27u));
212 case nir_intrinsic_load_sample_pos
:
213 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
214 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
215 if (reg
->file
== BAD_FILE
)
216 *reg
= *v
->emit_samplepos_setup();
219 case nir_intrinsic_load_sample_id
:
220 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
221 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
222 if (reg
->file
== BAD_FILE
)
223 *reg
= *v
->emit_sampleid_setup();
226 case nir_intrinsic_load_sample_mask_in
:
227 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
228 assert(v
->devinfo
->gen
>= 7);
229 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
230 if (reg
->file
== BAD_FILE
)
231 *reg
= fs_reg(retype(brw_vec8_grf(v
->payload
.sample_mask_in_reg
, 0),
232 BRW_REGISTER_TYPE_D
));
235 case nir_intrinsic_load_local_invocation_id
:
236 assert(v
->stage
== MESA_SHADER_COMPUTE
);
237 reg
= &v
->nir_system_values
[SYSTEM_VALUE_LOCAL_INVOCATION_ID
];
238 if (reg
->file
== BAD_FILE
)
239 *reg
= *v
->emit_cs_local_invocation_id_setup();
242 case nir_intrinsic_load_work_group_id
:
243 assert(v
->stage
== MESA_SHADER_COMPUTE
);
244 reg
= &v
->nir_system_values
[SYSTEM_VALUE_WORK_GROUP_ID
];
245 if (reg
->file
== BAD_FILE
)
246 *reg
= *v
->emit_cs_work_group_id_setup();
249 case nir_intrinsic_load_helper_invocation
:
250 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
251 reg
= &v
->nir_system_values
[SYSTEM_VALUE_HELPER_INVOCATION
];
252 if (reg
->file
== BAD_FILE
) {
253 const fs_builder abld
=
254 v
->bld
.annotate("gl_HelperInvocation", NULL
);
256 /* On Gen6+ (gl_HelperInvocation is only exposed on Gen7+) the
257 * pixel mask is in g1.7 of the thread payload.
259 * We move the per-channel pixel enable bit to the low bit of each
260 * channel by shifting the byte containing the pixel mask by the
261 * vector immediate 0x76543210UV.
263 * The region of <1,8,0> reads only 1 byte (the pixel masks for
264 * subspans 0 and 1) in SIMD8 and an additional byte (the pixel
265 * masks for 2 and 3) in SIMD16.
267 fs_reg shifted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
269 stride(byte_offset(retype(brw_vec1_grf(1, 0),
270 BRW_REGISTER_TYPE_UB
), 28),
272 brw_imm_uv(0x76543210));
274 /* A set bit in the pixel mask means the channel is enabled, but
275 * that is the opposite of gl_HelperInvocation so we need to invert
278 * The negate source-modifier bit of logical instructions on Gen8+
279 * performs 1's complement negation, so we can use that instead of
282 fs_reg inverted
= negate(shifted
);
283 if (v
->devinfo
->gen
< 8) {
284 inverted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
285 abld
.NOT(inverted
, shifted
);
288 /* We then resolve the 0/1 result to 0/~0 boolean values by ANDing
289 * with 1 and negating.
291 fs_reg anded
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
292 abld
.AND(anded
, inverted
, brw_imm_uw(1));
294 fs_reg dst
= abld
.vgrf(BRW_REGISTER_TYPE_D
, 1);
295 abld
.MOV(dst
, negate(retype(anded
, BRW_REGISTER_TYPE_D
)));
309 fs_visitor::nir_emit_system_values()
311 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
312 for (unsigned i
= 0; i
< SYSTEM_VALUE_MAX
; i
++) {
313 nir_system_values
[i
] = fs_reg();
316 nir_foreach_overload(nir
, overload
) {
317 assert(strcmp(overload
->function
->name
, "main") == 0);
318 assert(overload
->impl
);
319 nir_foreach_block(overload
->impl
, emit_system_values_block
, this);
324 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
326 nir_locals
= ralloc_array(mem_ctx
, fs_reg
, impl
->reg_alloc
);
327 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
328 nir_locals
[i
] = fs_reg();
331 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
332 unsigned array_elems
=
333 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
334 unsigned size
= array_elems
* reg
->num_components
;
335 nir_locals
[reg
->index
] = bld
.vgrf(BRW_REGISTER_TYPE_F
, size
);
338 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
341 nir_emit_cf_list(&impl
->body
);
345 fs_visitor::nir_emit_cf_list(exec_list
*list
)
347 exec_list_validate(list
);
348 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
349 switch (node
->type
) {
351 nir_emit_if(nir_cf_node_as_if(node
));
354 case nir_cf_node_loop
:
355 nir_emit_loop(nir_cf_node_as_loop(node
));
358 case nir_cf_node_block
:
359 nir_emit_block(nir_cf_node_as_block(node
));
363 unreachable("Invalid CFG node block");
369 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
371 /* first, put the condition into f0 */
372 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
373 retype(get_nir_src(if_stmt
->condition
),
374 BRW_REGISTER_TYPE_D
));
375 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
377 bld
.IF(BRW_PREDICATE_NORMAL
);
379 nir_emit_cf_list(&if_stmt
->then_list
);
381 /* note: if the else is empty, dead CF elimination will remove it */
382 bld
.emit(BRW_OPCODE_ELSE
);
384 nir_emit_cf_list(&if_stmt
->else_list
);
386 bld
.emit(BRW_OPCODE_ENDIF
);
390 fs_visitor::nir_emit_loop(nir_loop
*loop
)
392 bld
.emit(BRW_OPCODE_DO
);
394 nir_emit_cf_list(&loop
->body
);
396 bld
.emit(BRW_OPCODE_WHILE
);
400 fs_visitor::nir_emit_block(nir_block
*block
)
402 nir_foreach_instr(block
, instr
) {
403 nir_emit_instr(instr
);
408 fs_visitor::nir_emit_instr(nir_instr
*instr
)
410 const fs_builder abld
= bld
.annotate(NULL
, instr
);
412 switch (instr
->type
) {
413 case nir_instr_type_alu
:
414 nir_emit_alu(abld
, nir_instr_as_alu(instr
));
417 case nir_instr_type_intrinsic
:
419 case MESA_SHADER_VERTEX
:
420 nir_emit_vs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
422 case MESA_SHADER_GEOMETRY
:
423 nir_emit_gs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
425 case MESA_SHADER_FRAGMENT
:
426 nir_emit_fs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
428 case MESA_SHADER_COMPUTE
:
429 nir_emit_cs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
432 unreachable("unsupported shader stage");
436 case nir_instr_type_tex
:
437 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
440 case nir_instr_type_load_const
:
441 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
444 case nir_instr_type_ssa_undef
:
445 nir_emit_undef(abld
, nir_instr_as_ssa_undef(instr
));
448 case nir_instr_type_jump
:
449 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
453 unreachable("unknown instruction type");
458 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
459 const fs_reg
&result
)
461 if (!instr
->src
[0].src
.is_ssa
||
462 instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_intrinsic
)
465 nir_intrinsic_instr
*src0
=
466 nir_instr_as_intrinsic(instr
->src
[0].src
.ssa
->parent_instr
);
468 if (src0
->intrinsic
!= nir_intrinsic_load_front_face
)
471 nir_const_value
*value1
= nir_src_as_const_value(instr
->src
[1].src
);
472 if (!value1
|| fabsf(value1
->f
[0]) != 1.0f
)
475 nir_const_value
*value2
= nir_src_as_const_value(instr
->src
[2].src
);
476 if (!value2
|| fabsf(value2
->f
[0]) != 1.0f
)
479 fs_reg tmp
= vgrf(glsl_type::int_type
);
481 if (devinfo
->gen
>= 6) {
482 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
483 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
485 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
487 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
488 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
490 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
492 * This negation looks like it's safe in practice, because bits 0:4 will
493 * surely be TRIANGLES
496 if (value1
->f
[0] == -1.0f
) {
500 tmp
.type
= BRW_REGISTER_TYPE_W
;
501 tmp
.subreg_offset
= 2;
504 bld
.OR(tmp
, g0
, brw_imm_uw(0x3f80));
506 tmp
.type
= BRW_REGISTER_TYPE_D
;
507 tmp
.subreg_offset
= 0;
510 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
511 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
513 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
515 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
516 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
518 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
520 * This negation looks like it's safe in practice, because bits 0:4 will
521 * surely be TRIANGLES
524 if (value1
->f
[0] == -1.0f
) {
528 bld
.OR(tmp
, g1_6
, brw_imm_d(0x3f800000));
530 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, brw_imm_d(0xbf800000));
536 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
)
538 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
541 fs_reg result
= get_nir_dest(instr
->dest
.dest
);
542 result
.type
= brw_type_for_nir_type(nir_op_infos
[instr
->op
].output_type
);
545 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
546 op
[i
] = get_nir_src(instr
->src
[i
].src
);
547 op
[i
].type
= brw_type_for_nir_type(nir_op_infos
[instr
->op
].input_types
[i
]);
548 op
[i
].abs
= instr
->src
[i
].abs
;
549 op
[i
].negate
= instr
->src
[i
].negate
;
552 /* We get a bunch of mov's out of the from_ssa pass and they may still
553 * be vectorized. We'll handle them as a special-case. We'll also
554 * handle vecN here because it's basically the same thing.
562 fs_reg temp
= result
;
563 bool need_extra_copy
= false;
564 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
565 if (!instr
->src
[i
].src
.is_ssa
&&
566 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
567 need_extra_copy
= true;
568 temp
= bld
.vgrf(result
.type
, 4);
573 for (unsigned i
= 0; i
< 4; i
++) {
574 if (!(instr
->dest
.write_mask
& (1 << i
)))
577 if (instr
->op
== nir_op_imov
|| instr
->op
== nir_op_fmov
) {
578 inst
= bld
.MOV(offset(temp
, bld
, i
),
579 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
581 inst
= bld
.MOV(offset(temp
, bld
, i
),
582 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
584 inst
->saturate
= instr
->dest
.saturate
;
587 /* In this case the source and destination registers were the same,
588 * so we need to insert an extra set of moves in order to deal with
591 if (need_extra_copy
) {
592 for (unsigned i
= 0; i
< 4; i
++) {
593 if (!(instr
->dest
.write_mask
& (1 << i
)))
596 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
605 /* At this point, we have dealt with any instruction that operates on
606 * more than a single channel. Therefore, we can just adjust the source
607 * and destination registers for that channel and emit the instruction.
609 unsigned channel
= 0;
610 if (nir_op_infos
[instr
->op
].output_size
== 0) {
611 /* Since NIR is doing the scalarizing for us, we should only ever see
612 * vectorized operations with a single channel.
614 assert(_mesa_bitcount(instr
->dest
.write_mask
) == 1);
615 channel
= ffs(instr
->dest
.write_mask
) - 1;
617 result
= offset(result
, bld
, channel
);
620 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
621 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
622 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
628 inst
= bld
.MOV(result
, op
[0]);
629 inst
->saturate
= instr
->dest
.saturate
;
634 bld
.MOV(result
, op
[0]);
638 /* AND(val, 0x80000000) gives the sign bit.
640 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
643 bld
.CMP(bld
.null_reg_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
645 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
646 op
[0].type
= BRW_REGISTER_TYPE_UD
;
647 result
.type
= BRW_REGISTER_TYPE_UD
;
648 bld
.AND(result_int
, op
[0], brw_imm_ud(0x80000000u
));
650 inst
= bld
.OR(result_int
, result_int
, brw_imm_ud(0x3f800000u
));
651 inst
->predicate
= BRW_PREDICATE_NORMAL
;
652 if (instr
->dest
.saturate
) {
653 inst
= bld
.MOV(result
, result
);
654 inst
->saturate
= true;
660 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
661 * -> non-negative val generates 0x00000000.
662 * Predicated OR sets 1 if val is positive.
664 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_G
);
665 bld
.ASR(result
, op
[0], brw_imm_d(31));
666 inst
= bld
.OR(result
, result
, brw_imm_d(1));
667 inst
->predicate
= BRW_PREDICATE_NORMAL
;
671 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
672 inst
->saturate
= instr
->dest
.saturate
;
676 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
677 inst
->saturate
= instr
->dest
.saturate
;
681 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
682 inst
->saturate
= instr
->dest
.saturate
;
686 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
687 inst
->saturate
= instr
->dest
.saturate
;
691 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
692 inst
->saturate
= instr
->dest
.saturate
;
696 if (fs_key
->high_quality_derivatives
) {
697 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
699 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
701 inst
->saturate
= instr
->dest
.saturate
;
703 case nir_op_fddx_fine
:
704 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
705 inst
->saturate
= instr
->dest
.saturate
;
707 case nir_op_fddx_coarse
:
708 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
709 inst
->saturate
= instr
->dest
.saturate
;
712 if (fs_key
->high_quality_derivatives
) {
713 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0],
714 brw_imm_d(fs_key
->render_to_fbo
));
716 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0],
717 brw_imm_d(fs_key
->render_to_fbo
));
719 inst
->saturate
= instr
->dest
.saturate
;
721 case nir_op_fddy_fine
:
722 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0],
723 brw_imm_d(fs_key
->render_to_fbo
));
724 inst
->saturate
= instr
->dest
.saturate
;
726 case nir_op_fddy_coarse
:
727 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0],
728 brw_imm_d(fs_key
->render_to_fbo
));
729 inst
->saturate
= instr
->dest
.saturate
;
734 inst
= bld
.ADD(result
, op
[0], op
[1]);
735 inst
->saturate
= instr
->dest
.saturate
;
739 inst
= bld
.MUL(result
, op
[0], op
[1]);
740 inst
->saturate
= instr
->dest
.saturate
;
744 bld
.MUL(result
, op
[0], op
[1]);
747 case nir_op_imul_high
:
748 case nir_op_umul_high
:
749 bld
.emit(SHADER_OPCODE_MULH
, result
, op
[0], op
[1]);
754 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
757 case nir_op_uadd_carry
:
758 unreachable("Should have been lowered by carry_to_arith().");
760 case nir_op_usub_borrow
:
761 unreachable("Should have been lowered by borrow_to_arith().");
764 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
770 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
776 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
781 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_Z
);
786 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_NZ
);
790 if (devinfo
->gen
>= 8) {
791 op
[0] = resolve_source_modifiers(op
[0]);
793 bld
.NOT(result
, op
[0]);
796 if (devinfo
->gen
>= 8) {
797 op
[0] = resolve_source_modifiers(op
[0]);
798 op
[1] = resolve_source_modifiers(op
[1]);
800 bld
.XOR(result
, op
[0], op
[1]);
803 if (devinfo
->gen
>= 8) {
804 op
[0] = resolve_source_modifiers(op
[0]);
805 op
[1] = resolve_source_modifiers(op
[1]);
807 bld
.OR(result
, op
[0], op
[1]);
810 if (devinfo
->gen
>= 8) {
811 op
[0] = resolve_source_modifiers(op
[0]);
812 op
[1] = resolve_source_modifiers(op
[1]);
814 bld
.AND(result
, op
[0], op
[1]);
826 case nir_op_ball_fequal2
:
827 case nir_op_ball_iequal2
:
828 case nir_op_ball_fequal3
:
829 case nir_op_ball_iequal3
:
830 case nir_op_ball_fequal4
:
831 case nir_op_ball_iequal4
:
832 case nir_op_bany_fnequal2
:
833 case nir_op_bany_inequal2
:
834 case nir_op_bany_fnequal3
:
835 case nir_op_bany_inequal3
:
836 case nir_op_bany_fnequal4
:
837 case nir_op_bany_inequal4
:
838 unreachable("Lowered by nir_lower_alu_reductions");
840 case nir_op_fnoise1_1
:
841 case nir_op_fnoise1_2
:
842 case nir_op_fnoise1_3
:
843 case nir_op_fnoise1_4
:
844 case nir_op_fnoise2_1
:
845 case nir_op_fnoise2_2
:
846 case nir_op_fnoise2_3
:
847 case nir_op_fnoise2_4
:
848 case nir_op_fnoise3_1
:
849 case nir_op_fnoise3_2
:
850 case nir_op_fnoise3_3
:
851 case nir_op_fnoise3_4
:
852 case nir_op_fnoise4_1
:
853 case nir_op_fnoise4_2
:
854 case nir_op_fnoise4_3
:
855 case nir_op_fnoise4_4
:
856 unreachable("not reached: should be handled by lower_noise");
859 unreachable("not reached: should be handled by ldexp_to_arith()");
862 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
863 inst
->saturate
= instr
->dest
.saturate
;
867 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
868 inst
->saturate
= instr
->dest
.saturate
;
873 bld
.MOV(result
, negate(op
[0]));
877 bld
.CMP(result
, op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
880 bld
.CMP(result
, op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
884 inst
= bld
.RNDZ(result
, op
[0]);
885 inst
->saturate
= instr
->dest
.saturate
;
889 op
[0].negate
= !op
[0].negate
;
890 fs_reg temp
= vgrf(glsl_type::float_type
);
891 bld
.RNDD(temp
, op
[0]);
893 inst
= bld
.MOV(result
, temp
);
894 inst
->saturate
= instr
->dest
.saturate
;
898 inst
= bld
.RNDD(result
, op
[0]);
899 inst
->saturate
= instr
->dest
.saturate
;
902 inst
= bld
.FRC(result
, op
[0]);
903 inst
->saturate
= instr
->dest
.saturate
;
905 case nir_op_fround_even
:
906 inst
= bld
.RNDE(result
, op
[0]);
907 inst
->saturate
= instr
->dest
.saturate
;
913 if (devinfo
->gen
>= 6) {
914 inst
= bld
.emit(BRW_OPCODE_SEL
, result
, op
[0], op
[1]);
915 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
917 bld
.CMP(bld
.null_reg_d(), op
[0], op
[1], BRW_CONDITIONAL_L
);
918 inst
= bld
.SEL(result
, op
[0], op
[1]);
919 inst
->predicate
= BRW_PREDICATE_NORMAL
;
921 inst
->saturate
= instr
->dest
.saturate
;
927 if (devinfo
->gen
>= 6) {
928 inst
= bld
.emit(BRW_OPCODE_SEL
, result
, op
[0], op
[1]);
929 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
931 bld
.CMP(bld
.null_reg_d(), op
[0], op
[1], BRW_CONDITIONAL_GE
);
932 inst
= bld
.SEL(result
, op
[0], op
[1]);
933 inst
->predicate
= BRW_PREDICATE_NORMAL
;
935 inst
->saturate
= instr
->dest
.saturate
;
938 case nir_op_pack_snorm_2x16
:
939 case nir_op_pack_snorm_4x8
:
940 case nir_op_pack_unorm_2x16
:
941 case nir_op_pack_unorm_4x8
:
942 case nir_op_unpack_snorm_2x16
:
943 case nir_op_unpack_snorm_4x8
:
944 case nir_op_unpack_unorm_2x16
:
945 case nir_op_unpack_unorm_4x8
:
946 case nir_op_unpack_half_2x16
:
947 case nir_op_pack_half_2x16
:
948 unreachable("not reached: should be handled by lower_packing_builtins");
950 case nir_op_unpack_half_2x16_split_x
:
951 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
, result
, op
[0]);
952 inst
->saturate
= instr
->dest
.saturate
;
954 case nir_op_unpack_half_2x16_split_y
:
955 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
, result
, op
[0]);
956 inst
->saturate
= instr
->dest
.saturate
;
960 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
961 inst
->saturate
= instr
->dest
.saturate
;
964 case nir_op_bitfield_reverse
:
965 bld
.BFREV(result
, op
[0]);
968 case nir_op_bit_count
:
969 bld
.CBIT(result
, op
[0]);
972 case nir_op_ufind_msb
:
973 case nir_op_ifind_msb
: {
974 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
976 /* FBH counts from the MSB side, while GLSL's findMSB() wants the count
977 * from the LSB side. If FBH didn't return an error (0xFFFFFFFF), then
978 * subtract the result from 31 to convert the MSB count into an LSB count.
980 bld
.CMP(bld
.null_reg_d(), result
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
);
982 inst
= bld
.ADD(result
, result
, brw_imm_d(31));
983 inst
->predicate
= BRW_PREDICATE_NORMAL
;
984 inst
->src
[0].negate
= true;
988 case nir_op_find_lsb
:
989 bld
.FBL(result
, op
[0]);
992 case nir_op_ubitfield_extract
:
993 case nir_op_ibitfield_extract
:
994 bld
.BFE(result
, op
[2], op
[1], op
[0]);
997 bld
.BFI1(result
, op
[0], op
[1]);
1000 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
1003 case nir_op_bitfield_insert
:
1004 unreachable("not reached: should be handled by "
1005 "lower_instructions::bitfield_insert_to_bfm_bfi");
1008 bld
.SHL(result
, op
[0], op
[1]);
1011 bld
.ASR(result
, op
[0], op
[1]);
1014 bld
.SHR(result
, op
[0], op
[1]);
1017 case nir_op_pack_half_2x16_split
:
1018 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1022 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
1023 inst
->saturate
= instr
->dest
.saturate
;
1027 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
1028 inst
->saturate
= instr
->dest
.saturate
;
1032 if (optimize_frontfacing_ternary(instr
, result
))
1035 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1036 inst
= bld
.SEL(result
, op
[1], op
[2]);
1037 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1041 unreachable("unhandled instruction");
1044 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1045 * to sign extend the low bit to 0/~0
1047 if (devinfo
->gen
<= 5 &&
1048 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1049 fs_reg masked
= vgrf(glsl_type::int_type
);
1050 bld
.AND(masked
, result
, brw_imm_d(1));
1051 masked
.negate
= true;
1052 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
1057 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
1058 nir_load_const_instr
*instr
)
1060 fs_reg reg
= bld
.vgrf(BRW_REGISTER_TYPE_D
, instr
->def
.num_components
);
1062 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1063 bld
.MOV(offset(reg
, bld
, i
), brw_imm_d(instr
->value
.i
[i
]));
1065 nir_ssa_values
[instr
->def
.index
] = reg
;
1069 fs_visitor::nir_emit_undef(const fs_builder
&bld
, nir_ssa_undef_instr
*instr
)
1071 nir_ssa_values
[instr
->def
.index
] = bld
.vgrf(BRW_REGISTER_TYPE_D
,
1072 instr
->def
.num_components
);
1076 fs_reg_for_nir_reg(fs_visitor
*v
, nir_register
*nir_reg
,
1077 unsigned base_offset
, nir_src
*indirect
)
1081 assert(!nir_reg
->is_global
);
1083 reg
= v
->nir_locals
[nir_reg
->index
];
1085 reg
= offset(reg
, v
->bld
, base_offset
* nir_reg
->num_components
);
1087 int multiplier
= nir_reg
->num_components
* (v
->dispatch_width
/ 8);
1089 reg
.reladdr
= new(v
->mem_ctx
) fs_reg(v
->vgrf(glsl_type::int_type
));
1090 v
->bld
.MUL(*reg
.reladdr
, v
->get_nir_src(*indirect
),
1091 brw_imm_d(multiplier
));
1098 fs_visitor::get_nir_src(nir_src src
)
1102 reg
= nir_ssa_values
[src
.ssa
->index
];
1104 reg
= fs_reg_for_nir_reg(this, src
.reg
.reg
, src
.reg
.base_offset
,
1108 /* to avoid floating-point denorm flushing problems, set the type by
1109 * default to D - instructions that need floating point semantics will set
1110 * this to F if they need to
1112 return retype(reg
, BRW_REGISTER_TYPE_D
);
1116 fs_visitor::get_nir_dest(nir_dest dest
)
1119 nir_ssa_values
[dest
.ssa
.index
] = bld
.vgrf(BRW_REGISTER_TYPE_F
,
1120 dest
.ssa
.num_components
);
1121 return nir_ssa_values
[dest
.ssa
.index
];
1124 return fs_reg_for_nir_reg(this, dest
.reg
.reg
, dest
.reg
.base_offset
,
1129 fs_visitor::get_nir_image_deref(const nir_deref_var
*deref
)
1131 fs_reg
image(UNIFORM
, deref
->var
->data
.driver_location
,
1132 BRW_REGISTER_TYPE_UD
);
1134 for (const nir_deref
*tail
= &deref
->deref
; tail
->child
;
1135 tail
= tail
->child
) {
1136 const nir_deref_array
*deref_array
= nir_deref_as_array(tail
->child
);
1137 assert(tail
->child
->deref_type
== nir_deref_type_array
);
1138 const unsigned size
= glsl_get_length(tail
->type
);
1139 const unsigned element_size
= type_size_scalar(deref_array
->deref
.type
);
1140 const unsigned base
= MIN2(deref_array
->base_offset
, size
- 1);
1141 image
= offset(image
, bld
, base
* element_size
);
1143 if (deref_array
->deref_array_type
== nir_deref_array_type_indirect
) {
1144 fs_reg tmp
= vgrf(glsl_type::int_type
);
1146 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
) {
1147 /* IVB hangs when trying to access an invalid surface index with
1148 * the dataport. According to the spec "if the index used to
1149 * select an individual element is negative or greater than or
1150 * equal to the size of the array, the results of the operation
1151 * are undefined but may not lead to termination" -- which is one
1152 * of the possible outcomes of the hang. Clamp the index to
1153 * prevent access outside of the array bounds.
1155 bld
.emit_minmax(tmp
, retype(get_nir_src(deref_array
->indirect
),
1156 BRW_REGISTER_TYPE_UD
),
1157 brw_imm_ud(size
- base
- 1), BRW_CONDITIONAL_L
);
1159 bld
.MOV(tmp
, get_nir_src(deref_array
->indirect
));
1162 bld
.MUL(tmp
, tmp
, brw_imm_ud(element_size
));
1164 bld
.ADD(*image
.reladdr
, *image
.reladdr
, tmp
);
1166 image
.reladdr
= new(mem_ctx
) fs_reg(tmp
);
1174 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
1177 for (unsigned i
= 0; i
< 4; i
++) {
1178 if (!((wr_mask
>> i
) & 1))
1181 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
1182 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
1183 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1184 if (new_inst
->src
[j
].file
== VGRF
)
1185 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
1192 * Get the matching channel register datatype for an image intrinsic of the
1193 * specified GLSL image type.
1196 get_image_base_type(const glsl_type
*type
)
1198 switch ((glsl_base_type
)type
->sampler_type
) {
1199 case GLSL_TYPE_UINT
:
1200 return BRW_REGISTER_TYPE_UD
;
1202 return BRW_REGISTER_TYPE_D
;
1203 case GLSL_TYPE_FLOAT
:
1204 return BRW_REGISTER_TYPE_F
;
1206 unreachable("Not reached.");
1211 * Get the appropriate atomic op for an image atomic intrinsic.
1214 get_image_atomic_op(nir_intrinsic_op op
, const glsl_type
*type
)
1217 case nir_intrinsic_image_atomic_add
:
1219 case nir_intrinsic_image_atomic_min
:
1220 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1221 BRW_AOP_IMIN
: BRW_AOP_UMIN
);
1222 case nir_intrinsic_image_atomic_max
:
1223 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1224 BRW_AOP_IMAX
: BRW_AOP_UMAX
);
1225 case nir_intrinsic_image_atomic_and
:
1227 case nir_intrinsic_image_atomic_or
:
1229 case nir_intrinsic_image_atomic_xor
:
1231 case nir_intrinsic_image_atomic_exchange
:
1233 case nir_intrinsic_image_atomic_comp_swap
:
1234 return BRW_AOP_CMPWR
;
1236 unreachable("Not reachable.");
1241 emit_pixel_interpolater_send(const fs_builder
&bld
,
1246 glsl_interp_qualifier interpolation
)
1252 if (src
.file
== BAD_FILE
) {
1254 payload
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 1);
1258 mlen
= 2 * bld
.dispatch_width() / 8;
1261 inst
= bld
.emit(opcode
, dst
, payload
, desc
);
1263 /* 2 floats per slot returned */
1264 inst
->regs_written
= 2 * bld
.dispatch_width() / 8;
1265 inst
->pi_noperspective
= interpolation
== INTERP_QUALIFIER_NOPERSPECTIVE
;
1271 * Computes 1 << x, given a D/UD register containing some value x.
1274 intexp2(const fs_builder
&bld
, const fs_reg
&x
)
1276 assert(x
.type
== BRW_REGISTER_TYPE_UD
|| x
.type
== BRW_REGISTER_TYPE_D
);
1278 fs_reg result
= bld
.vgrf(x
.type
, 1);
1279 fs_reg one
= bld
.vgrf(x
.type
, 1);
1281 bld
.MOV(one
, retype(brw_imm_d(1), one
.type
));
1282 bld
.SHL(result
, one
, x
);
1287 fs_visitor::emit_gs_end_primitive(const nir_src
&vertex_count_nir_src
)
1289 assert(stage
== MESA_SHADER_GEOMETRY
);
1291 struct brw_gs_prog_data
*gs_prog_data
=
1292 (struct brw_gs_prog_data
*) prog_data
;
1294 /* We can only do EndPrimitive() functionality when the control data
1295 * consists of cut bits. Fortunately, the only time it isn't is when the
1296 * output type is points, in which case EndPrimitive() is a no-op.
1298 if (gs_prog_data
->control_data_format
!=
1299 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT
) {
1303 /* Cut bits use one bit per vertex. */
1304 assert(gs_compile
->control_data_bits_per_vertex
== 1);
1306 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1307 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1309 /* Cut bit n should be set to 1 if EndPrimitive() was called after emitting
1310 * vertex n, 0 otherwise. So all we need to do here is mark bit
1311 * (vertex_count - 1) % 32 in the cut_bits register to indicate that
1312 * EndPrimitive() was called after emitting vertex (vertex_count - 1);
1313 * vec4_gs_visitor::emit_control_data_bits() will take care of the rest.
1315 * Note that if EndPrimitive() is called before emitting any vertices, this
1316 * will cause us to set bit 31 of the control_data_bits register to 1.
1317 * That's fine because:
1319 * - If max_vertices < 32, then vertex number 31 (zero-based) will never be
1320 * output, so the hardware will ignore cut bit 31.
1322 * - If max_vertices == 32, then vertex number 31 is guaranteed to be the
1323 * last vertex, so setting cut bit 31 has no effect (since the primitive
1324 * is automatically ended when the GS terminates).
1326 * - If max_vertices > 32, then the ir_emit_vertex visitor will reset the
1327 * control_data_bits register to 0 when the first vertex is emitted.
1330 const fs_builder abld
= bld
.annotate("end primitive");
1332 /* control_data_bits |= 1 << ((vertex_count - 1) % 32) */
1333 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1334 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1335 fs_reg mask
= intexp2(abld
, prev_count
);
1336 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1337 * attention to the lower 5 bits of its second source argument, so on this
1338 * architecture, 1 << (vertex_count - 1) is equivalent to 1 <<
1339 * ((vertex_count - 1) % 32).
1341 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1345 fs_visitor::emit_gs_control_data_bits(const fs_reg
&vertex_count
)
1347 assert(stage
== MESA_SHADER_GEOMETRY
);
1348 assert(gs_compile
->control_data_bits_per_vertex
!= 0);
1350 struct brw_gs_prog_data
*gs_prog_data
=
1351 (struct brw_gs_prog_data
*) prog_data
;
1353 const fs_builder abld
= bld
.annotate("emit control data bits");
1354 const fs_builder fwa_bld
= bld
.exec_all();
1356 /* We use a single UD register to accumulate control data bits (32 bits
1357 * for each of the SIMD8 channels). So we need to write a DWord (32 bits)
1360 * Unfortunately, the URB_WRITE_SIMD8 message uses 128-bit (OWord) offsets.
1361 * We have select a 128-bit group via the Global and Per-Slot Offsets, then
1362 * use the Channel Mask phase to enable/disable which DWord within that
1363 * group to write. (Remember, different SIMD8 channels may have emitted
1364 * different numbers of vertices, so we may need per-slot offsets.)
1366 * Channel masking presents an annoying problem: we may have to replicate
1367 * the data up to 4 times:
1369 * Msg = Handles, Per-Slot Offsets, Channel Masks, Data, Data, Data, Data.
1371 * To avoid penalizing shaders that emit a small number of vertices, we
1372 * can avoid these sometimes: if the size of the control data header is
1373 * <= 128 bits, then there is only 1 OWord. All SIMD8 channels will land
1374 * land in the same 128-bit group, so we can skip per-slot offsets.
1376 * Similarly, if the control data header is <= 32 bits, there is only one
1377 * DWord, so we can skip channel masks.
1379 enum opcode opcode
= SHADER_OPCODE_URB_WRITE_SIMD8
;
1381 fs_reg channel_mask
, per_slot_offset
;
1383 if (gs_compile
->control_data_header_size_bits
> 32) {
1384 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
1385 channel_mask
= vgrf(glsl_type::uint_type
);
1388 if (gs_compile
->control_data_header_size_bits
> 128) {
1389 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
;
1390 per_slot_offset
= vgrf(glsl_type::uint_type
);
1393 /* Figure out which DWord we're trying to write to using the formula:
1395 * dword_index = (vertex_count - 1) * bits_per_vertex / 32
1397 * Since bits_per_vertex is a power of two, and is known at compile
1398 * time, this can be optimized to:
1400 * dword_index = (vertex_count - 1) >> (6 - log2(bits_per_vertex))
1402 if (opcode
!= SHADER_OPCODE_URB_WRITE_SIMD8
) {
1403 fs_reg dword_index
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1404 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1405 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1406 unsigned log2_bits_per_vertex
=
1407 _mesa_fls(gs_compile
->control_data_bits_per_vertex
);
1408 abld
.SHR(dword_index
, prev_count
, brw_imm_ud(6u - log2_bits_per_vertex
));
1410 if (per_slot_offset
.file
!= BAD_FILE
) {
1411 /* Set the per-slot offset to dword_index / 4, so that we'll write to
1412 * the appropriate OWord within the control data header.
1414 abld
.SHR(per_slot_offset
, dword_index
, brw_imm_ud(2u));
1417 /* Set the channel masks to 1 << (dword_index % 4), so that we'll
1418 * write to the appropriate DWORD within the OWORD.
1420 fs_reg channel
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1421 fwa_bld
.AND(channel
, dword_index
, brw_imm_ud(3u));
1422 channel_mask
= intexp2(fwa_bld
, channel
);
1423 /* Then the channel masks need to be in bits 23:16. */
1424 fwa_bld
.SHL(channel_mask
, channel_mask
, brw_imm_ud(16u));
1427 /* Store the control data bits in the message payload and send it. */
1429 if (channel_mask
.file
!= BAD_FILE
)
1430 mlen
+= 4; /* channel masks, plus 3 extra copies of the data */
1431 if (per_slot_offset
.file
!= BAD_FILE
)
1434 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
1435 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, mlen
);
1437 sources
[i
++] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1438 if (per_slot_offset
.file
!= BAD_FILE
)
1439 sources
[i
++] = per_slot_offset
;
1440 if (channel_mask
.file
!= BAD_FILE
)
1441 sources
[i
++] = channel_mask
;
1443 sources
[i
++] = this->control_data_bits
;
1446 abld
.LOAD_PAYLOAD(payload
, sources
, mlen
, mlen
);
1447 fs_inst
*inst
= abld
.emit(opcode
, reg_undef
, payload
);
1449 /* We need to increment Global Offset by 256-bits to make room for
1450 * Broadwell's extra "Vertex Count" payload at the beginning of the
1451 * URB entry. Since this is an OWord message, Global Offset is counted
1452 * in 128-bit units, so we must set it to 2.
1454 if (gs_prog_data
->static_vertex_count
== -1)
1459 fs_visitor::set_gs_stream_control_data_bits(const fs_reg
&vertex_count
,
1462 /* control_data_bits |= stream_id << ((2 * (vertex_count - 1)) % 32) */
1464 /* Note: we are calling this *before* increasing vertex_count, so
1465 * this->vertex_count == vertex_count - 1 in the formula above.
1468 /* Stream mode uses 2 bits per vertex */
1469 assert(gs_compile
->control_data_bits_per_vertex
== 2);
1471 /* Must be a valid stream */
1472 assert(stream_id
>= 0 && stream_id
< MAX_VERTEX_STREAMS
);
1474 /* Control data bits are initialized to 0 so we don't have to set any
1475 * bits when sending vertices to stream 0.
1480 const fs_builder abld
= bld
.annotate("set stream control data bits", NULL
);
1482 /* reg::sid = stream_id */
1483 fs_reg sid
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1484 abld
.MOV(sid
, brw_imm_ud(stream_id
));
1486 /* reg:shift_count = 2 * (vertex_count - 1) */
1487 fs_reg shift_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1488 abld
.SHL(shift_count
, vertex_count
, brw_imm_ud(1u));
1490 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1491 * attention to the lower 5 bits of its second source argument, so on this
1492 * architecture, stream_id << 2 * (vertex_count - 1) is equivalent to
1493 * stream_id << ((2 * (vertex_count - 1)) % 32).
1495 fs_reg mask
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1496 abld
.SHL(mask
, sid
, shift_count
);
1497 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1501 fs_visitor::emit_gs_vertex(const nir_src
&vertex_count_nir_src
,
1504 assert(stage
== MESA_SHADER_GEOMETRY
);
1506 struct brw_gs_prog_data
*gs_prog_data
=
1507 (struct brw_gs_prog_data
*) prog_data
;
1509 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1510 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1512 /* Haswell and later hardware ignores the "Render Stream Select" bits
1513 * from the 3DSTATE_STREAMOUT packet when the SOL stage is disabled,
1514 * and instead sends all primitives down the pipeline for rasterization.
1515 * If the SOL stage is enabled, "Render Stream Select" is honored and
1516 * primitives bound to non-zero streams are discarded after stream output.
1518 * Since the only purpose of primives sent to non-zero streams is to
1519 * be recorded by transform feedback, we can simply discard all geometry
1520 * bound to these streams when transform feedback is disabled.
1522 if (stream_id
> 0 && !nir
->info
.has_transform_feedback_varyings
)
1525 /* If we're outputting 32 control data bits or less, then we can wait
1526 * until the shader is over to output them all. Otherwise we need to
1527 * output them as we go. Now is the time to do it, since we're about to
1528 * output the vertex_count'th vertex, so it's guaranteed that the
1529 * control data bits associated with the (vertex_count - 1)th vertex are
1532 if (gs_compile
->control_data_header_size_bits
> 32) {
1533 const fs_builder abld
=
1534 bld
.annotate("emit vertex: emit control data bits");
1536 /* Only emit control data bits if we've finished accumulating a batch
1537 * of 32 bits. This is the case when:
1539 * (vertex_count * bits_per_vertex) % 32 == 0
1541 * (in other words, when the last 5 bits of vertex_count *
1542 * bits_per_vertex are 0). Assuming bits_per_vertex == 2^n for some
1543 * integer n (which is always the case, since bits_per_vertex is
1544 * always 1 or 2), this is equivalent to requiring that the last 5-n
1545 * bits of vertex_count are 0:
1547 * vertex_count & (2^(5-n) - 1) == 0
1549 * 2^(5-n) == 2^5 / 2^n == 32 / bits_per_vertex, so this is
1552 * vertex_count & (32 / bits_per_vertex - 1) == 0
1554 * TODO: If vertex_count is an immediate, we could do some of this math
1555 * at compile time...
1558 abld
.AND(bld
.null_reg_d(), vertex_count
,
1559 brw_imm_ud(32u / gs_compile
->control_data_bits_per_vertex
- 1u));
1560 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1562 abld
.IF(BRW_PREDICATE_NORMAL
);
1563 /* If vertex_count is 0, then no control data bits have been
1564 * accumulated yet, so we can skip emitting them.
1566 abld
.CMP(bld
.null_reg_d(), vertex_count
, brw_imm_ud(0u),
1567 BRW_CONDITIONAL_NEQ
);
1568 abld
.IF(BRW_PREDICATE_NORMAL
);
1569 emit_gs_control_data_bits(vertex_count
);
1570 abld
.emit(BRW_OPCODE_ENDIF
);
1572 /* Reset control_data_bits to 0 so we can start accumulating a new
1575 * Note: in the case where vertex_count == 0, this neutralizes the
1576 * effect of any call to EndPrimitive() that the shader may have
1577 * made before outputting its first vertex.
1579 inst
= abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
1580 inst
->force_writemask_all
= true;
1581 abld
.emit(BRW_OPCODE_ENDIF
);
1584 emit_urb_writes(vertex_count
);
1586 /* In stream mode we have to set control data bits for all vertices
1587 * unless we have disabled control data bits completely (which we do
1588 * do for GL_POINTS outputs that don't use streams).
1590 if (gs_compile
->control_data_header_size_bits
> 0 &&
1591 gs_prog_data
->control_data_format
==
1592 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
) {
1593 set_gs_stream_control_data_bits(vertex_count
, stream_id
);
1598 fs_visitor::emit_gs_input_load(const fs_reg
&dst
,
1599 const nir_src
&vertex_src
,
1600 const fs_reg
&indirect_offset
,
1601 unsigned imm_offset
,
1602 unsigned num_components
)
1604 struct brw_gs_prog_data
*gs_prog_data
= (struct brw_gs_prog_data
*) prog_data
;
1606 /* Offset 0 is the VUE header, which contains VARYING_SLOT_LAYER [.y],
1607 * VARYING_SLOT_VIEWPORT [.z], and VARYING_SLOT_PSIZ [.w]. Only
1608 * gl_PointSize is available as a GS input, however, so it must be that.
1610 const bool is_point_size
=
1611 indirect_offset
.file
== BAD_FILE
&& imm_offset
== 0;
1613 nir_const_value
*vertex_const
= nir_src_as_const_value(vertex_src
);
1614 const unsigned push_reg_count
= gs_prog_data
->base
.urb_read_length
* 8;
1616 if (indirect_offset
.file
== BAD_FILE
&& vertex_const
!= NULL
&&
1617 4 * imm_offset
< push_reg_count
) {
1618 imm_offset
= 4 * imm_offset
+ vertex_const
->u
[0] * push_reg_count
;
1619 /* This input was pushed into registers. */
1620 if (is_point_size
) {
1621 /* gl_PointSize comes in .w */
1622 bld
.MOV(dst
, fs_reg(ATTR
, imm_offset
+ 3, dst
.type
));
1624 for (unsigned i
= 0; i
< num_components
; i
++) {
1625 bld
.MOV(offset(dst
, bld
, i
),
1626 fs_reg(ATTR
, imm_offset
+ i
, dst
.type
));
1630 /* Resort to the pull model. Ensure the VUE handles are provided. */
1631 gs_prog_data
->base
.include_vue_handles
= true;
1633 unsigned first_icp_handle
= gs_prog_data
->include_primitive_id
? 3 : 2;
1637 /* The vertex index is constant; just select the proper URB handle. */
1639 retype(brw_vec8_grf(first_icp_handle
+ vertex_const
->i
[0], 0),
1640 BRW_REGISTER_TYPE_UD
);
1642 /* The vertex index is non-constant. We need to use indirect
1643 * addressing to fetch the proper URB handle.
1645 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
1646 * indicating that channel <n> should read the handle from
1647 * DWord <n>. We convert that to bytes by multiplying by 4.
1649 * Next, we convert the vertex index to bytes by multiplying
1650 * by 32 (shifting by 5), and add the two together. This is
1651 * the final indirect byte offset.
1653 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_W
, 1);
1654 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1655 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1656 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1657 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1659 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
1660 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
1661 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
1662 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
1663 /* Convert vertex_index to bytes (multiply by 32) */
1664 bld
.SHL(vertex_offset_bytes
,
1665 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
1667 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
1669 /* Use first_icp_handle as the base offset. There is one register
1670 * of URB handles per vertex, so inform the register allocator that
1671 * we might read up to nir->info.gs.vertices_in registers.
1673 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
1674 fs_reg(brw_vec8_grf(first_icp_handle
, 0)),
1675 fs_reg(icp_offset_bytes
),
1676 brw_imm_ud(nir
->info
.gs
.vertices_in
* REG_SIZE
));
1680 if (indirect_offset
.file
== BAD_FILE
) {
1681 /* Constant indexing - use global offset. */
1682 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
1683 inst
->offset
= imm_offset
;
1684 inst
->base_mrf
= -1;
1686 inst
->regs_written
= num_components
;
1688 /* Indirect indexing - use per-slot offsets as well. */
1689 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
1690 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
1691 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
1693 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
, payload
);
1694 inst
->offset
= imm_offset
;
1695 inst
->base_mrf
= -1;
1697 inst
->regs_written
= num_components
;
1700 if (is_point_size
) {
1701 /* Read the whole VUE header (because of alignment) and read .w. */
1702 fs_reg tmp
= bld
.vgrf(dst
.type
, 4);
1704 inst
->regs_written
= 4;
1705 bld
.MOV(dst
, offset(tmp
, bld
, 3));
1711 fs_visitor::nir_emit_vs_intrinsic(const fs_builder
&bld
,
1712 nir_intrinsic_instr
*instr
)
1714 assert(stage
== MESA_SHADER_VERTEX
);
1717 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
1718 dest
= get_nir_dest(instr
->dest
);
1720 switch (instr
->intrinsic
) {
1721 case nir_intrinsic_load_vertex_id
:
1722 unreachable("should be lowered by lower_vertex_id()");
1724 case nir_intrinsic_load_vertex_id_zero_base
:
1725 case nir_intrinsic_load_base_vertex
:
1726 case nir_intrinsic_load_instance_id
: {
1727 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
1728 fs_reg val
= nir_system_values
[sv
];
1729 assert(val
.file
!= BAD_FILE
);
1730 dest
.type
= val
.type
;
1736 nir_emit_intrinsic(bld
, instr
);
1742 fs_visitor::nir_emit_gs_intrinsic(const fs_builder
&bld
,
1743 nir_intrinsic_instr
*instr
)
1745 assert(stage
== MESA_SHADER_GEOMETRY
);
1746 fs_reg indirect_offset
;
1749 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
1750 dest
= get_nir_dest(instr
->dest
);
1752 switch (instr
->intrinsic
) {
1753 case nir_intrinsic_load_primitive_id
:
1754 assert(stage
== MESA_SHADER_GEOMETRY
);
1755 assert(((struct brw_gs_prog_data
*)prog_data
)->include_primitive_id
);
1756 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
1757 retype(fs_reg(brw_vec8_grf(2, 0)), BRW_REGISTER_TYPE_UD
));
1760 case nir_intrinsic_load_input_indirect
:
1761 case nir_intrinsic_load_input
:
1762 unreachable("load_input intrinsics are invalid for the GS stage");
1764 case nir_intrinsic_load_per_vertex_input_indirect
:
1765 indirect_offset
= retype(get_nir_src(instr
->src
[1]), BRW_REGISTER_TYPE_D
);
1767 case nir_intrinsic_load_per_vertex_input
:
1768 emit_gs_input_load(dest
, instr
->src
[0],
1769 indirect_offset
, instr
->const_index
[0],
1770 instr
->num_components
);
1773 case nir_intrinsic_emit_vertex_with_counter
:
1774 emit_gs_vertex(instr
->src
[0], instr
->const_index
[0]);
1777 case nir_intrinsic_end_primitive_with_counter
:
1778 emit_gs_end_primitive(instr
->src
[0]);
1781 case nir_intrinsic_set_vertex_count
:
1782 bld
.MOV(this->final_gs_vertex_count
, get_nir_src(instr
->src
[0]));
1785 case nir_intrinsic_load_invocation_id
: {
1786 fs_reg val
= nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
1787 assert(val
.file
!= BAD_FILE
);
1788 dest
.type
= val
.type
;
1794 nir_emit_intrinsic(bld
, instr
);
1800 fs_visitor::nir_emit_fs_intrinsic(const fs_builder
&bld
,
1801 nir_intrinsic_instr
*instr
)
1803 assert(stage
== MESA_SHADER_FRAGMENT
);
1804 struct brw_wm_prog_data
*wm_prog_data
=
1805 (struct brw_wm_prog_data
*) prog_data
;
1808 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
1809 dest
= get_nir_dest(instr
->dest
);
1811 switch (instr
->intrinsic
) {
1812 case nir_intrinsic_load_front_face
:
1813 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
1814 *emit_frontfacing_interpolation());
1817 case nir_intrinsic_load_sample_pos
: {
1818 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
1819 assert(sample_pos
.file
!= BAD_FILE
);
1820 dest
.type
= sample_pos
.type
;
1821 bld
.MOV(dest
, sample_pos
);
1822 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
1826 case nir_intrinsic_load_helper_invocation
:
1827 case nir_intrinsic_load_sample_mask_in
:
1828 case nir_intrinsic_load_sample_id
: {
1829 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
1830 fs_reg val
= nir_system_values
[sv
];
1831 assert(val
.file
!= BAD_FILE
);
1832 dest
.type
= val
.type
;
1837 case nir_intrinsic_discard
:
1838 case nir_intrinsic_discard_if
: {
1839 /* We track our discarded pixels in f0.1. By predicating on it, we can
1840 * update just the flag bits that aren't yet discarded. If there's no
1841 * condition, we emit a CMP of g0 != g0, so all currently executing
1842 * channels will get turned off.
1845 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
1846 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
1847 brw_imm_d(0), BRW_CONDITIONAL_Z
);
1849 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
1850 BRW_REGISTER_TYPE_UW
));
1851 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
1853 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
1854 cmp
->flag_subreg
= 1;
1856 if (devinfo
->gen
>= 6) {
1857 emit_discard_jump();
1862 case nir_intrinsic_interp_var_at_centroid
:
1863 case nir_intrinsic_interp_var_at_sample
:
1864 case nir_intrinsic_interp_var_at_offset
: {
1865 /* Handle ARB_gpu_shader5 interpolation intrinsics
1867 * It's worth a quick word of explanation as to why we handle the full
1868 * variable-based interpolation intrinsic rather than a lowered version
1869 * with like we do for other inputs. We have to do that because the way
1870 * we set up inputs doesn't allow us to use the already setup inputs for
1871 * interpolation. At the beginning of the shader, we go through all of
1872 * the input variables and do the initial interpolation and put it in
1873 * the nir_inputs array based on its location as determined in
1874 * nir_lower_io. If the input isn't used, dead code cleans up and
1875 * everything works fine. However, when we get to the ARB_gpu_shader5
1876 * interpolation intrinsics, we need to reinterpolate the input
1877 * differently. If we used an intrinsic that just had an index it would
1878 * only give us the offset into the nir_inputs array. However, this is
1879 * useless because that value is post-interpolation and we need
1880 * pre-interpolation. In order to get the actual location of the bits
1881 * we get from the vertex fetching hardware, we need the variable.
1883 wm_prog_data
->pulls_bary
= true;
1885 fs_reg dst_xy
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 2);
1886 const glsl_interp_qualifier interpolation
=
1887 (glsl_interp_qualifier
) instr
->variables
[0]->var
->data
.interpolation
;
1889 switch (instr
->intrinsic
) {
1890 case nir_intrinsic_interp_var_at_centroid
:
1891 emit_pixel_interpolater_send(bld
,
1892 FS_OPCODE_INTERPOLATE_AT_CENTROID
,
1899 case nir_intrinsic_interp_var_at_sample
: {
1900 nir_const_value
*const_sample
= nir_src_as_const_value(instr
->src
[0]);
1903 unsigned msg_data
= const_sample
->i
[0] << 4;
1905 emit_pixel_interpolater_send(bld
,
1906 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
1909 brw_imm_ud(msg_data
),
1912 const fs_reg sample_src
= retype(get_nir_src(instr
->src
[0]),
1913 BRW_REGISTER_TYPE_UD
);
1915 if (nir_src_is_dynamically_uniform(instr
->src
[0])) {
1916 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
1917 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
1918 bld
.exec_all().group(1, 0)
1919 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
1920 emit_pixel_interpolater_send(bld
,
1921 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
1927 /* Make a loop that sends a message to the pixel interpolater
1928 * for the sample number in each live channel. If there are
1929 * multiple channels with the same sample number then these
1930 * will be handled simultaneously with a single interation of
1933 bld
.emit(BRW_OPCODE_DO
);
1935 /* Get the next live sample number into sample_id_reg */
1936 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
1938 /* Set the flag register so that we can perform the send
1939 * message on all channels that have the same sample number
1941 bld
.CMP(bld
.null_reg_ud(),
1942 sample_src
, sample_id
,
1943 BRW_CONDITIONAL_EQ
);
1944 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
1945 bld
.exec_all().group(1, 0)
1946 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
1948 emit_pixel_interpolater_send(bld
,
1949 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
1954 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
1956 /* Continue the loop if there are any live channels left */
1957 set_predicate_inv(BRW_PREDICATE_NORMAL
,
1959 bld
.emit(BRW_OPCODE_WHILE
));
1966 case nir_intrinsic_interp_var_at_offset
: {
1967 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
1970 unsigned off_x
= MIN2((int)(const_offset
->f
[0] * 16), 7) & 0xf;
1971 unsigned off_y
= MIN2((int)(const_offset
->f
[1] * 16), 7) & 0xf;
1973 emit_pixel_interpolater_send(bld
,
1974 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
,
1977 brw_imm_ud(off_x
| (off_y
<< 4)),
1980 fs_reg src
= vgrf(glsl_type::ivec2_type
);
1981 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
1982 BRW_REGISTER_TYPE_F
);
1983 for (int i
= 0; i
< 2; i
++) {
1984 fs_reg temp
= vgrf(glsl_type::float_type
);
1985 bld
.MUL(temp
, offset(offset_src
, bld
, i
), brw_imm_f(16.0f
));
1986 fs_reg itemp
= vgrf(glsl_type::int_type
);
1987 bld
.MOV(itemp
, temp
); /* float to int */
1989 /* Clamp the upper end of the range to +7/16.
1990 * ARB_gpu_shader5 requires that we support a maximum offset
1991 * of +0.5, which isn't representable in a S0.4 value -- if
1992 * we didn't clamp it, we'd end up with -8/16, which is the
1993 * opposite of what the shader author wanted.
1995 * This is legal due to ARB_gpu_shader5's quantization
1998 * "Not all values of <offset> may be supported; x and y
1999 * offsets may be rounded to fixed-point values with the
2000 * number of fraction bits given by the
2001 * implementation-dependent constant
2002 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
2004 set_condmod(BRW_CONDITIONAL_L
,
2005 bld
.SEL(offset(src
, bld
, i
), itemp
, brw_imm_d(7)));
2008 const enum opcode opcode
= FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
;
2009 emit_pixel_interpolater_send(bld
,
2020 unreachable("Invalid intrinsic");
2023 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
2024 fs_reg src
= interp_reg(instr
->variables
[0]->var
->data
.location
, j
);
2025 src
.type
= dest
.type
;
2027 bld
.emit(FS_OPCODE_LINTERP
, dest
, dst_xy
, src
);
2028 dest
= offset(dest
, bld
, 1);
2033 nir_emit_intrinsic(bld
, instr
);
2039 fs_visitor::nir_emit_cs_intrinsic(const fs_builder
&bld
,
2040 nir_intrinsic_instr
*instr
)
2042 assert(stage
== MESA_SHADER_COMPUTE
);
2043 struct brw_cs_prog_data
*cs_prog_data
=
2044 (struct brw_cs_prog_data
*) prog_data
;
2047 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2048 dest
= get_nir_dest(instr
->dest
);
2050 switch (instr
->intrinsic
) {
2051 case nir_intrinsic_barrier
:
2053 cs_prog_data
->uses_barrier
= true;
2056 case nir_intrinsic_load_local_invocation_id
:
2057 case nir_intrinsic_load_work_group_id
: {
2058 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
2059 fs_reg val
= nir_system_values
[sv
];
2060 assert(val
.file
!= BAD_FILE
);
2061 dest
.type
= val
.type
;
2062 for (unsigned i
= 0; i
< 3; i
++)
2063 bld
.MOV(offset(dest
, bld
, i
), offset(val
, bld
, i
));
2067 case nir_intrinsic_load_num_work_groups
: {
2068 const unsigned surface
=
2069 cs_prog_data
->binding_table
.work_groups_start
;
2071 cs_prog_data
->uses_num_work_groups
= true;
2073 fs_reg surf_index
= brw_imm_ud(surface
);
2074 brw_mark_surface_used(prog_data
, surface
);
2076 /* Read the 3 GLuint components of gl_NumWorkGroups */
2077 for (unsigned i
= 0; i
< 3; i
++) {
2078 fs_reg read_result
=
2079 emit_untyped_read(bld
, surf_index
,
2081 1 /* dims */, 1 /* size */,
2082 BRW_PREDICATE_NONE
);
2083 read_result
.type
= dest
.type
;
2084 bld
.MOV(dest
, read_result
);
2085 dest
= offset(dest
, bld
, 1);
2091 nir_emit_intrinsic(bld
, instr
);
2097 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
2100 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2101 dest
= get_nir_dest(instr
->dest
);
2103 bool has_indirect
= false;
2105 switch (instr
->intrinsic
) {
2106 case nir_intrinsic_atomic_counter_inc
:
2107 case nir_intrinsic_atomic_counter_dec
:
2108 case nir_intrinsic_atomic_counter_read
: {
2109 using namespace surface_access
;
2111 /* Get the arguments of the atomic intrinsic. */
2112 const fs_reg offset
= get_nir_src(instr
->src
[0]);
2113 const unsigned surface
= (stage_prog_data
->binding_table
.abo_start
+
2114 instr
->const_index
[0]);
2117 /* Emit a surface read or atomic op. */
2118 switch (instr
->intrinsic
) {
2119 case nir_intrinsic_atomic_counter_read
:
2120 tmp
= emit_untyped_read(bld
, brw_imm_ud(surface
), offset
, 1, 1);
2123 case nir_intrinsic_atomic_counter_inc
:
2124 tmp
= emit_untyped_atomic(bld
, brw_imm_ud(surface
), offset
, fs_reg(),
2125 fs_reg(), 1, 1, BRW_AOP_INC
);
2128 case nir_intrinsic_atomic_counter_dec
:
2129 tmp
= emit_untyped_atomic(bld
, brw_imm_ud(surface
), offset
, fs_reg(),
2130 fs_reg(), 1, 1, BRW_AOP_PREDEC
);
2134 unreachable("Unreachable");
2137 /* Assign the result. */
2138 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), tmp
);
2140 /* Mark the surface as used. */
2141 brw_mark_surface_used(stage_prog_data
, surface
);
2145 case nir_intrinsic_image_load
:
2146 case nir_intrinsic_image_store
:
2147 case nir_intrinsic_image_atomic_add
:
2148 case nir_intrinsic_image_atomic_min
:
2149 case nir_intrinsic_image_atomic_max
:
2150 case nir_intrinsic_image_atomic_and
:
2151 case nir_intrinsic_image_atomic_or
:
2152 case nir_intrinsic_image_atomic_xor
:
2153 case nir_intrinsic_image_atomic_exchange
:
2154 case nir_intrinsic_image_atomic_comp_swap
: {
2155 using namespace image_access
;
2157 /* Get the referenced image variable and type. */
2158 const nir_variable
*var
= instr
->variables
[0]->var
;
2159 const glsl_type
*type
= var
->type
->without_array();
2160 const brw_reg_type base_type
= get_image_base_type(type
);
2162 /* Get some metadata from the image intrinsic. */
2163 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
2164 const unsigned arr_dims
= type
->sampler_array
? 1 : 0;
2165 const unsigned surf_dims
= type
->coordinate_components() - arr_dims
;
2166 const mesa_format format
=
2167 (var
->data
.image
.write_only
? MESA_FORMAT_NONE
:
2168 _mesa_get_shader_image_format(var
->data
.image
.format
));
2170 /* Get the arguments of the image intrinsic. */
2171 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
2172 const fs_reg addr
= retype(get_nir_src(instr
->src
[0]),
2173 BRW_REGISTER_TYPE_UD
);
2174 const fs_reg src0
= (info
->num_srcs
>= 3 ?
2175 retype(get_nir_src(instr
->src
[2]), base_type
) :
2177 const fs_reg src1
= (info
->num_srcs
>= 4 ?
2178 retype(get_nir_src(instr
->src
[3]), base_type
) :
2182 /* Emit an image load, store or atomic op. */
2183 if (instr
->intrinsic
== nir_intrinsic_image_load
)
2184 tmp
= emit_image_load(bld
, image
, addr
, surf_dims
, arr_dims
, format
);
2186 else if (instr
->intrinsic
== nir_intrinsic_image_store
)
2187 emit_image_store(bld
, image
, addr
, src0
, surf_dims
, arr_dims
, format
);
2190 tmp
= emit_image_atomic(bld
, image
, addr
, src0
, src1
,
2191 surf_dims
, arr_dims
, info
->dest_components
,
2192 get_image_atomic_op(instr
->intrinsic
, type
));
2194 /* Assign the result. */
2195 for (unsigned c
= 0; c
< info
->dest_components
; ++c
)
2196 bld
.MOV(offset(retype(dest
, base_type
), bld
, c
),
2197 offset(tmp
, bld
, c
));
2201 case nir_intrinsic_memory_barrier_atomic_counter
:
2202 case nir_intrinsic_memory_barrier_buffer
:
2203 case nir_intrinsic_memory_barrier_image
:
2204 case nir_intrinsic_memory_barrier
: {
2205 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 16 / dispatch_width
);
2206 bld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
)
2211 case nir_intrinsic_group_memory_barrier
:
2212 case nir_intrinsic_memory_barrier_shared
:
2213 /* We treat these workgroup-level barriers as no-ops. This should be
2214 * safe at present and as long as:
2216 * - Memory access instructions are not subsequently reordered by the
2217 * compiler back-end.
2219 * - All threads from a given compute shader workgroup fit within a
2220 * single subslice and therefore talk to the same HDC shared unit
2221 * what supposedly guarantees ordering and coherency between threads
2222 * from the same workgroup. This may change in the future when we
2223 * start splitting workgroups across multiple subslices.
2225 * - The context is not in fault-and-stream mode, which could cause
2226 * memory transactions (including to SLM) prior to the barrier to be
2227 * replayed after the barrier if a pagefault occurs. This shouldn't
2228 * be a problem up to and including SKL because fault-and-stream is
2229 * not usable due to hardware issues, but that's likely to change in
2234 case nir_intrinsic_shader_clock
: {
2235 /* We cannot do anything if there is an event, so ignore it for now */
2236 fs_reg shader_clock
= get_timestamp(bld
);
2237 const fs_reg srcs
[] = { shader_clock
.set_smear(0), shader_clock
.set_smear(1) };
2239 bld
.LOAD_PAYLOAD(dest
, srcs
, ARRAY_SIZE(srcs
), 0);
2243 case nir_intrinsic_image_size
: {
2244 /* Get the referenced image variable and type. */
2245 const nir_variable
*var
= instr
->variables
[0]->var
;
2246 const glsl_type
*type
= var
->type
->without_array();
2248 /* Get the size of the image. */
2249 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
2250 const fs_reg size
= offset(image
, bld
, BRW_IMAGE_PARAM_SIZE_OFFSET
);
2252 /* For 1DArray image types, the array index is stored in the Z component.
2253 * Fix this by swizzling the Z component to the Y component.
2255 const bool is_1d_array_image
=
2256 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_1D
&&
2257 type
->sampler_array
;
2259 /* For CubeArray images, we should count the number of cubes instead
2260 * of the number of faces. Fix it by dividing the (Z component) by 6.
2262 const bool is_cube_array_image
=
2263 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
2264 type
->sampler_array
;
2266 /* Copy all the components. */
2267 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
2268 for (unsigned c
= 0; c
< info
->dest_components
; ++c
) {
2269 if ((int)c
>= type
->coordinate_components()) {
2270 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
2272 } else if (c
== 1 && is_1d_array_image
) {
2273 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
2274 offset(size
, bld
, 2));
2275 } else if (c
== 2 && is_cube_array_image
) {
2276 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
,
2277 offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
2278 offset(size
, bld
, c
), brw_imm_d(6));
2280 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
2281 offset(size
, bld
, c
));
2288 case nir_intrinsic_image_samples
:
2289 /* The driver does not support multi-sampled images. */
2290 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(1));
2293 case nir_intrinsic_load_uniform_indirect
:
2294 has_indirect
= true;
2296 case nir_intrinsic_load_uniform
: {
2297 fs_reg
uniform_reg(UNIFORM
, instr
->const_index
[0]);
2298 uniform_reg
.reg_offset
= instr
->const_index
[1];
2300 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
2301 fs_reg src
= offset(retype(uniform_reg
, dest
.type
), bld
, j
);
2303 src
.reladdr
= new(mem_ctx
) fs_reg(get_nir_src(instr
->src
[0]));
2306 dest
= offset(dest
, bld
, 1);
2311 case nir_intrinsic_load_ubo_indirect
:
2312 has_indirect
= true;
2314 case nir_intrinsic_load_ubo
: {
2315 nir_const_value
*const_index
= nir_src_as_const_value(instr
->src
[0]);
2319 const unsigned index
= stage_prog_data
->binding_table
.ubo_start
+
2321 surf_index
= brw_imm_ud(index
);
2322 brw_mark_surface_used(prog_data
, index
);
2324 /* The block index is not a constant. Evaluate the index expression
2325 * per-channel and add the base UBO index; we have to select a value
2326 * from any live channel.
2328 surf_index
= vgrf(glsl_type::uint_type
);
2329 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
2330 brw_imm_ud(stage_prog_data
->binding_table
.ubo_start
));
2331 surf_index
= bld
.emit_uniformize(surf_index
);
2333 /* Assume this may touch any UBO. It would be nice to provide
2334 * a tighter bound, but the array information is already lowered away.
2336 brw_mark_surface_used(prog_data
,
2337 stage_prog_data
->binding_table
.ubo_start
+
2338 nir
->info
.num_ubos
- 1);
2342 /* Turn the byte offset into a dword offset. */
2343 fs_reg base_offset
= vgrf(glsl_type::int_type
);
2344 bld
.SHR(base_offset
, retype(get_nir_src(instr
->src
[1]),
2345 BRW_REGISTER_TYPE_D
),
2348 unsigned vec4_offset
= instr
->const_index
[0] / 4;
2349 for (int i
= 0; i
< instr
->num_components
; i
++)
2350 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
2351 base_offset
, vec4_offset
+ i
);
2353 fs_reg packed_consts
= vgrf(glsl_type::float_type
);
2354 packed_consts
.type
= dest
.type
;
2356 struct brw_reg const_offset_reg
= brw_imm_ud(instr
->const_index
[0] & ~15);
2357 bld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
, packed_consts
,
2358 surf_index
, const_offset_reg
);
2360 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2361 packed_consts
.set_smear(instr
->const_index
[0] % 16 / 4 + i
);
2363 /* The std140 packing rules don't allow vectors to cross 16-byte
2364 * boundaries, and a reg is 32 bytes.
2366 assert(packed_consts
.subreg_offset
< 32);
2368 bld
.MOV(dest
, packed_consts
);
2369 dest
= offset(dest
, bld
, 1);
2375 case nir_intrinsic_load_ssbo_indirect
:
2376 has_indirect
= true;
2378 case nir_intrinsic_load_ssbo
: {
2379 assert(devinfo
->gen
>= 7);
2381 nir_const_value
*const_uniform_block
=
2382 nir_src_as_const_value(instr
->src
[0]);
2385 if (const_uniform_block
) {
2386 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
2387 const_uniform_block
->u
[0];
2388 surf_index
= brw_imm_ud(index
);
2389 brw_mark_surface_used(prog_data
, index
);
2391 surf_index
= vgrf(glsl_type::uint_type
);
2392 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
2393 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
2395 /* Assume this may touch any UBO. It would be nice to provide
2396 * a tighter bound, but the array information is already lowered away.
2398 brw_mark_surface_used(prog_data
,
2399 stage_prog_data
->binding_table
.ssbo_start
+
2400 nir
->info
.num_ssbos
- 1);
2403 /* Get the offset to read from */
2406 offset_reg
= get_nir_src(instr
->src
[1]);
2408 offset_reg
= brw_imm_ud(instr
->const_index
[0]);
2411 /* Read the vector */
2412 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, offset_reg
,
2414 instr
->num_components
,
2415 BRW_PREDICATE_NONE
);
2416 read_result
.type
= dest
.type
;
2417 for (int i
= 0; i
< instr
->num_components
; i
++)
2418 bld
.MOV(offset(dest
, bld
, i
), offset(read_result
, bld
, i
));
2423 case nir_intrinsic_load_input_indirect
:
2424 has_indirect
= true;
2426 case nir_intrinsic_load_input
: {
2428 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
2430 if (stage
== MESA_SHADER_VERTEX
) {
2431 src
= offset(fs_reg(ATTR
, instr
->const_index
[0], dest
.type
), bld
, index
);
2433 src
= offset(retype(nir_inputs
, dest
.type
), bld
,
2434 instr
->const_index
[0] + index
);
2437 src
.reladdr
= new(mem_ctx
) fs_reg(get_nir_src(instr
->src
[0]));
2441 dest
= offset(dest
, bld
, 1);
2446 case nir_intrinsic_store_ssbo_indirect
:
2447 has_indirect
= true;
2449 case nir_intrinsic_store_ssbo
: {
2450 assert(devinfo
->gen
>= 7);
2454 nir_const_value
*const_uniform_block
=
2455 nir_src_as_const_value(instr
->src
[1]);
2456 if (const_uniform_block
) {
2457 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
2458 const_uniform_block
->u
[0];
2459 surf_index
= brw_imm_ud(index
);
2460 brw_mark_surface_used(prog_data
, index
);
2462 surf_index
= vgrf(glsl_type::uint_type
);
2463 bld
.ADD(surf_index
, get_nir_src(instr
->src
[1]),
2464 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
2466 brw_mark_surface_used(prog_data
,
2467 stage_prog_data
->binding_table
.ssbo_start
+
2468 nir
->info
.num_ssbos
- 1);
2472 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
2475 unsigned writemask
= instr
->const_index
[1];
2477 /* Combine groups of consecutive enabled channels in one write
2478 * message. We use ffs to find the first enabled channel and then ffs on
2479 * the bit-inverse, down-shifted writemask to determine the length of
2480 * the block of enabled bits.
2483 unsigned first_component
= ffs(writemask
) - 1;
2484 unsigned length
= ffs(~(writemask
>> first_component
)) - 1;
2487 if (!has_indirect
) {
2488 offset_reg
= brw_imm_ud(instr
->const_index
[0] + 4 * first_component
);
2490 offset_reg
= vgrf(glsl_type::uint_type
);
2492 retype(get_nir_src(instr
->src
[2]), BRW_REGISTER_TYPE_UD
),
2493 brw_imm_ud(4 * first_component
));
2496 emit_untyped_write(bld
, surf_index
, offset_reg
,
2497 offset(val_reg
, bld
, first_component
),
2498 1 /* dims */, length
,
2499 BRW_PREDICATE_NONE
);
2501 /* Clear the bits in the writemask that we just wrote, then try
2502 * again to see if more channels are left.
2504 writemask
&= (15 << (first_component
+ length
));
2509 case nir_intrinsic_store_output_indirect
:
2510 has_indirect
= true;
2512 case nir_intrinsic_store_output
: {
2513 fs_reg src
= get_nir_src(instr
->src
[0]);
2515 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
2516 fs_reg new_dest
= offset(retype(nir_outputs
, src
.type
), bld
,
2517 instr
->const_index
[0] + index
);
2519 src
.reladdr
= new(mem_ctx
) fs_reg(get_nir_src(instr
->src
[1]));
2521 bld
.MOV(new_dest
, src
);
2522 src
= offset(src
, bld
, 1);
2527 case nir_intrinsic_ssbo_atomic_add
:
2528 nir_emit_ssbo_atomic(bld
, BRW_AOP_ADD
, instr
);
2530 case nir_intrinsic_ssbo_atomic_imin
:
2531 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMIN
, instr
);
2533 case nir_intrinsic_ssbo_atomic_umin
:
2534 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMIN
, instr
);
2536 case nir_intrinsic_ssbo_atomic_imax
:
2537 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMAX
, instr
);
2539 case nir_intrinsic_ssbo_atomic_umax
:
2540 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMAX
, instr
);
2542 case nir_intrinsic_ssbo_atomic_and
:
2543 nir_emit_ssbo_atomic(bld
, BRW_AOP_AND
, instr
);
2545 case nir_intrinsic_ssbo_atomic_or
:
2546 nir_emit_ssbo_atomic(bld
, BRW_AOP_OR
, instr
);
2548 case nir_intrinsic_ssbo_atomic_xor
:
2549 nir_emit_ssbo_atomic(bld
, BRW_AOP_XOR
, instr
);
2551 case nir_intrinsic_ssbo_atomic_exchange
:
2552 nir_emit_ssbo_atomic(bld
, BRW_AOP_MOV
, instr
);
2554 case nir_intrinsic_ssbo_atomic_comp_swap
:
2555 nir_emit_ssbo_atomic(bld
, BRW_AOP_CMPWR
, instr
);
2558 case nir_intrinsic_get_buffer_size
: {
2559 nir_const_value
*const_uniform_block
= nir_src_as_const_value(instr
->src
[0]);
2560 unsigned ssbo_index
= const_uniform_block
? const_uniform_block
->u
[0] : 0;
2561 int reg_width
= dispatch_width
/ 8;
2564 fs_reg source
= brw_imm_d(0);
2566 int mlen
= 1 * reg_width
;
2568 /* A resinfo's sampler message is used to get the buffer size.
2569 * The SIMD8's writeback message consists of four registers and
2570 * SIMD16's writeback message consists of 8 destination registers
2571 * (two per each component), although we are only interested on the
2572 * first component, where resinfo returns the buffer size for
2575 int regs_written
= 4 * mlen
;
2576 fs_reg src_payload
= fs_reg(VGRF
, alloc
.allocate(mlen
),
2577 BRW_REGISTER_TYPE_UD
);
2578 bld
.LOAD_PAYLOAD(src_payload
, &source
, 1, 0);
2579 fs_reg buffer_size
= fs_reg(VGRF
, alloc
.allocate(regs_written
),
2580 BRW_REGISTER_TYPE_UD
);
2581 const unsigned index
= prog_data
->binding_table
.ssbo_start
+ ssbo_index
;
2582 fs_inst
*inst
= bld
.emit(FS_OPCODE_GET_BUFFER_SIZE
, buffer_size
,
2583 src_payload
, brw_imm_ud(index
));
2584 inst
->header_size
= 0;
2586 inst
->regs_written
= regs_written
;
2588 bld
.MOV(retype(dest
, buffer_size
.type
), buffer_size
);
2590 brw_mark_surface_used(prog_data
, index
);
2595 unreachable("unknown intrinsic");
2600 fs_visitor::nir_emit_ssbo_atomic(const fs_builder
&bld
,
2601 int op
, nir_intrinsic_instr
*instr
)
2604 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2605 dest
= get_nir_dest(instr
->dest
);
2608 nir_const_value
*const_surface
= nir_src_as_const_value(instr
->src
[0]);
2609 if (const_surface
) {
2610 unsigned surf_index
= stage_prog_data
->binding_table
.ssbo_start
+
2611 const_surface
->u
[0];
2612 surface
= brw_imm_ud(surf_index
);
2613 brw_mark_surface_used(prog_data
, surf_index
);
2615 surface
= vgrf(glsl_type::uint_type
);
2616 bld
.ADD(surface
, get_nir_src(instr
->src
[0]),
2617 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
2619 /* Assume this may touch any SSBO. This is the same we do for other
2620 * UBO/SSBO accesses with non-constant surface.
2622 brw_mark_surface_used(prog_data
,
2623 stage_prog_data
->binding_table
.ssbo_start
+
2624 nir
->info
.num_ssbos
- 1);
2627 fs_reg offset
= get_nir_src(instr
->src
[1]);
2628 fs_reg data1
= get_nir_src(instr
->src
[2]);
2630 if (op
== BRW_AOP_CMPWR
)
2631 data2
= get_nir_src(instr
->src
[3]);
2633 /* Emit the actual atomic operation operation */
2635 fs_reg atomic_result
=
2636 surface_access::emit_untyped_atomic(bld
, surface
, offset
,
2638 1 /* dims */, 1 /* rsize */,
2640 BRW_PREDICATE_NONE
);
2641 dest
.type
= atomic_result
.type
;
2642 bld
.MOV(dest
, atomic_result
);
2646 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
2648 unsigned sampler
= instr
->sampler_index
;
2649 fs_reg
sampler_reg(brw_imm_ud(sampler
));
2651 int gather_component
= instr
->component
;
2653 bool is_cube_array
= instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
2656 int lod_components
= 0;
2657 int UNUSED offset_components
= 0;
2659 fs_reg coordinate
, shadow_comparitor
, lod
, lod2
, sample_index
, mcs
, tex_offset
;
2661 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
2662 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
2663 switch (instr
->src
[i
].src_type
) {
2664 case nir_tex_src_bias
:
2665 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
2667 case nir_tex_src_comparitor
:
2668 shadow_comparitor
= retype(src
, BRW_REGISTER_TYPE_F
);
2670 case nir_tex_src_coord
:
2671 switch (instr
->op
) {
2673 case nir_texop_txf_ms
:
2674 case nir_texop_samples_identical
:
2675 coordinate
= retype(src
, BRW_REGISTER_TYPE_D
);
2678 coordinate
= retype(src
, BRW_REGISTER_TYPE_F
);
2682 case nir_tex_src_ddx
:
2683 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
2684 lod_components
= nir_tex_instr_src_size(instr
, i
);
2686 case nir_tex_src_ddy
:
2687 lod2
= retype(src
, BRW_REGISTER_TYPE_F
);
2689 case nir_tex_src_lod
:
2690 switch (instr
->op
) {
2692 lod
= retype(src
, BRW_REGISTER_TYPE_UD
);
2695 lod
= retype(src
, BRW_REGISTER_TYPE_D
);
2698 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
2702 case nir_tex_src_ms_index
:
2703 sample_index
= retype(src
, BRW_REGISTER_TYPE_UD
);
2705 case nir_tex_src_offset
:
2706 tex_offset
= retype(src
, BRW_REGISTER_TYPE_D
);
2707 if (instr
->is_array
)
2708 offset_components
= instr
->coord_components
- 1;
2710 offset_components
= instr
->coord_components
;
2712 case nir_tex_src_projector
:
2713 unreachable("should be lowered");
2715 case nir_tex_src_sampler_offset
: {
2716 /* Figure out the highest possible sampler index and mark it as used */
2717 uint32_t max_used
= sampler
+ instr
->sampler_array_size
- 1;
2718 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
< 8) {
2719 max_used
+= stage_prog_data
->binding_table
.gather_texture_start
;
2721 max_used
+= stage_prog_data
->binding_table
.texture_start
;
2723 brw_mark_surface_used(prog_data
, max_used
);
2725 /* Emit code to evaluate the actual indexing expression */
2726 sampler_reg
= vgrf(glsl_type::uint_type
);
2727 bld
.ADD(sampler_reg
, src
, brw_imm_ud(sampler
));
2728 sampler_reg
= bld
.emit_uniformize(sampler_reg
);
2733 unreachable("unknown texture source");
2737 if (instr
->op
== nir_texop_txf_ms
||
2738 instr
->op
== nir_texop_samples_identical
) {
2739 if (devinfo
->gen
>= 7 &&
2740 key_tex
->compressed_multisample_layout_mask
& (1 << sampler
)) {
2741 mcs
= emit_mcs_fetch(coordinate
, instr
->coord_components
, sampler_reg
);
2743 mcs
= brw_imm_ud(0u);
2747 for (unsigned i
= 0; i
< 3; i
++) {
2748 if (instr
->const_offset
[i
] != 0) {
2749 assert(offset_components
== 0);
2750 tex_offset
= brw_imm_ud(brw_texture_offset(instr
->const_offset
, 3));
2755 enum glsl_base_type dest_base_type
=
2756 brw_glsl_base_type_for_nir_type (instr
->dest_type
);
2758 const glsl_type
*dest_type
=
2759 glsl_type::get_instance(dest_base_type
, nir_tex_instr_dest_size(instr
),
2762 ir_texture_opcode op
;
2763 switch (instr
->op
) {
2764 case nir_texop_lod
: op
= ir_lod
; break;
2765 case nir_texop_query_levels
: op
= ir_query_levels
; break;
2766 case nir_texop_tex
: op
= ir_tex
; break;
2767 case nir_texop_tg4
: op
= ir_tg4
; break;
2768 case nir_texop_txb
: op
= ir_txb
; break;
2769 case nir_texop_txd
: op
= ir_txd
; break;
2770 case nir_texop_txf
: op
= ir_txf
; break;
2771 case nir_texop_txf_ms
: op
= ir_txf_ms
; break;
2772 case nir_texop_txl
: op
= ir_txl
; break;
2773 case nir_texop_txs
: op
= ir_txs
; break;
2774 case nir_texop_texture_samples
: {
2775 fs_reg dst
= retype(get_nir_dest(instr
->dest
), BRW_REGISTER_TYPE_D
);
2776 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_SAMPLEINFO
, dst
,
2777 bld
.vgrf(BRW_REGISTER_TYPE_D
, 1),
2780 inst
->header_size
= 1;
2781 inst
->base_mrf
= -1;
2784 case nir_texop_samples_identical
: op
= ir_samples_identical
; break;
2786 unreachable("unknown texture opcode");
2789 emit_texture(op
, dest_type
, coordinate
, instr
->coord_components
,
2790 shadow_comparitor
, lod
, lod2
, lod_components
, sample_index
,
2791 tex_offset
, mcs
, gather_component
,
2792 is_cube_array
, sampler
, sampler_reg
);
2794 fs_reg dest
= get_nir_dest(instr
->dest
);
2795 dest
.type
= this->result
.type
;
2796 unsigned num_components
= nir_tex_instr_dest_size(instr
);
2797 emit_percomp(bld
, fs_inst(BRW_OPCODE_MOV
, bld
.dispatch_width(),
2798 dest
, this->result
),
2799 (1 << num_components
) - 1);
2803 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
2805 switch (instr
->type
) {
2806 case nir_jump_break
:
2807 bld
.emit(BRW_OPCODE_BREAK
);
2809 case nir_jump_continue
:
2810 bld
.emit(BRW_OPCODE_CONTINUE
);
2812 case nir_jump_return
:
2814 unreachable("unknown jump");