src/mesa/drivers/dri/i965/brw_gs_emit.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33 #include "main/glheader.h"
  34 #include "main/macros.h"
  35 #include "main/enums.h"
  36
  37 #include "program/program.h"
  38 #include "intel_batchbuffer.h"
  39
  40 #include "brw_defines.h"
  41 #include "brw_context.h"
  42 #include "brw_eu.h"
  43 #include "brw_gs.h"
  44
  45 static void brw_gs_alloc_regs( struct brw_gs_compile *c,
  46                                GLuint nr_verts )
  47 {
  48    GLuint i = 0,j;
  49
  50    /* Register usage is static, precompute here:
  51     */
  52    c->reg.R0 = retype(brw_vec8_grf(i, 0), BRW_REGISTER_TYPE_UD); i++;
  53
  54    /* Payload vertices plus space for more generated vertices:
  55     */
  56    for (j = 0; j < nr_verts; j++) {
  57       c->reg.vertex[j] = brw_vec4_grf(i, 0);
  58       i += c->nr_regs;
  59    }
  60
  61    c->reg.header = retype(brw_vec8_grf(i++, 0), BRW_REGISTER_TYPE_UD);
  62    c->reg.temp = retype(brw_vec8_grf(i++, 0), BRW_REGISTER_TYPE_UD);
  63
  64    c->prog_data.urb_read_length = c->nr_regs;
  65    c->prog_data.total_grf = i;
  66 }
  67
  68
  69 /**
  70  * Set up the initial value of c->reg.header register based on c->reg.R0.
  71  *
  72  * The following information is passed to the GS thread in R0, and needs to be
  73  * included in the first URB_WRITE or FF_SYNC message sent by the GS:
  74  *
  75  * - DWORD 0 [31:0] handle info (Gen4 only)
  76  * - DWORD 5 [7:0] FFTID
  77  * - DWORD 6 [31:0] Debug info
  78  * - DWORD 7 [31:0] Debug info
  79  *
  80  * This function sets up the above data by copying by copying the contents of
  81  * R0 to the header register.
  82  */
  83 static void brw_gs_initialize_header(struct brw_gs_compile *c)
  84 {
  85    struct brw_compile *p = &c->func;
  86    brw_MOV(p, c->reg.header, c->reg.R0);
  87 }
  88
  89 /**
  90  * Overwrite DWORD 2 of c->reg.header with the given immediate unsigned value.
  91  *
  92  * In URB_WRITE messages, DWORD 2 contains the fields PrimType, PrimStart,
  93  * PrimEnd, Increment CL_INVOCATIONS, and SONumPrimsWritten, many of which we
  94  * need to be able to update on a per-vertex basis.
  95  */
  96 static void brw_gs_overwrite_header_dw2(struct brw_gs_compile *c,
  97                                         unsigned dw2)
  98 {
  99    struct brw_compile *p = &c->func;
 100    brw_MOV(p, get_element_ud(c->reg.header, 2), brw_imm_ud(dw2));
 101 }
 102
 103 /**
 104  * Emit a vertex using the URB_WRITE message.  Use the contents of
 105  * c->reg.header for the message header, and the registers starting at \c vert
 106  * for the vertex data.
 107  *
 108  * If \c last is true, then this is the last vertex, so no further URB space
 109  * should be allocated, and this message should end the thread.
 110  *
 111  * If \c last is false, then a new URB entry will be allocated, and its handle
 112  * will be stored in DWORD 0 of c->reg.header for use in the next URB_WRITE
 113  * message.
 114  */
 115 static void brw_gs_emit_vue(struct brw_gs_compile *c,
 116                             struct brw_reg vert,
 117                             bool last)
 118 {
 119    struct brw_compile *p = &c->func;
 120    bool allocate = !last;
 121
 122    /* Copy the vertex from vertn into m1..mN+1:
 123     */
 124    brw_copy8(p, brw_message_reg(1), vert, c->nr_regs);
 125
 126    /* Send each vertex as a seperate write to the urb.  This is
 127     * different to the concept in brw_sf_emit.c, where subsequent
 128     * writes are used to build up a single urb entry.  Each of these
 129     * writes instantiates a seperate urb entry, and a new one must be
 130     * allocated each time.
 131     */
 132    brw_urb_WRITE(p,
 133                  allocate ? c->reg.temp
 134                           : retype(brw_null_reg(), BRW_REGISTER_TYPE_UD),
 135                  0,
 136                  c->reg.header,
 137                  allocate,
 138                  1,             /* used */
 139                  c->nr_regs + 1, /* msg length */
 140                  allocate ? 1 : 0, /* response length */
 141                  allocate ? 0 : 1, /* eot */
 142                  1,             /* writes_complete */
 143                  0,             /* urb offset */
 144                  BRW_URB_SWIZZLE_NONE);
 145
 146    if (allocate) {
 147       brw_MOV(p, get_element_ud(c->reg.header, 0),
 148               get_element_ud(c->reg.temp, 0));
 149    }
 150 }
 151
 152 /**
 153  * Send an FF_SYNC message to ensure that all previously spawned GS threads
 154  * have finished sending primitives down the pipeline, and to allocate a URB
 155  * entry for the first output vertex.  Only needed when intel->needs_ff_sync
 156  * is true.
 157  *
 158  * This function modifies c->reg.header: in DWORD 1, it stores num_prim (which
 159  * is needed by the FF_SYNC message), and in DWORD 0, it stores the handle to
 160  * the allocated URB entry (which will be needed by the URB_WRITE meesage that
 161  * follows).
 162  */
 163 static void brw_gs_ff_sync(struct brw_gs_compile *c, int num_prim)
 164 {
 165    struct brw_compile *p = &c->func;
 166
 167    brw_MOV(p, get_element_ud(c->reg.header, 1), brw_imm_ud(num_prim));
 168    brw_ff_sync(p,
 169                c->reg.temp,
 170                0,
 171                c->reg.header,
 172                1, /* allocate */
 173                1, /* response length */
 174                0 /* eot */);
 175    brw_MOV(p, get_element_ud(c->reg.header, 0),
 176            get_element_ud(c->reg.temp, 0));
 177 }
 178
 179
 180 void brw_gs_quads( struct brw_gs_compile *c, struct brw_gs_prog_key *key )
 181 {
 182    struct intel_context *intel = &c->func.brw->intel;
 183
 184    brw_gs_alloc_regs(c, 4);
 185    brw_gs_initialize_header(c);
 186    /* Use polygons for correct edgeflag behaviour. Note that vertex 3
 187     * is the PV for quads, but vertex 0 for polygons:
 188     */
 189    if (intel->needs_ff_sync)
 190       brw_gs_ff_sync(c, 1);
 191    brw_gs_overwrite_header_dw2(
 192       c, ((_3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT)
 193           | URB_WRITE_PRIM_START));
 194    if (key->pv_first) {
 195       brw_gs_emit_vue(c, c->reg.vertex[0], 0);
 196       brw_gs_overwrite_header_dw2(
 197          c, _3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT);
 198       brw_gs_emit_vue(c, c->reg.vertex[1], 0);
 199       brw_gs_emit_vue(c, c->reg.vertex[2], 0);
 200       brw_gs_overwrite_header_dw2(
 201          c, ((_3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT)
 202              | URB_WRITE_PRIM_END));
 203       brw_gs_emit_vue(c, c->reg.vertex[3], 1);
 204    }
 205    else {
 206       brw_gs_emit_vue(c, c->reg.vertex[3], 0);
 207       brw_gs_overwrite_header_dw2(
 208          c, _3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT);
 209       brw_gs_emit_vue(c, c->reg.vertex[0], 0);
 210       brw_gs_emit_vue(c, c->reg.vertex[1], 0);
 211       brw_gs_overwrite_header_dw2(
 212          c, ((_3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT)
 213              | URB_WRITE_PRIM_END));
 214       brw_gs_emit_vue(c, c->reg.vertex[2], 1);
 215    }
 216 }
 217
 218 void brw_gs_quad_strip( struct brw_gs_compile *c, struct brw_gs_prog_key *key )
 219 {
 220    struct intel_context *intel = &c->func.brw->intel;
 221
 222    brw_gs_alloc_regs(c, 4);
 223    brw_gs_initialize_header(c);
 224
 225    if (intel->needs_ff_sync)
 226       brw_gs_ff_sync(c, 1);
 227    brw_gs_overwrite_header_dw2(
 228       c, ((_3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT)
 229           | URB_WRITE_PRIM_START));
 230    if (key->pv_first) {
 231       brw_gs_emit_vue(c, c->reg.vertex[0], 0);
 232       brw_gs_overwrite_header_dw2(
 233          c, _3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT);
 234       brw_gs_emit_vue(c, c->reg.vertex[1], 0);
 235       brw_gs_emit_vue(c, c->reg.vertex[2], 0);
 236       brw_gs_overwrite_header_dw2(
 237          c, ((_3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT)
 238              | URB_WRITE_PRIM_END));
 239       brw_gs_emit_vue(c, c->reg.vertex[3], 1);
 240    }
 241    else {
 242       brw_gs_emit_vue(c, c->reg.vertex[2], 0);
 243       brw_gs_overwrite_header_dw2(
 244          c, _3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT);
 245       brw_gs_emit_vue(c, c->reg.vertex[3], 0);
 246       brw_gs_emit_vue(c, c->reg.vertex[0], 0);
 247       brw_gs_overwrite_header_dw2(
 248          c, ((_3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT)
 249              | URB_WRITE_PRIM_END));
 250       brw_gs_emit_vue(c, c->reg.vertex[1], 1);
 251    }
 252 }
 253
 254 void brw_gs_lines( struct brw_gs_compile *c )
 255 {
 256    struct intel_context *intel = &c->func.brw->intel;
 257
 258    brw_gs_alloc_regs(c, 2);
 259    brw_gs_initialize_header(c);
 260
 261    if (intel->needs_ff_sync)
 262       brw_gs_ff_sync(c, 1);
 263    brw_gs_overwrite_header_dw2(
 264       c, ((_3DPRIM_LINESTRIP << URB_WRITE_PRIM_TYPE_SHIFT)
 265           | URB_WRITE_PRIM_START));
 266    brw_gs_emit_vue(c, c->reg.vertex[0], 0);
 267    brw_gs_overwrite_header_dw2(
 268       c, ((_3DPRIM_LINESTRIP << URB_WRITE_PRIM_TYPE_SHIFT)
 269           | URB_WRITE_PRIM_END));
 270    brw_gs_emit_vue(c, c->reg.vertex[1], 1);
 271 }