src/mesa/drivers/dri/i965/brw_gs_emit.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33 #include "main/glheader.h"
  34 #include "main/macros.h"
  35 #include "main/enums.h"
  36
  37 #include "program/program.h"
  38 #include "intel_batchbuffer.h"
  39
  40 #include "brw_defines.h"
  41 #include "brw_context.h"
  42 #include "brw_eu.h"
  43 #include "brw_gs.h"
  44
  45 /**
  46  * Allocate registers for GS.
  47  *
  48  * If sol_program is true, then:
  49  *
  50  * - The thread will be spawned with the "SVBI Payload Enable" bit set, so GRF
  51  *   1 needs to be set aside to hold the streamed vertex buffer indices.
  52  *
  53  * - The thread will need to use the destination_indices register.
  54  */
  55 static void brw_ff_gs_alloc_regs(struct brw_ff_gs_compile *c,
  56                                  GLuint nr_verts,
  57                                  bool sol_program)
  58 {
  59    GLuint i = 0,j;
  60
  61    /* Register usage is static, precompute here:
  62     */
  63    c->reg.R0 = retype(brw_vec8_grf(i, 0), BRW_REGISTER_TYPE_UD); i++;
  64
  65    /* Streamed vertex buffer indices */
  66    if (sol_program)
  67       c->reg.SVBI = retype(brw_vec8_grf(i++, 0), BRW_REGISTER_TYPE_UD);
  68
  69    /* Payload vertices plus space for more generated vertices:
  70     */
  71    for (j = 0; j < nr_verts; j++) {
  72       c->reg.vertex[j] = brw_vec4_grf(i, 0);
  73       i += c->nr_regs;
  74    }
  75
  76    c->reg.header = retype(brw_vec8_grf(i++, 0), BRW_REGISTER_TYPE_UD);
  77    c->reg.temp = retype(brw_vec8_grf(i++, 0), BRW_REGISTER_TYPE_UD);
  78
  79    if (sol_program) {
  80       c->reg.destination_indices =
  81          retype(brw_vec4_grf(i++, 0), BRW_REGISTER_TYPE_UD);
  82    }
  83
  84    c->prog_data.urb_read_length = c->nr_regs;
  85    c->prog_data.total_grf = i;
  86 }
  87
  88
  89 /**
  90  * Set up the initial value of c->reg.header register based on c->reg.R0.
  91  *
  92  * The following information is passed to the GS thread in R0, and needs to be
  93  * included in the first URB_WRITE or FF_SYNC message sent by the GS:
  94  *
  95  * - DWORD 0 [31:0] handle info (Gen4 only)
  96  * - DWORD 5 [7:0] FFTID
  97  * - DWORD 6 [31:0] Debug info
  98  * - DWORD 7 [31:0] Debug info
  99  *
 100  * This function sets up the above data by copying by copying the contents of
 101  * R0 to the header register.
 102  */
 103 static void brw_ff_gs_initialize_header(struct brw_ff_gs_compile *c)
 104 {
 105    struct brw_compile *p = &c->func;
 106    brw_MOV(p, c->reg.header, c->reg.R0);
 107 }
 108
 109 /**
 110  * Overwrite DWORD 2 of c->reg.header with the given immediate unsigned value.
 111  *
 112  * In URB_WRITE messages, DWORD 2 contains the fields PrimType, PrimStart,
 113  * PrimEnd, Increment CL_INVOCATIONS, and SONumPrimsWritten, many of which we
 114  * need to be able to update on a per-vertex basis.
 115  */
 116 static void brw_ff_gs_overwrite_header_dw2(struct brw_ff_gs_compile *c,
 117                                            unsigned dw2)
 118 {
 119    struct brw_compile *p = &c->func;
 120    brw_MOV(p, get_element_ud(c->reg.header, 2), brw_imm_ud(dw2));
 121 }
 122
 123 /**
 124  * Overwrite DWORD 2 of c->reg.header with the primitive type from c->reg.R0.
 125  *
 126  * When the thread is spawned, GRF 0 contains the primitive type in bits 4:0
 127  * of DWORD 2.  URB_WRITE messages need the primitive type in bits 6:2 of
 128  * DWORD 2.  So this function extracts the primitive type field, bitshifts it
 129  * appropriately, and stores it in c->reg.header.
 130  */
 131 static void brw_ff_gs_overwrite_header_dw2_from_r0(struct brw_ff_gs_compile *c)
 132 {
 133    struct brw_compile *p = &c->func;
 134    brw_AND(p, get_element_ud(c->reg.header, 2), get_element_ud(c->reg.R0, 2),
 135            brw_imm_ud(0x1f));
 136    brw_SHL(p, get_element_ud(c->reg.header, 2),
 137            get_element_ud(c->reg.header, 2), brw_imm_ud(2));
 138 }
 139
 140 /**
 141  * Apply an additive offset to DWORD 2 of c->reg.header.
 142  *
 143  * This is used to set/unset the "PrimStart" and "PrimEnd" flags appropriately
 144  * for each vertex.
 145  */
 146 static void brw_ff_gs_offset_header_dw2(struct brw_ff_gs_compile *c,
 147                                         int offset)
 148 {
 149    struct brw_compile *p = &c->func;
 150    brw_ADD(p, get_element_d(c->reg.header, 2), get_element_d(c->reg.header, 2),
 151            brw_imm_d(offset));
 152 }
 153
 154
 155 /**
 156  * Emit a vertex using the URB_WRITE message.  Use the contents of
 157  * c->reg.header for the message header, and the registers starting at \c vert
 158  * for the vertex data.
 159  *
 160  * If \c last is true, then this is the last vertex, so no further URB space
 161  * should be allocated, and this message should end the thread.
 162  *
 163  * If \c last is false, then a new URB entry will be allocated, and its handle
 164  * will be stored in DWORD 0 of c->reg.header for use in the next URB_WRITE
 165  * message.
 166  */
 167 static void brw_ff_gs_emit_vue(struct brw_ff_gs_compile *c,
 168                                struct brw_reg vert,
 169                                bool last)
 170 {
 171    struct brw_compile *p = &c->func;
 172    int write_offset = 0;
 173    bool complete = false;
 174
 175    do {
 176       /* We can't write more than 14 registers at a time to the URB */
 177       int write_len = MIN2(c->nr_regs - write_offset, 14);
 178       if (write_len == c->nr_regs - write_offset)
 179          complete = true;
 180
 181       /* Copy the vertex from vertn into m1..mN+1:
 182        */
 183       brw_copy8(p, brw_message_reg(1), offset(vert, write_offset), write_len);
 184
 185       /* Send the vertex data to the URB.  If this is the last write for this
 186        * vertex, then we mark it as complete, and either end the thread or
 187        * allocate another vertex URB entry (depending whether this is the last
 188        * vertex).
 189        */
 190       enum brw_urb_write_flags flags;
 191       if (!complete)
 192          flags = BRW_URB_WRITE_NO_FLAGS;
 193       else if (last)
 194          flags = BRW_URB_WRITE_EOT_COMPLETE;
 195       else
 196          flags = BRW_URB_WRITE_ALLOCATE_COMPLETE;
 197       brw_urb_WRITE(p,
 198                     (flags & BRW_URB_WRITE_ALLOCATE) ? c->reg.temp
 199                     : retype(brw_null_reg(), BRW_REGISTER_TYPE_UD),
 200                     0,
 201                     c->reg.header,
 202                     flags,
 203                     write_len + 1, /* msg length */
 204                     (flags & BRW_URB_WRITE_ALLOCATE) ? 1
 205                     : 0, /* response length */
 206                     write_offset,  /* urb offset */
 207                     BRW_URB_SWIZZLE_NONE);
 208       write_offset += write_len;
 209    } while (!complete);
 210
 211    if (!last) {
 212       brw_MOV(p, get_element_ud(c->reg.header, 0),
 213               get_element_ud(c->reg.temp, 0));
 214    }
 215 }
 216
 217 /**
 218  * Send an FF_SYNC message to ensure that all previously spawned GS threads
 219  * have finished sending primitives down the pipeline, and to allocate a URB
 220  * entry for the first output vertex.  Only needed on Ironlake+.
 221  *
 222  * This function modifies c->reg.header: in DWORD 1, it stores num_prim (which
 223  * is needed by the FF_SYNC message), and in DWORD 0, it stores the handle to
 224  * the allocated URB entry (which will be needed by the URB_WRITE meesage that
 225  * follows).
 226  */
 227 static void brw_ff_gs_ff_sync(struct brw_ff_gs_compile *c, int num_prim)
 228 {
 229    struct brw_compile *p = &c->func;
 230
 231    brw_MOV(p, get_element_ud(c->reg.header, 1), brw_imm_ud(num_prim));
 232    brw_ff_sync(p,
 233                c->reg.temp,
 234                0,
 235                c->reg.header,
 236                1, /* allocate */
 237                1, /* response length */
 238                0 /* eot */);
 239    brw_MOV(p, get_element_ud(c->reg.header, 0),
 240            get_element_ud(c->reg.temp, 0));
 241 }
 242
 243
 244 void
 245 brw_ff_gs_quads(struct brw_ff_gs_compile *c, struct brw_ff_gs_prog_key *key)
 246 {
 247    struct brw_context *brw = c->func.brw;
 248
 249    brw_ff_gs_alloc_regs(c, 4, false);
 250    brw_ff_gs_initialize_header(c);
 251    /* Use polygons for correct edgeflag behaviour. Note that vertex 3
 252     * is the PV for quads, but vertex 0 for polygons:
 253     */
 254    if (brw->gen == 5)
 255       brw_ff_gs_ff_sync(c, 1);
 256    brw_ff_gs_overwrite_header_dw2(
 257       c, ((_3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT)
 258           | URB_WRITE_PRIM_START));
 259    if (key->pv_first) {
 260       brw_ff_gs_emit_vue(c, c->reg.vertex[0], 0);
 261       brw_ff_gs_overwrite_header_dw2(
 262          c, _3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT);
 263       brw_ff_gs_emit_vue(c, c->reg.vertex[1], 0);
 264       brw_ff_gs_emit_vue(c, c->reg.vertex[2], 0);
 265       brw_ff_gs_overwrite_header_dw2(
 266          c, ((_3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT)
 267              | URB_WRITE_PRIM_END));
 268       brw_ff_gs_emit_vue(c, c->reg.vertex[3], 1);
 269    }
 270    else {
 271       brw_ff_gs_emit_vue(c, c->reg.vertex[3], 0);
 272       brw_ff_gs_overwrite_header_dw2(
 273          c, _3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT);
 274       brw_ff_gs_emit_vue(c, c->reg.vertex[0], 0);
 275       brw_ff_gs_emit_vue(c, c->reg.vertex[1], 0);
 276       brw_ff_gs_overwrite_header_dw2(
 277          c, ((_3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT)
 278              | URB_WRITE_PRIM_END));
 279       brw_ff_gs_emit_vue(c, c->reg.vertex[2], 1);
 280    }
 281 }
 282
 283 void
 284 brw_ff_gs_quad_strip(struct brw_ff_gs_compile *c,
 285                      struct brw_ff_gs_prog_key *key)
 286 {
 287    struct brw_context *brw = c->func.brw;
 288
 289    brw_ff_gs_alloc_regs(c, 4, false);
 290    brw_ff_gs_initialize_header(c);
 291
 292    if (brw->gen == 5)
 293       brw_ff_gs_ff_sync(c, 1);
 294    brw_ff_gs_overwrite_header_dw2(
 295       c, ((_3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT)
 296           | URB_WRITE_PRIM_START));
 297    if (key->pv_first) {
 298       brw_ff_gs_emit_vue(c, c->reg.vertex[0], 0);
 299       brw_ff_gs_overwrite_header_dw2(
 300          c, _3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT);
 301       brw_ff_gs_emit_vue(c, c->reg.vertex[1], 0);
 302       brw_ff_gs_emit_vue(c, c->reg.vertex[2], 0);
 303       brw_ff_gs_overwrite_header_dw2(
 304          c, ((_3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT)
 305              | URB_WRITE_PRIM_END));
 306       brw_ff_gs_emit_vue(c, c->reg.vertex[3], 1);
 307    }
 308    else {
 309       brw_ff_gs_emit_vue(c, c->reg.vertex[2], 0);
 310       brw_ff_gs_overwrite_header_dw2(
 311          c, _3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT);
 312       brw_ff_gs_emit_vue(c, c->reg.vertex[3], 0);
 313       brw_ff_gs_emit_vue(c, c->reg.vertex[0], 0);
 314       brw_ff_gs_overwrite_header_dw2(
 315          c, ((_3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT)
 316              | URB_WRITE_PRIM_END));
 317       brw_ff_gs_emit_vue(c, c->reg.vertex[1], 1);
 318    }
 319 }
 320
 321 void brw_ff_gs_lines(struct brw_ff_gs_compile *c)
 322 {
 323    struct brw_context *brw = c->func.brw;
 324
 325    brw_ff_gs_alloc_regs(c, 2, false);
 326    brw_ff_gs_initialize_header(c);
 327
 328    if (brw->gen == 5)
 329       brw_ff_gs_ff_sync(c, 1);
 330    brw_ff_gs_overwrite_header_dw2(
 331       c, ((_3DPRIM_LINESTRIP << URB_WRITE_PRIM_TYPE_SHIFT)
 332           | URB_WRITE_PRIM_START));
 333    brw_ff_gs_emit_vue(c, c->reg.vertex[0], 0);
 334    brw_ff_gs_overwrite_header_dw2(
 335       c, ((_3DPRIM_LINESTRIP << URB_WRITE_PRIM_TYPE_SHIFT)
 336           | URB_WRITE_PRIM_END));
 337    brw_ff_gs_emit_vue(c, c->reg.vertex[1], 1);
 338 }
 339
 340 /**
 341  * Generate the geometry shader program used on Gen6 to perform stream output
 342  * (transform feedback).
 343  */
 344 void
 345 gen6_sol_program(struct brw_ff_gs_compile *c, struct brw_ff_gs_prog_key *key,
 346                  unsigned num_verts, bool check_edge_flags)
 347 {
 348    struct brw_compile *p = &c->func;
 349    c->prog_data.svbi_postincrement_value = num_verts;
 350
 351    brw_ff_gs_alloc_regs(c, num_verts, true);
 352    brw_ff_gs_initialize_header(c);
 353
 354    if (key->num_transform_feedback_bindings > 0) {
 355       unsigned vertex, binding;
 356       struct brw_reg destination_indices_uw =
 357          vec8(retype(c->reg.destination_indices, BRW_REGISTER_TYPE_UW));
 358
 359       /* Note: since we use the binding table to keep track of buffer offsets
 360        * and stride, the GS doesn't need to keep track of a separate pointer
 361        * into each buffer; it uses a single pointer which increments by 1 for
 362        * each vertex.  So we use SVBI0 for this pointer, regardless of whether
 363        * transform feedback is in interleaved or separate attribs mode.
 364        *
 365        * Make sure that the buffers have enough room for all the vertices.
 366        */
 367       brw_ADD(p, get_element_ud(c->reg.temp, 0),
 368                  get_element_ud(c->reg.SVBI, 0), brw_imm_ud(num_verts));
 369       brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_LE,
 370                  get_element_ud(c->reg.temp, 0),
 371                  get_element_ud(c->reg.SVBI, 4));
 372       brw_IF(p, BRW_EXECUTE_1);
 373
 374       /* Compute the destination indices to write to.  Usually we use SVBI[0]
 375        * + (0, 1, 2).  However, for odd-numbered triangles in tristrips, the
 376        * vertices come down the pipeline in reversed winding order, so we need
 377        * to flip the order when writing to the transform feedback buffer.  To
 378        * ensure that flatshading accuracy is preserved, we need to write them
 379        * in order SVBI[0] + (0, 2, 1) if we're using the first provoking
 380        * vertex convention, and in order SVBI[0] + (1, 0, 2) if we're using
 381        * the last provoking vertex convention.
 382        *
 383        * Note: since brw_imm_v can only be used in instructions in
 384        * packed-word execution mode, and SVBI is a double-word, we need to
 385        * first move the appropriate immediate constant ((0, 1, 2), (0, 2, 1),
 386        * or (1, 0, 2)) to the destination_indices register, and then add SVBI
 387        * using a separate instruction.  Also, since the immediate constant is
 388        * expressed as packed words, and we need to load double-words into
 389        * destination_indices, we need to intersperse zeros to fill the upper
 390        * halves of each double-word.
 391        */
 392       brw_MOV(p, destination_indices_uw,
 393               brw_imm_v(0x00020100)); /* (0, 1, 2) */
 394       if (num_verts == 3) {
 395          /* Get primitive type into temp register. */
 396          brw_AND(p, get_element_ud(c->reg.temp, 0),
 397                  get_element_ud(c->reg.R0, 2), brw_imm_ud(0x1f));
 398
 399          /* Test if primitive type is TRISTRIP_REVERSE.  We need to do this as
 400           * an 8-wide comparison so that the conditional MOV that follows
 401           * moves all 8 words correctly.
 402           */
 403          brw_CMP(p, vec8(brw_null_reg()), BRW_CONDITIONAL_EQ,
 404                  get_element_ud(c->reg.temp, 0),
 405                  brw_imm_ud(_3DPRIM_TRISTRIP_REVERSE));
 406
 407          /* If so, then overwrite destination_indices_uw with the appropriate
 408           * reordering.
 409           */
 410          brw_MOV(p, destination_indices_uw,
 411                  brw_imm_v(key->pv_first ? 0x00010200    /* (0, 2, 1) */
 412                                          : 0x00020001)); /* (1, 0, 2) */
 413          brw_set_predicate_control(p, BRW_PREDICATE_NONE);
 414       }
 415       brw_ADD(p, c->reg.destination_indices,
 416               c->reg.destination_indices, get_element_ud(c->reg.SVBI, 0));
 417
 418       /* For each vertex, generate code to output each varying using the
 419        * appropriate binding table entry.
 420        */
 421       for (vertex = 0; vertex < num_verts; ++vertex) {
 422          /* Set up the correct destination index for this vertex */
 423          brw_MOV(p, get_element_ud(c->reg.header, 5),
 424                  get_element_ud(c->reg.destination_indices, vertex));
 425
 426          for (binding = 0; binding < key->num_transform_feedback_bindings;
 427               ++binding) {
 428             unsigned char varying =
 429                key->transform_feedback_bindings[binding];
 430             unsigned char slot = c->vue_map.varying_to_slot[varying];
 431             /* From the Sandybridge PRM, Volume 2, Part 1, Section 4.5.1:
 432              *
 433              *   "Prior to End of Thread with a URB_WRITE, the kernel must
 434              *   ensure that all writes are complete by sending the final
 435              *   write as a committed write."
 436              */
 437             bool final_write =
 438                binding == key->num_transform_feedback_bindings - 1 &&
 439                vertex == num_verts - 1;
 440             struct brw_reg vertex_slot = c->reg.vertex[vertex];
 441             vertex_slot.nr += slot / 2;
 442             vertex_slot.subnr = (slot % 2) * 16;
 443             /* gl_PointSize is stored in VARYING_SLOT_PSIZ.w. */
 444             vertex_slot.dw1.bits.swizzle = varying == VARYING_SLOT_PSIZ
 445                ? BRW_SWIZZLE_WWWW : key->transform_feedback_swizzles[binding];
 446             brw_set_access_mode(p, BRW_ALIGN_16);
 447             brw_MOV(p, stride(c->reg.header, 4, 4, 1),
 448                     retype(vertex_slot, BRW_REGISTER_TYPE_UD));
 449             brw_set_access_mode(p, BRW_ALIGN_1);
 450             brw_svb_write(p,
 451                           final_write ? c->reg.temp : brw_null_reg(), /* dest */
 452                           1, /* msg_reg_nr */
 453                           c->reg.header, /* src0 */
 454                           SURF_INDEX_GEN6_SOL_BINDING(binding), /* binding_table_index */
 455                           final_write); /* send_commit_msg */
 456          }
 457       }
 458       brw_ENDIF(p);
 459
 460       /* Now, reinitialize the header register from R0 to restore the parts of
 461        * the register that we overwrote while streaming out transform feedback
 462        * data.
 463        */
 464       brw_ff_gs_initialize_header(c);
 465
 466       /* Finally, wait for the write commit to occur so that we can proceed to
 467        * other things safely.
 468        *
 469        * From the Sandybridge PRM, Volume 4, Part 1, Section 3.3:
 470        *
 471        *   The write commit does not modify the destination register, but
 472        *   merely clears the dependency associated with the destination
 473        *   register. Thus, a simple “mov” instruction using the register as a
 474        *   source is sufficient to wait for the write commit to occur.
 475        */
 476       brw_MOV(p, c->reg.temp, c->reg.temp);
 477    }
 478
 479    brw_ff_gs_ff_sync(c, 1);
 480
 481    brw_ff_gs_overwrite_header_dw2_from_r0(c);
 482    switch (num_verts) {
 483    case 1:
 484       brw_ff_gs_offset_header_dw2(c,
 485                                   URB_WRITE_PRIM_START | URB_WRITE_PRIM_END);
 486       brw_ff_gs_emit_vue(c, c->reg.vertex[0], true);
 487       break;
 488    case 2:
 489       brw_ff_gs_offset_header_dw2(c, URB_WRITE_PRIM_START);
 490       brw_ff_gs_emit_vue(c, c->reg.vertex[0], false);
 491       brw_ff_gs_offset_header_dw2(c,
 492                                   URB_WRITE_PRIM_END - URB_WRITE_PRIM_START);
 493       brw_ff_gs_emit_vue(c, c->reg.vertex[1], true);
 494       break;
 495    case 3:
 496       if (check_edge_flags) {
 497          /* Only emit vertices 0 and 1 if this is the first triangle of the
 498           * polygon.  Otherwise they are redundant.
 499           */
 500          brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ);
 501          brw_AND(p, retype(brw_null_reg(), BRW_REGISTER_TYPE_UD),
 502                  get_element_ud(c->reg.R0, 2),
 503                  brw_imm_ud(BRW_GS_EDGE_INDICATOR_0));
 504          brw_IF(p, BRW_EXECUTE_1);
 505       }
 506       brw_ff_gs_offset_header_dw2(c, URB_WRITE_PRIM_START);
 507       brw_ff_gs_emit_vue(c, c->reg.vertex[0], false);
 508       brw_ff_gs_offset_header_dw2(c, -URB_WRITE_PRIM_START);
 509       brw_ff_gs_emit_vue(c, c->reg.vertex[1], false);
 510       if (check_edge_flags) {
 511          brw_ENDIF(p);
 512          /* Only emit vertex 2 in PRIM_END mode if this is the last triangle
 513           * of the polygon.  Otherwise leave the primitive incomplete because
 514           * there are more polygon vertices coming.
 515           */
 516          brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ);
 517          brw_AND(p, retype(brw_null_reg(), BRW_REGISTER_TYPE_UD),
 518                  get_element_ud(c->reg.R0, 2),
 519                  brw_imm_ud(BRW_GS_EDGE_INDICATOR_1));
 520          brw_set_predicate_control(p, BRW_PREDICATE_NORMAL);
 521       }
 522       brw_ff_gs_offset_header_dw2(c, URB_WRITE_PRIM_END);
 523       brw_set_predicate_control(p, BRW_PREDICATE_NONE);
 524       brw_ff_gs_emit_vue(c, c->reg.vertex[2], true);
 525       break;
 526    }
 527 }