src/mesa/drivers/dri/i965/brw_gs_emit.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33 #include "main/glheader.h"
  34 #include "main/macros.h"
  35 #include "main/enums.h"
  36
  37 #include "program/program.h"
  38 #include "intel_batchbuffer.h"
  39
  40 #include "brw_defines.h"
  41 #include "brw_context.h"
  42 #include "brw_eu.h"
  43 #include "brw_gs.h"
  44
  45 /**
  46  * Allocate registers for GS.
  47  *
  48  * If sol_program is true, then:
  49  *
  50  * - The thread will be spawned with the "SVBI Payload Enable" bit set, so GRF
  51  *   1 needs to be set aside to hold the streamed vertex buffer indices.
  52  *
  53  * - The thread will need to use the destination_indices register.
  54  */
  55 static void brw_ff_gs_alloc_regs(struct brw_ff_gs_compile *c,
  56                                  GLuint nr_verts,
  57                                  bool sol_program)
  58 {
  59    GLuint i = 0,j;
  60
  61    /* Register usage is static, precompute here:
  62     */
  63    c->reg.R0 = retype(brw_vec8_grf(i, 0), BRW_REGISTER_TYPE_UD); i++;
  64
  65    /* Streamed vertex buffer indices */
  66    if (sol_program)
  67       c->reg.SVBI = retype(brw_vec8_grf(i++, 0), BRW_REGISTER_TYPE_UD);
  68
  69    /* Payload vertices plus space for more generated vertices:
  70     */
  71    for (j = 0; j < nr_verts; j++) {
  72       c->reg.vertex[j] = brw_vec4_grf(i, 0);
  73       i += c->nr_regs;
  74    }
  75
  76    c->reg.header = retype(brw_vec8_grf(i++, 0), BRW_REGISTER_TYPE_UD);
  77    c->reg.temp = retype(brw_vec8_grf(i++, 0), BRW_REGISTER_TYPE_UD);
  78
  79    if (sol_program) {
  80       c->reg.destination_indices =
  81          retype(brw_vec4_grf(i++, 0), BRW_REGISTER_TYPE_UD);
  82    }
  83
  84    c->prog_data.urb_read_length = c->nr_regs;
  85    c->prog_data.total_grf = i;
  86 }
  87
  88
  89 /**
  90  * Set up the initial value of c->reg.header register based on c->reg.R0.
  91  *
  92  * The following information is passed to the GS thread in R0, and needs to be
  93  * included in the first URB_WRITE or FF_SYNC message sent by the GS:
  94  *
  95  * - DWORD 0 [31:0] handle info (Gen4 only)
  96  * - DWORD 5 [7:0] FFTID
  97  * - DWORD 6 [31:0] Debug info
  98  * - DWORD 7 [31:0] Debug info
  99  *
 100  * This function sets up the above data by copying by copying the contents of
 101  * R0 to the header register.
 102  */
 103 static void brw_ff_gs_initialize_header(struct brw_ff_gs_compile *c)
 104 {
 105    struct brw_compile *p = &c->func;
 106    brw_MOV(p, c->reg.header, c->reg.R0);
 107 }
 108
 109 /**
 110  * Overwrite DWORD 2 of c->reg.header with the given immediate unsigned value.
 111  *
 112  * In URB_WRITE messages, DWORD 2 contains the fields PrimType, PrimStart,
 113  * PrimEnd, Increment CL_INVOCATIONS, and SONumPrimsWritten, many of which we
 114  * need to be able to update on a per-vertex basis.
 115  */
 116 static void brw_ff_gs_overwrite_header_dw2(struct brw_ff_gs_compile *c,
 117                                            unsigned dw2)
 118 {
 119    struct brw_compile *p = &c->func;
 120    brw_MOV(p, get_element_ud(c->reg.header, 2), brw_imm_ud(dw2));
 121 }
 122
 123 /**
 124  * Overwrite DWORD 2 of c->reg.header with the primitive type from c->reg.R0.
 125  *
 126  * When the thread is spawned, GRF 0 contains the primitive type in bits 4:0
 127  * of DWORD 2.  URB_WRITE messages need the primitive type in bits 6:2 of
 128  * DWORD 2.  So this function extracts the primitive type field, bitshifts it
 129  * appropriately, and stores it in c->reg.header.
 130  */
 131 static void brw_ff_gs_overwrite_header_dw2_from_r0(struct brw_ff_gs_compile *c)
 132 {
 133    struct brw_compile *p = &c->func;
 134    brw_AND(p, get_element_ud(c->reg.header, 2), get_element_ud(c->reg.R0, 2),
 135            brw_imm_ud(0x1f));
 136    brw_SHL(p, get_element_ud(c->reg.header, 2),
 137            get_element_ud(c->reg.header, 2), brw_imm_ud(2));
 138 }
 139
 140 /**
 141  * Apply an additive offset to DWORD 2 of c->reg.header.
 142  *
 143  * This is used to set/unset the "PrimStart" and "PrimEnd" flags appropriately
 144  * for each vertex.
 145  */
 146 static void brw_ff_gs_offset_header_dw2(struct brw_ff_gs_compile *c,
 147                                         int offset)
 148 {
 149    struct brw_compile *p = &c->func;
 150    brw_ADD(p, get_element_d(c->reg.header, 2), get_element_d(c->reg.header, 2),
 151            brw_imm_d(offset));
 152 }
 153
 154
 155 /**
 156  * Emit a vertex using the URB_WRITE message.  Use the contents of
 157  * c->reg.header for the message header, and the registers starting at \c vert
 158  * for the vertex data.
 159  *
 160  * If \c last is true, then this is the last vertex, so no further URB space
 161  * should be allocated, and this message should end the thread.
 162  *
 163  * If \c last is false, then a new URB entry will be allocated, and its handle
 164  * will be stored in DWORD 0 of c->reg.header for use in the next URB_WRITE
 165  * message.
 166  */
 167 static void brw_ff_gs_emit_vue(struct brw_ff_gs_compile *c,
 168                                struct brw_reg vert,
 169                                bool last)
 170 {
 171    struct brw_compile *p = &c->func;
 172    bool allocate = !last;
 173
 174    /* Copy the vertex from vertn into m1..mN+1:
 175     */
 176    brw_copy8(p, brw_message_reg(1), vert, c->nr_regs);
 177
 178    /* Send each vertex as a seperate write to the urb.  This is
 179     * different to the concept in brw_sf_emit.c, where subsequent
 180     * writes are used to build up a single urb entry.  Each of these
 181     * writes instantiates a seperate urb entry, and a new one must be
 182     * allocated each time.
 183     */
 184    brw_urb_WRITE(p,
 185                  allocate ? c->reg.temp
 186                           : retype(brw_null_reg(), BRW_REGISTER_TYPE_UD),
 187                  0,
 188                  c->reg.header,
 189                  allocate ? BRW_URB_WRITE_ALLOCATE_COMPLETE
 190                           : BRW_URB_WRITE_EOT_COMPLETE,
 191                  c->nr_regs + 1, /* msg length */
 192                  allocate ? 1 : 0, /* response length */
 193                  0,             /* urb offset */
 194                  BRW_URB_SWIZZLE_NONE);
 195
 196    if (allocate) {
 197       brw_MOV(p, get_element_ud(c->reg.header, 0),
 198               get_element_ud(c->reg.temp, 0));
 199    }
 200 }
 201
 202 /**
 203  * Send an FF_SYNC message to ensure that all previously spawned GS threads
 204  * have finished sending primitives down the pipeline, and to allocate a URB
 205  * entry for the first output vertex.  Only needed on Ironlake+.
 206  *
 207  * This function modifies c->reg.header: in DWORD 1, it stores num_prim (which
 208  * is needed by the FF_SYNC message), and in DWORD 0, it stores the handle to
 209  * the allocated URB entry (which will be needed by the URB_WRITE meesage that
 210  * follows).
 211  */
 212 static void brw_ff_gs_ff_sync(struct brw_ff_gs_compile *c, int num_prim)
 213 {
 214    struct brw_compile *p = &c->func;
 215
 216    brw_MOV(p, get_element_ud(c->reg.header, 1), brw_imm_ud(num_prim));
 217    brw_ff_sync(p,
 218                c->reg.temp,
 219                0,
 220                c->reg.header,
 221                1, /* allocate */
 222                1, /* response length */
 223                0 /* eot */);
 224    brw_MOV(p, get_element_ud(c->reg.header, 0),
 225            get_element_ud(c->reg.temp, 0));
 226 }
 227
 228
 229 void
 230 brw_ff_gs_quads(struct brw_ff_gs_compile *c, struct brw_ff_gs_prog_key *key)
 231 {
 232    struct brw_context *brw = c->func.brw;
 233
 234    brw_ff_gs_alloc_regs(c, 4, false);
 235    brw_ff_gs_initialize_header(c);
 236    /* Use polygons for correct edgeflag behaviour. Note that vertex 3
 237     * is the PV for quads, but vertex 0 for polygons:
 238     */
 239    if (brw->gen == 5)
 240       brw_ff_gs_ff_sync(c, 1);
 241    brw_ff_gs_overwrite_header_dw2(
 242       c, ((_3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT)
 243           | URB_WRITE_PRIM_START));
 244    if (key->pv_first) {
 245       brw_ff_gs_emit_vue(c, c->reg.vertex[0], 0);
 246       brw_ff_gs_overwrite_header_dw2(
 247          c, _3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT);
 248       brw_ff_gs_emit_vue(c, c->reg.vertex[1], 0);
 249       brw_ff_gs_emit_vue(c, c->reg.vertex[2], 0);
 250       brw_ff_gs_overwrite_header_dw2(
 251          c, ((_3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT)
 252              | URB_WRITE_PRIM_END));
 253       brw_ff_gs_emit_vue(c, c->reg.vertex[3], 1);
 254    }
 255    else {
 256       brw_ff_gs_emit_vue(c, c->reg.vertex[3], 0);
 257       brw_ff_gs_overwrite_header_dw2(
 258          c, _3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT);
 259       brw_ff_gs_emit_vue(c, c->reg.vertex[0], 0);
 260       brw_ff_gs_emit_vue(c, c->reg.vertex[1], 0);
 261       brw_ff_gs_overwrite_header_dw2(
 262          c, ((_3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT)
 263              | URB_WRITE_PRIM_END));
 264       brw_ff_gs_emit_vue(c, c->reg.vertex[2], 1);
 265    }
 266 }
 267
 268 void
 269 brw_ff_gs_quad_strip(struct brw_ff_gs_compile *c,
 270                      struct brw_ff_gs_prog_key *key)
 271 {
 272    struct brw_context *brw = c->func.brw;
 273
 274    brw_ff_gs_alloc_regs(c, 4, false);
 275    brw_ff_gs_initialize_header(c);
 276
 277    if (brw->gen == 5)
 278       brw_ff_gs_ff_sync(c, 1);
 279    brw_ff_gs_overwrite_header_dw2(
 280       c, ((_3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT)
 281           | URB_WRITE_PRIM_START));
 282    if (key->pv_first) {
 283       brw_ff_gs_emit_vue(c, c->reg.vertex[0], 0);
 284       brw_ff_gs_overwrite_header_dw2(
 285          c, _3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT);
 286       brw_ff_gs_emit_vue(c, c->reg.vertex[1], 0);
 287       brw_ff_gs_emit_vue(c, c->reg.vertex[2], 0);
 288       brw_ff_gs_overwrite_header_dw2(
 289          c, ((_3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT)
 290              | URB_WRITE_PRIM_END));
 291       brw_ff_gs_emit_vue(c, c->reg.vertex[3], 1);
 292    }
 293    else {
 294       brw_ff_gs_emit_vue(c, c->reg.vertex[2], 0);
 295       brw_ff_gs_overwrite_header_dw2(
 296          c, _3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT);
 297       brw_ff_gs_emit_vue(c, c->reg.vertex[3], 0);
 298       brw_ff_gs_emit_vue(c, c->reg.vertex[0], 0);
 299       brw_ff_gs_overwrite_header_dw2(
 300          c, ((_3DPRIM_POLYGON << URB_WRITE_PRIM_TYPE_SHIFT)
 301              | URB_WRITE_PRIM_END));
 302       brw_ff_gs_emit_vue(c, c->reg.vertex[1], 1);
 303    }
 304 }
 305
 306 void brw_ff_gs_lines(struct brw_ff_gs_compile *c)
 307 {
 308    struct brw_context *brw = c->func.brw;
 309
 310    brw_ff_gs_alloc_regs(c, 2, false);
 311    brw_ff_gs_initialize_header(c);
 312
 313    if (brw->gen == 5)
 314       brw_ff_gs_ff_sync(c, 1);
 315    brw_ff_gs_overwrite_header_dw2(
 316       c, ((_3DPRIM_LINESTRIP << URB_WRITE_PRIM_TYPE_SHIFT)
 317           | URB_WRITE_PRIM_START));
 318    brw_ff_gs_emit_vue(c, c->reg.vertex[0], 0);
 319    brw_ff_gs_overwrite_header_dw2(
 320       c, ((_3DPRIM_LINESTRIP << URB_WRITE_PRIM_TYPE_SHIFT)
 321           | URB_WRITE_PRIM_END));
 322    brw_ff_gs_emit_vue(c, c->reg.vertex[1], 1);
 323 }
 324
 325 /**
 326  * Generate the geometry shader program used on Gen6 to perform stream output
 327  * (transform feedback).
 328  */
 329 void
 330 gen6_sol_program(struct brw_ff_gs_compile *c, struct brw_ff_gs_prog_key *key,
 331                  unsigned num_verts, bool check_edge_flags)
 332 {
 333    struct brw_compile *p = &c->func;
 334    c->prog_data.svbi_postincrement_value = num_verts;
 335
 336    brw_ff_gs_alloc_regs(c, num_verts, true);
 337    brw_ff_gs_initialize_header(c);
 338
 339    if (key->num_transform_feedback_bindings > 0) {
 340       unsigned vertex, binding;
 341       struct brw_reg destination_indices_uw =
 342          vec8(retype(c->reg.destination_indices, BRW_REGISTER_TYPE_UW));
 343
 344       /* Note: since we use the binding table to keep track of buffer offsets
 345        * and stride, the GS doesn't need to keep track of a separate pointer
 346        * into each buffer; it uses a single pointer which increments by 1 for
 347        * each vertex.  So we use SVBI0 for this pointer, regardless of whether
 348        * transform feedback is in interleaved or separate attribs mode.
 349        *
 350        * Make sure that the buffers have enough room for all the vertices.
 351        */
 352       brw_ADD(p, get_element_ud(c->reg.temp, 0),
 353                  get_element_ud(c->reg.SVBI, 0), brw_imm_ud(num_verts));
 354       brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_LE,
 355                  get_element_ud(c->reg.temp, 0),
 356                  get_element_ud(c->reg.SVBI, 4));
 357       brw_IF(p, BRW_EXECUTE_1);
 358
 359       /* Compute the destination indices to write to.  Usually we use SVBI[0]
 360        * + (0, 1, 2).  However, for odd-numbered triangles in tristrips, the
 361        * vertices come down the pipeline in reversed winding order, so we need
 362        * to flip the order when writing to the transform feedback buffer.  To
 363        * ensure that flatshading accuracy is preserved, we need to write them
 364        * in order SVBI[0] + (0, 2, 1) if we're using the first provoking
 365        * vertex convention, and in order SVBI[0] + (1, 0, 2) if we're using
 366        * the last provoking vertex convention.
 367        *
 368        * Note: since brw_imm_v can only be used in instructions in
 369        * packed-word execution mode, and SVBI is a double-word, we need to
 370        * first move the appropriate immediate constant ((0, 1, 2), (0, 2, 1),
 371        * or (1, 0, 2)) to the destination_indices register, and then add SVBI
 372        * using a separate instruction.  Also, since the immediate constant is
 373        * expressed as packed words, and we need to load double-words into
 374        * destination_indices, we need to intersperse zeros to fill the upper
 375        * halves of each double-word.
 376        */
 377       brw_MOV(p, destination_indices_uw,
 378               brw_imm_v(0x00020100)); /* (0, 1, 2) */
 379       if (num_verts == 3) {
 380          /* Get primitive type into temp register. */
 381          brw_AND(p, get_element_ud(c->reg.temp, 0),
 382                  get_element_ud(c->reg.R0, 2), brw_imm_ud(0x1f));
 383
 384          /* Test if primitive type is TRISTRIP_REVERSE.  We need to do this as
 385           * an 8-wide comparison so that the conditional MOV that follows
 386           * moves all 8 words correctly.
 387           */
 388          brw_CMP(p, vec8(brw_null_reg()), BRW_CONDITIONAL_EQ,
 389                  get_element_ud(c->reg.temp, 0),
 390                  brw_imm_ud(_3DPRIM_TRISTRIP_REVERSE));
 391
 392          /* If so, then overwrite destination_indices_uw with the appropriate
 393           * reordering.
 394           */
 395          brw_MOV(p, destination_indices_uw,
 396                  brw_imm_v(key->pv_first ? 0x00010200    /* (0, 2, 1) */
 397                                          : 0x00020001)); /* (1, 0, 2) */
 398          brw_set_predicate_control(p, BRW_PREDICATE_NONE);
 399       }
 400       brw_ADD(p, c->reg.destination_indices,
 401               c->reg.destination_indices, get_element_ud(c->reg.SVBI, 0));
 402
 403       /* For each vertex, generate code to output each varying using the
 404        * appropriate binding table entry.
 405        */
 406       for (vertex = 0; vertex < num_verts; ++vertex) {
 407          /* Set up the correct destination index for this vertex */
 408          brw_MOV(p, get_element_ud(c->reg.header, 5),
 409                  get_element_ud(c->reg.destination_indices, vertex));
 410
 411          for (binding = 0; binding < key->num_transform_feedback_bindings;
 412               ++binding) {
 413             unsigned char varying =
 414                key->transform_feedback_bindings[binding];
 415             unsigned char slot = c->vue_map.varying_to_slot[varying];
 416             /* From the Sandybridge PRM, Volume 2, Part 1, Section 4.5.1:
 417              *
 418              *   "Prior to End of Thread with a URB_WRITE, the kernel must
 419              *   ensure that all writes are complete by sending the final
 420              *   write as a committed write."
 421              */
 422             bool final_write =
 423                binding == key->num_transform_feedback_bindings - 1 &&
 424                vertex == num_verts - 1;
 425             struct brw_reg vertex_slot = c->reg.vertex[vertex];
 426             vertex_slot.nr += slot / 2;
 427             vertex_slot.subnr = (slot % 2) * 16;
 428             /* gl_PointSize is stored in VARYING_SLOT_PSIZ.w. */
 429             vertex_slot.dw1.bits.swizzle = varying == VARYING_SLOT_PSIZ
 430                ? BRW_SWIZZLE_WWWW : key->transform_feedback_swizzles[binding];
 431             brw_set_access_mode(p, BRW_ALIGN_16);
 432             brw_MOV(p, stride(c->reg.header, 4, 4, 1),
 433                     retype(vertex_slot, BRW_REGISTER_TYPE_UD));
 434             brw_set_access_mode(p, BRW_ALIGN_1);
 435             brw_svb_write(p,
 436                           final_write ? c->reg.temp : brw_null_reg(), /* dest */
 437                           1, /* msg_reg_nr */
 438                           c->reg.header, /* src0 */
 439                           SURF_INDEX_GEN6_SOL_BINDING(binding), /* binding_table_index */
 440                           final_write); /* send_commit_msg */
 441          }
 442       }
 443       brw_ENDIF(p);
 444
 445       /* Now, reinitialize the header register from R0 to restore the parts of
 446        * the register that we overwrote while streaming out transform feedback
 447        * data.
 448        */
 449       brw_ff_gs_initialize_header(c);
 450
 451       /* Finally, wait for the write commit to occur so that we can proceed to
 452        * other things safely.
 453        *
 454        * From the Sandybridge PRM, Volume 4, Part 1, Section 3.3:
 455        *
 456        *   The write commit does not modify the destination register, but
 457        *   merely clears the dependency associated with the destination
 458        *   register. Thus, a simple “mov” instruction using the register as a
 459        *   source is sufficient to wait for the write commit to occur.
 460        */
 461       brw_MOV(p, c->reg.temp, c->reg.temp);
 462    }
 463
 464    brw_ff_gs_ff_sync(c, 1);
 465
 466    brw_ff_gs_overwrite_header_dw2_from_r0(c);
 467    switch (num_verts) {
 468    case 1:
 469       brw_ff_gs_offset_header_dw2(c,
 470                                   URB_WRITE_PRIM_START | URB_WRITE_PRIM_END);
 471       brw_ff_gs_emit_vue(c, c->reg.vertex[0], true);
 472       break;
 473    case 2:
 474       brw_ff_gs_offset_header_dw2(c, URB_WRITE_PRIM_START);
 475       brw_ff_gs_emit_vue(c, c->reg.vertex[0], false);
 476       brw_ff_gs_offset_header_dw2(c,
 477                                   URB_WRITE_PRIM_END - URB_WRITE_PRIM_START);
 478       brw_ff_gs_emit_vue(c, c->reg.vertex[1], true);
 479       break;
 480    case 3:
 481       if (check_edge_flags) {
 482          /* Only emit vertices 0 and 1 if this is the first triangle of the
 483           * polygon.  Otherwise they are redundant.
 484           */
 485          brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ);
 486          brw_AND(p, retype(brw_null_reg(), BRW_REGISTER_TYPE_UD),
 487                  get_element_ud(c->reg.R0, 2),
 488                  brw_imm_ud(BRW_GS_EDGE_INDICATOR_0));
 489          brw_IF(p, BRW_EXECUTE_1);
 490       }
 491       brw_ff_gs_offset_header_dw2(c, URB_WRITE_PRIM_START);
 492       brw_ff_gs_emit_vue(c, c->reg.vertex[0], false);
 493       brw_ff_gs_offset_header_dw2(c, -URB_WRITE_PRIM_START);
 494       brw_ff_gs_emit_vue(c, c->reg.vertex[1], false);
 495       if (check_edge_flags) {
 496          brw_ENDIF(p);
 497          /* Only emit vertex 2 in PRIM_END mode if this is the last triangle
 498           * of the polygon.  Otherwise leave the primitive incomplete because
 499           * there are more polygon vertices coming.
 500           */
 501          brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ);
 502          brw_AND(p, retype(brw_null_reg(), BRW_REGISTER_TYPE_UD),
 503                  get_element_ud(c->reg.R0, 2),
 504                  brw_imm_ud(BRW_GS_EDGE_INDICATOR_1));
 505          brw_set_predicate_control(p, BRW_PREDICATE_NORMAL);
 506       }
 507       brw_ff_gs_offset_header_dw2(c, URB_WRITE_PRIM_END);
 508       brw_set_predicate_control(p, BRW_PREDICATE_NONE);
 509       brw_ff_gs_emit_vue(c, c->reg.vertex[2], true);
 510       break;
 511    }
 512 }