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intel: s/brw_device_info/gen_device_info/
[mesa.git] / src / mesa / drivers / dri / i965 / brw_inst.h
1 /*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /**
25 * @file brw_inst.h
26 *
27 * A representation of i965 EU assembly instructions, with helper methods to
28 * get and set various fields. This is the actual hardware format.
29 */
30
31 #ifndef BRW_INST_H
32 #define BRW_INST_H
33
34 #include <stdint.h>
35
36 #include "brw_context.h"
37
38 #ifdef __cplusplus
39 extern "C" {
40 #endif
41
42 /* brw_context.h has a forward declaration of brw_inst, so name the struct. */
43 typedef struct brw_inst {
44 uint64_t data[2];
45 } brw_inst;
46
47 static inline uint64_t brw_inst_bits(const brw_inst *inst,
48 unsigned high, unsigned low);
49 static inline void brw_inst_set_bits(brw_inst *inst,
50 unsigned high, unsigned low,
51 uint64_t value);
52
53 #define FC(name, high, low, assertions) \
54 static inline void \
55 brw_inst_set_##name(const struct gen_device_info *devinfo, \
56 brw_inst *inst, uint64_t v) \
57 { \
58 assert(assertions); \
59 (void) devinfo; \
60 brw_inst_set_bits(inst, high, low, v); \
61 } \
62 static inline uint64_t \
63 brw_inst_##name(const struct gen_device_info *devinfo, \
64 const brw_inst *inst) \
65 { \
66 assert(assertions); \
67 (void) devinfo; \
68 return brw_inst_bits(inst, high, low); \
69 }
70
71 /* A simple macro for fields which stay in the same place on all generations. */
72 #define F(name, high, low) FC(name, high, low, true)
73
74 #define BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, hi7, lo7, hi8, lo8) \
75 unsigned high, low; \
76 if (devinfo->gen >= 8) { \
77 high = hi8; low = lo8; \
78 } else if (devinfo->gen >= 7) { \
79 high = hi7; low = lo7; \
80 } else if (devinfo->gen >= 6) { \
81 high = hi6; low = lo6; \
82 } else if (devinfo->gen >= 5) { \
83 high = hi5; low = lo5; \
84 } else if (devinfo->is_g4x) { \
85 high = hi45; low = lo45; \
86 } else { \
87 high = hi4; low = lo4; \
88 } \
89 assert(((int) high) != -1 && ((int) low) != -1); \
90
91 /* A general macro for cases where the field has moved to several different
92 * bit locations across generations. GCC appears to combine cases where the
93 * bits are identical, removing some of the inefficiency.
94 */
95 #define FF(name, hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, hi7, lo7, hi8, lo8)\
96 static inline void \
97 brw_inst_set_##name(const struct gen_device_info *devinfo, \
98 brw_inst *inst, uint64_t value) \
99 { \
100 BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, hi7, lo7, hi8, lo8) \
101 brw_inst_set_bits(inst, high, low, value); \
102 } \
103 static inline uint64_t \
104 brw_inst_##name(const struct gen_device_info *devinfo, const brw_inst *inst) \
105 { \
106 BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, hi7, lo7, hi8, lo8) \
107 return brw_inst_bits(inst, high, low); \
108 }
109
110 /* A macro for fields which moved as of Gen8+. */
111 #define F8(name, gen4_high, gen4_low, gen8_high, gen8_low) \
112 FF(name, \
113 /* 4: */ gen4_high, gen4_low, \
114 /* 4.5: */ gen4_high, gen4_low, \
115 /* 5: */ gen4_high, gen4_low, \
116 /* 6: */ gen4_high, gen4_low, \
117 /* 7: */ gen4_high, gen4_low, \
118 /* 8: */ gen8_high, gen8_low);
119
120 F(src1_vstride, 120, 117)
121 F(src1_width, 116, 114)
122 F(src1_da16_swiz_w, 115, 114)
123 F(src1_da16_swiz_z, 113, 112)
124 F(src1_hstride, 113, 112)
125 F(src1_address_mode, 111, 111)
126 /** Src1.SrcMod @{ */
127 F(src1_negate, 110, 110)
128 F(src1_abs, 109, 109)
129 /** @} */
130 F8(src1_ia_subreg_nr, /* 4+ */ 108, 106, /* 8+ */ 108, 105)
131 F(src1_da_reg_nr, 108, 101)
132 F(src1_da16_subreg_nr, 100, 100)
133 F(src1_da1_subreg_nr, 100, 96)
134 F(src1_da16_swiz_y, 99, 98)
135 F(src1_da16_swiz_x, 97, 96)
136 F8(src1_reg_type, /* 4+ */ 46, 44, /* 8+ */ 94, 91)
137 F8(src1_reg_file, /* 4+ */ 43, 42, /* 8+ */ 90, 89)
138 F(src0_vstride, 88, 85)
139 F(src0_width, 84, 82)
140 F(src0_da16_swiz_w, 83, 82)
141 F(src0_da16_swiz_z, 81, 80)
142 F(src0_hstride, 81, 80)
143 F(src0_address_mode, 79, 79)
144 /** Src0.SrcMod @{ */
145 F(src0_negate, 78, 78)
146 F(src0_abs, 77, 77)
147 /** @} */
148 F8(src0_ia_subreg_nr, /* 4+ */ 76, 74, /* 8+ */ 76, 73)
149 F(src0_da_reg_nr, 76, 69)
150 F(src0_da16_subreg_nr, 68, 68)
151 F(src0_da1_subreg_nr, 68, 64)
152 F(src0_da16_swiz_y, 67, 66)
153 F(src0_da16_swiz_x, 65, 64)
154 F(dst_address_mode, 63, 63)
155 F(dst_hstride, 62, 61)
156 F8(dst_ia_subreg_nr, /* 4+ */ 60, 58, /* 8+ */ 60, 57)
157 F(dst_da_reg_nr, 60, 53)
158 F(dst_da16_subreg_nr, 52, 52)
159 F(dst_da1_subreg_nr, 52, 48)
160 F(da16_writemask, 51, 48) /* Dst.ChanEn */
161 F8(src0_reg_type, /* 4+ */ 41, 39, /* 8+ */ 46, 43)
162 F8(src0_reg_file, /* 4+ */ 38, 37, /* 8+ */ 42, 41)
163 F8(dst_reg_type, /* 4+ */ 36, 34, /* 8+ */ 40, 37)
164 F8(dst_reg_file, /* 4+ */ 33, 32, /* 8+ */ 36, 35)
165 F8(mask_control, /* 4+ */ 9, 9, /* 8+ */ 34, 34)
166 FF(flag_reg_nr,
167 /* 4-6: doesn't exist */ -1, -1, -1, -1, -1, -1, -1, -1,
168 /* 7: */ 90, 90,
169 /* 8: */ 33, 33)
170 F8(flag_subreg_nr, /* 4+ */ 89, 89, /* 8+ */ 32, 32)
171 F(saturate, 31, 31)
172 F(debug_control, 30, 30)
173 F(cmpt_control, 29, 29)
174 FC(branch_control, 28, 28, devinfo->gen >= 8)
175 FC(acc_wr_control, 28, 28, devinfo->gen >= 6)
176 FC(mask_control_ex, 28, 28, devinfo->is_g4x || devinfo->gen == 5)
177 F(cond_modifier, 27, 24)
178 FC(math_function, 27, 24, devinfo->gen >= 6)
179 F(exec_size, 23, 21)
180 F(pred_inv, 20, 20)
181 F(pred_control, 19, 16)
182 F(thread_control, 15, 14)
183 F(qtr_control, 13, 12)
184 FF(nib_control,
185 /* 4-6: doesn't exist */ -1, -1, -1, -1, -1, -1, -1, -1,
186 /* 7: */ 47, 47,
187 /* 8: */ 11, 11)
188 F8(no_dd_check, /* 4+ */ 11, 11, /* 8+ */ 10, 10)
189 F8(no_dd_clear, /* 4+ */ 10, 10, /* 8+ */ 9, 9)
190 F(access_mode, 8, 8)
191 /* Bit 7 is Reserved (for future Opcode expansion) */
192 F(opcode, 6, 0)
193
194 /**
195 * Three-source instructions:
196 * @{
197 */
198 F(3src_src2_reg_nr, 125, 118)
199 F(3src_src2_subreg_nr, 117, 115) /* Extra discontiguous bit on CHV? */
200 F(3src_src2_swizzle, 114, 107)
201 F(3src_src2_rep_ctrl, 106, 106)
202 F(3src_src1_reg_nr, 104, 97)
203 F(3src_src1_subreg_nr, 96, 94) /* Extra discontiguous bit on CHV? */
204 F(3src_src1_swizzle, 93, 86)
205 F(3src_src1_rep_ctrl, 85, 85)
206 F(3src_src0_reg_nr, 83, 76)
207 F(3src_src0_subreg_nr, 75, 73) /* Extra discontiguous bit on CHV? */
208 F(3src_src0_swizzle, 72, 65)
209 F(3src_src0_rep_ctrl, 64, 64)
210 F(3src_dst_reg_nr, 63, 56)
211 F(3src_dst_subreg_nr, 55, 53)
212 F(3src_dst_writemask, 52, 49)
213 F8(3src_nib_ctrl, 47, 47, 11, 11) /* only exists on IVB+ */
214 F8(3src_dst_type, 45, 44, 48, 46) /* only exists on IVB+ */
215 F8(3src_src_type, 43, 42, 45, 43)
216 F8(3src_src2_negate, 41, 41, 42, 42)
217 F8(3src_src2_abs, 40, 40, 41, 41)
218 F8(3src_src1_negate, 39, 39, 40, 40)
219 F8(3src_src1_abs, 38, 38, 39, 39)
220 F8(3src_src0_negate, 37, 37, 38, 38)
221 F8(3src_src0_abs, 36, 36, 37, 37)
222 F8(3src_flag_reg_nr, 34, 34, 33, 33)
223 F8(3src_flag_subreg_nr, 33, 33, 32, 32)
224 FF(3src_dst_reg_file,
225 /* 4-5: doesn't exist - no 3-source instructions */ -1, -1, -1, -1, -1, -1,
226 /* 6: */ 32, 32,
227 /* 7-8: doesn't exist - no MRFs */ -1, -1, -1, -1)
228 F(3src_saturate, 31, 31)
229 F(3src_debug_control, 30, 30)
230 F(3src_cmpt_control, 29, 29)
231 F(3src_acc_wr_control, 28, 28)
232 F(3src_cond_modifier, 27, 24)
233 F(3src_exec_size, 23, 21)
234 F(3src_pred_inv, 20, 20)
235 F(3src_pred_control, 19, 16)
236 F(3src_thread_control, 15, 14)
237 F(3src_qtr_control, 13, 12)
238 F8(3src_no_dd_check, 11, 11, 10, 10)
239 F8(3src_no_dd_clear, 10, 10, 9, 9)
240 F8(3src_mask_control, 9, 9, 34, 34)
241 F(3src_access_mode, 8, 8)
242 /* Bit 7 is Reserved (for future Opcode expansion) */
243 F(3src_opcode, 6, 0)
244 /** @} */
245
246 /**
247 * Flow control instruction bits:
248 * @{
249 */
250 static inline void
251 brw_inst_set_uip(const struct gen_device_info *devinfo,
252 brw_inst *inst, int32_t value)
253 {
254 assert(devinfo->gen >= 6);
255
256 if (devinfo->gen >= 8) {
257 brw_inst_set_bits(inst, 95, 64, (uint32_t)value);
258 } else {
259 assert(value <= (1 << 16) - 1);
260 assert(value > -(1 << 16));
261 brw_inst_set_bits(inst, 127, 112, (uint16_t)value);
262 }
263 }
264
265 static inline int32_t
266 brw_inst_uip(const struct gen_device_info *devinfo, const brw_inst *inst)
267 {
268 assert(devinfo->gen >= 6);
269
270 if (devinfo->gen >= 8) {
271 return brw_inst_bits(inst, 95, 64);
272 } else {
273 return (int16_t)brw_inst_bits(inst, 127, 112);
274 }
275 }
276
277 static inline void
278 brw_inst_set_jip(const struct gen_device_info *devinfo,
279 brw_inst *inst, int32_t value)
280 {
281 assert(devinfo->gen >= 6);
282
283 if (devinfo->gen >= 8) {
284 brw_inst_set_bits(inst, 127, 96, (uint32_t)value);
285 } else {
286 assert(value <= (1 << 16) - 1);
287 assert(value > -(1 << 16));
288 brw_inst_set_bits(inst, 111, 96, (uint16_t)value);
289 }
290 }
291
292 static inline int32_t
293 brw_inst_jip(const struct gen_device_info *devinfo, const brw_inst *inst)
294 {
295 assert(devinfo->gen >= 6);
296
297 if (devinfo->gen >= 8) {
298 return brw_inst_bits(inst, 127, 96);
299 } else {
300 return (int16_t)brw_inst_bits(inst, 111, 96);
301 }
302 }
303
304 /** Like FC, but using int16_t to handle negative jump targets. */
305 #define FJ(name, high, low, assertions) \
306 static inline void \
307 brw_inst_set_##name(const struct gen_device_info *devinfo, brw_inst *inst, int16_t v) \
308 { \
309 assert(assertions); \
310 (void) devinfo; \
311 brw_inst_set_bits(inst, high, low, (uint16_t) v); \
312 } \
313 static inline int16_t \
314 brw_inst_##name(const struct gen_device_info *devinfo, const brw_inst *inst) \
315 { \
316 assert(assertions); \
317 (void) devinfo; \
318 return brw_inst_bits(inst, high, low); \
319 }
320
321 FJ(gen6_jump_count, 63, 48, devinfo->gen == 6)
322 FJ(gen4_jump_count, 111, 96, devinfo->gen < 6)
323 FC(gen4_pop_count, 115, 112, devinfo->gen < 6)
324 /** @} */
325
326 /* Message descriptor bits */
327 #define MD(x) ((x) + 96)
328
329 /**
330 * Fields for SEND messages:
331 * @{
332 */
333 F(eot, 127, 127)
334 FF(mlen,
335 /* 4: */ 119, 116,
336 /* 4.5: */ 119, 116,
337 /* 5: */ 124, 121,
338 /* 6: */ 124, 121,
339 /* 7: */ 124, 121,
340 /* 8: */ 124, 121);
341 FF(rlen,
342 /* 4: */ 115, 112,
343 /* 4.5: */ 115, 112,
344 /* 5: */ 120, 116,
345 /* 6: */ 120, 116,
346 /* 7: */ 120, 116,
347 /* 8: */ 120, 116);
348 FF(header_present,
349 /* 4: doesn't exist */ -1, -1, -1, -1,
350 /* 5: */ 115, 115,
351 /* 6: */ 115, 115,
352 /* 7: */ 115, 115,
353 /* 8: */ 115, 115)
354 F(gateway_notify, MD(16), MD(15))
355 FF(function_control,
356 /* 4: */ 111, 96,
357 /* 4.5: */ 111, 96,
358 /* 5: */ 114, 96,
359 /* 6: */ 114, 96,
360 /* 7: */ 114, 96,
361 /* 8: */ 114, 96)
362 FF(gateway_subfuncid,
363 /* 4: */ MD(1), MD(0),
364 /* 4.5: */ MD(1), MD(0),
365 /* 5: */ MD(1), MD(0), /* 2:0, but bit 2 is reserved MBZ */
366 /* 6: */ MD(2), MD(0),
367 /* 7: */ MD(2), MD(0),
368 /* 8: */ MD(2), MD(0))
369 FF(sfid,
370 /* 4: */ 123, 120, /* called msg_target */
371 /* 4.5 */ 123, 120,
372 /* 5: */ 95, 92,
373 /* 6: */ 27, 24,
374 /* 7: */ 27, 24,
375 /* 8: */ 27, 24)
376 FC(base_mrf, 27, 24, devinfo->gen < 6);
377 /** @} */
378
379 /**
380 * URB message function control bits:
381 * @{
382 */
383 FF(urb_per_slot_offset,
384 /* 4-6: */ -1, -1, -1, -1, -1, -1, -1, -1,
385 /* 7: */ MD(16), MD(16),
386 /* 8: */ MD(17), MD(17))
387 FC(urb_channel_mask_present, MD(15), MD(15), devinfo->gen >= 8)
388 FC(urb_complete, MD(15), MD(15), devinfo->gen < 8)
389 FC(urb_used, MD(14), MD(14), devinfo->gen < 7)
390 FC(urb_allocate, MD(13), MD(13), devinfo->gen < 7)
391 FF(urb_swizzle_control,
392 /* 4: */ MD(11), MD(10),
393 /* 4.5: */ MD(11), MD(10),
394 /* 5: */ MD(11), MD(10),
395 /* 6: */ MD(11), MD(10),
396 /* 7: */ MD(14), MD(14),
397 /* 8: */ MD(15), MD(15))
398 FF(urb_global_offset,
399 /* 4: */ MD( 9), MD(4),
400 /* 4.5: */ MD( 9), MD(4),
401 /* 5: */ MD( 9), MD(4),
402 /* 6: */ MD( 9), MD(4),
403 /* 7: */ MD(13), MD(3),
404 /* 8: */ MD(14), MD(4))
405 FF(urb_opcode,
406 /* 4: */ MD( 3), MD(0),
407 /* 4.5: */ MD( 3), MD(0),
408 /* 5: */ MD( 3), MD(0),
409 /* 6: */ MD( 3), MD(0),
410 /* 7: */ MD( 2), MD(0),
411 /* 8: */ MD( 3), MD(0))
412 /** @} */
413
414 /**
415 * Gen4-5 math messages:
416 * @{
417 */
418 FC(math_msg_data_type, MD(7), MD(7), devinfo->gen < 6)
419 FC(math_msg_saturate, MD(6), MD(6), devinfo->gen < 6)
420 FC(math_msg_precision, MD(5), MD(5), devinfo->gen < 6)
421 FC(math_msg_signed_int, MD(4), MD(4), devinfo->gen < 6)
422 FC(math_msg_function, MD(3), MD(0), devinfo->gen < 6)
423 /** @} */
424
425 /**
426 * Sampler message function control bits:
427 * @{
428 */
429 FF(sampler_simd_mode,
430 /* 4: doesn't exist */ -1, -1, -1, -1,
431 /* 5: */ MD(17), MD(16),
432 /* 6: */ MD(17), MD(16),
433 /* 7: */ MD(18), MD(17),
434 /* 8: */ MD(18), MD(17))
435 FF(sampler_msg_type,
436 /* 4: */ MD(15), MD(14),
437 /* 4.5: */ MD(15), MD(12),
438 /* 5: */ MD(15), MD(12),
439 /* 6: */ MD(15), MD(12),
440 /* 7: */ MD(16), MD(12),
441 /* 8: */ MD(16), MD(12))
442 FC(sampler_return_format, MD(13), MD(12), devinfo->gen == 4 && !devinfo->is_g4x)
443 F(sampler, MD(11), MD(8))
444 F(binding_table_index, MD( 7), MD(0)) /* also used by other messages */
445 /** @} */
446
447 /**
448 * Data port message function control bits:
449 * @{
450 */
451 FC(dp_category, MD(18), MD(18), devinfo->gen >= 7)
452
453 /* Gen4-5 store fields in different bits for read/write messages. */
454 FF(dp_read_msg_type,
455 /* 4: */ MD(13), MD(12),
456 /* 4.5: */ MD(13), MD(11),
457 /* 5: */ MD(13), MD(11),
458 /* 6: */ MD(16), MD(13),
459 /* 7: */ MD(17), MD(14),
460 /* 8: */ MD(17), MD(14))
461 FF(dp_write_msg_type,
462 /* 4: */ MD(14), MD(12),
463 /* 4.5: */ MD(14), MD(12),
464 /* 5: */ MD(14), MD(12),
465 /* 6: */ MD(16), MD(13),
466 /* 7: */ MD(17), MD(14),
467 /* 8: */ MD(17), MD(14))
468 FF(dp_read_msg_control,
469 /* 4: */ MD(11), MD( 8),
470 /* 4.5: */ MD(10), MD( 8),
471 /* 5: */ MD(10), MD( 8),
472 /* 6: */ MD(12), MD( 8),
473 /* 7: */ MD(13), MD( 8),
474 /* 8: */ MD(13), MD( 8))
475 FF(dp_write_msg_control,
476 /* 4: */ MD(11), MD( 8),
477 /* 4.5: */ MD(11), MD( 8),
478 /* 5: */ MD(11), MD( 8),
479 /* 6: */ MD(12), MD( 8),
480 /* 7: */ MD(13), MD( 8),
481 /* 8: */ MD(13), MD( 8))
482 FC(dp_read_target_cache, MD(15), MD(14), devinfo->gen < 6);
483
484 FF(dp_write_commit,
485 /* 4: */ MD(15), MD(15),
486 /* 4.5: */ MD(15), MD(15),
487 /* 5: */ MD(15), MD(15),
488 /* 6: */ MD(17), MD(17),
489 /* 7+: does not exist */ -1, -1, -1, -1)
490
491 /* Gen6+ use the same bit locations for everything. */
492 FF(dp_msg_type,
493 /* 4-5: use dp_read_msg_type or dp_write_msg_type instead */
494 -1, -1, -1, -1, -1, -1,
495 /* 6: */ MD(16), MD(13),
496 /* 7: */ MD(17), MD(14),
497 /* 8: */ MD(17), MD(14))
498 FF(dp_msg_control,
499 /* 4: */ MD(11), MD( 8),
500 /* 4.5-5: use dp_read_msg_control or dp_write_msg_control */ -1, -1, -1, -1,
501 /* 6: */ MD(12), MD( 8),
502 /* 7: */ MD(13), MD( 8),
503 /* 8: */ MD(13), MD( 8))
504 /** @} */
505
506 /**
507 * Scratch message bits (Gen7+):
508 * @{
509 */
510 FC(scratch_read_write, MD(17), MD(17), devinfo->gen >= 7) /* 0 = read, 1 = write */
511 FC(scratch_type, MD(16), MD(16), devinfo->gen >= 7) /* 0 = OWord, 1 = DWord */
512 FC(scratch_invalidate_after_read, MD(15), MD(15), devinfo->gen >= 7)
513 FC(scratch_block_size, MD(13), MD(12), devinfo->gen >= 7)
514 FC(scratch_addr_offset, MD(11), MD( 0), devinfo->gen >= 7)
515 /** @} */
516
517 /**
518 * Render Target message function control bits:
519 * @{
520 */
521 FF(rt_last,
522 /* 4: */ MD(11), MD(11),
523 /* 4.5: */ MD(11), MD(11),
524 /* 5: */ MD(11), MD(11),
525 /* 6: */ MD(12), MD(12),
526 /* 7: */ MD(12), MD(12),
527 /* 8: */ MD(12), MD(12))
528 FC(rt_slot_group, MD(11), MD(11), devinfo->gen >= 6)
529 F(rt_message_type, MD(10), MD( 8))
530 /** @} */
531
532 /**
533 * Thread Spawn message function control bits:
534 * @{
535 */
536 F(ts_resource_select, MD( 4), MD( 4))
537 F(ts_request_type, MD( 1), MD( 1))
538 F(ts_opcode, MD( 0), MD( 0))
539 /** @} */
540
541 /**
542 * Pixel Interpolator message function control bits:
543 * @{
544 */
545 F(pi_simd_mode, MD(16), MD(16))
546 F(pi_nopersp, MD(14), MD(14))
547 F(pi_message_type, MD(13), MD(12))
548 F(pi_slot_group, MD(11), MD(11))
549 F(pi_message_data, MD(7), MD(0))
550 /** @} */
551
552 /**
553 * Immediates:
554 * @{
555 */
556 static inline int
557 brw_inst_imm_d(const struct gen_device_info *devinfo, const brw_inst *insn)
558 {
559 (void) devinfo;
560 return brw_inst_bits(insn, 127, 96);
561 }
562
563 static inline unsigned
564 brw_inst_imm_ud(const struct gen_device_info *devinfo, const brw_inst *insn)
565 {
566 (void) devinfo;
567 return brw_inst_bits(insn, 127, 96);
568 }
569
570 static inline float
571 brw_inst_imm_f(const struct gen_device_info *devinfo, const brw_inst *insn)
572 {
573 fi_type ft;
574 (void) devinfo;
575 ft.u = brw_inst_bits(insn, 127, 96);
576 return ft.f;
577 }
578
579 static inline double
580 brw_inst_imm_df(const struct gen_device_info *devinfo, const brw_inst *insn)
581 {
582 union {
583 double d;
584 uint64_t u;
585 } dt;
586 (void) devinfo;
587 dt.u = brw_inst_bits(insn, 127, 64);
588 return dt.d;
589 }
590
591 static inline void
592 brw_inst_set_imm_d(const struct gen_device_info *devinfo,
593 brw_inst *insn, int value)
594 {
595 (void) devinfo;
596 return brw_inst_set_bits(insn, 127, 96, value);
597 }
598
599 static inline void
600 brw_inst_set_imm_ud(const struct gen_device_info *devinfo,
601 brw_inst *insn, unsigned value)
602 {
603 (void) devinfo;
604 return brw_inst_set_bits(insn, 127, 96, value);
605 }
606
607 static inline void
608 brw_inst_set_imm_f(const struct gen_device_info *devinfo,
609 brw_inst *insn, float value)
610 {
611 fi_type ft;
612 (void) devinfo;
613 ft.f = value;
614 brw_inst_set_bits(insn, 127, 96, ft.u);
615 }
616
617 static inline void
618 brw_inst_set_imm_df(const struct gen_device_info *devinfo,
619 brw_inst *insn, double value)
620 {
621 union {
622 double d;
623 uint64_t u;
624 } dt;
625 (void) devinfo;
626 dt.d = value;
627 brw_inst_set_bits(insn, 127, 64, dt.u);
628 }
629
630 /** @} */
631
632 /* The AddrImm fields are split into two discontiguous sections on Gen8+ */
633 #define BRW_IA1_ADDR_IMM(reg, g4_high, g4_low, g8_nine, g8_high, g8_low) \
634 static inline void \
635 brw_inst_set_##reg##_ia1_addr_imm(const struct gen_device_info *devinfo, \
636 brw_inst *inst, \
637 unsigned value) \
638 { \
639 assert((value & ~0x3ff) == 0); \
640 if (devinfo->gen >= 8) { \
641 brw_inst_set_bits(inst, g8_high, g8_low, value & 0x1ff); \
642 brw_inst_set_bits(inst, g8_nine, g8_nine, value >> 9); \
643 } else { \
644 brw_inst_set_bits(inst, g4_high, g4_low, value); \
645 } \
646 } \
647 static inline unsigned \
648 brw_inst_##reg##_ia1_addr_imm(const struct gen_device_info *devinfo, \
649 const brw_inst *inst) \
650 { \
651 if (devinfo->gen >= 8) { \
652 return brw_inst_bits(inst, g8_high, g8_low) | \
653 (brw_inst_bits(inst, g8_nine, g8_nine) << 9); \
654 } else { \
655 return brw_inst_bits(inst, g4_high, g4_low); \
656 } \
657 }
658
659 /* AddrImm[9:0] for Align1 Indirect Addressing */
660 /* -Gen 4- ----Gen8---- */
661 BRW_IA1_ADDR_IMM(src1, 105, 96, 121, 104, 96)
662 BRW_IA1_ADDR_IMM(src0, 73, 64, 95, 72, 64)
663 BRW_IA1_ADDR_IMM(dst, 57, 48, 47, 56, 48)
664
665 #define BRW_IA16_ADDR_IMM(reg, g4_high, g4_low, g8_nine, g8_high, g8_low) \
666 static inline void \
667 brw_inst_set_##reg##_ia16_addr_imm(const struct gen_device_info *devinfo, \
668 brw_inst *inst, unsigned value) \
669 { \
670 assert((value & ~0x3ff) == 0); \
671 if (devinfo->gen >= 8) { \
672 brw_inst_set_bits(inst, g8_high, g8_low, value & 0x1ff); \
673 brw_inst_set_bits(inst, g8_nine, g8_nine, value >> 9); \
674 } else { \
675 brw_inst_set_bits(inst, g4_high, g4_low, value >> 9); \
676 } \
677 } \
678 static inline unsigned \
679 brw_inst_##reg##_ia16_addr_imm(const struct gen_device_info *devinfo, \
680 const brw_inst *inst) \
681 { \
682 if (devinfo->gen >= 8) { \
683 return brw_inst_bits(inst, g8_high, g8_low) | \
684 (brw_inst_bits(inst, g8_nine, g8_nine) << 9); \
685 } else { \
686 return brw_inst_bits(inst, g4_high, g4_low); \
687 } \
688 }
689
690 /* AddrImm[9:0] for Align16 Indirect Addressing:
691 * Compared to Align1, these are missing the low 4 bits.
692 * -Gen 4- ----Gen8----
693 */
694 BRW_IA16_ADDR_IMM(src1, 105, 96, 121, 104, 100)
695 BRW_IA16_ADDR_IMM(src0, 73, 64, 95, 72, 68)
696 BRW_IA16_ADDR_IMM(dst, 57, 52, 47, 56, 52)
697
698 /**
699 * Fetch a set of contiguous bits from the instruction.
700 *
701 * Bits indices range from 0..127; fields may not cross 64-bit boundaries.
702 */
703 static inline uint64_t
704 brw_inst_bits(const brw_inst *inst, unsigned high, unsigned low)
705 {
706 /* We assume the field doesn't cross 64-bit boundaries. */
707 const unsigned word = high / 64;
708 assert(word == low / 64);
709
710 high %= 64;
711 low %= 64;
712
713 const uint64_t mask = (~0ull >> (64 - (high - low + 1)));
714
715 return (inst->data[word] >> low) & mask;
716 }
717
718 /**
719 * Set bits in the instruction, with proper shifting and masking.
720 *
721 * Bits indices range from 0..127; fields may not cross 64-bit boundaries.
722 */
723 static inline void
724 brw_inst_set_bits(brw_inst *inst, unsigned high, unsigned low, uint64_t value)
725 {
726 const unsigned word = high / 64;
727 assert(word == low / 64);
728
729 high %= 64;
730 low %= 64;
731
732 const uint64_t mask = (~0ull >> (64 - (high - low + 1))) << low;
733
734 /* Make sure the supplied value actually fits in the given bitfield. */
735 assert((value & (mask >> low)) == value);
736
737 inst->data[word] = (inst->data[word] & ~mask) | (value << low);
738 }
739
740 #undef BRW_IA16_ADDR_IMM
741 #undef BRW_IA1_ADDR_IMM
742 #undef MD
743 #undef F8
744 #undef FF
745 #undef BOUNDS
746 #undef F
747 #undef FC
748
749 typedef struct {
750 uint64_t data;
751 } brw_compact_inst;
752
753 /**
754 * Fetch a set of contiguous bits from the compacted instruction.
755 *
756 * Bits indices range from 0..63.
757 */
758 static inline unsigned
759 brw_compact_inst_bits(const brw_compact_inst *inst, unsigned high, unsigned low)
760 {
761 const uint64_t mask = (1ull << (high - low + 1)) - 1;
762
763 return (inst->data >> low) & mask;
764 }
765
766 /**
767 * Set bits in the compacted instruction.
768 *
769 * Bits indices range from 0..63.
770 */
771 static inline void
772 brw_compact_inst_set_bits(brw_compact_inst *inst, unsigned high, unsigned low,
773 uint64_t value)
774 {
775 const uint64_t mask = ((1ull << (high - low + 1)) - 1) << low;
776
777 /* Make sure the supplied value actually fits in the given bitfield. */
778 assert((value & (mask >> low)) == value);
779
780 inst->data = (inst->data & ~mask) | (value << low);
781 }
782
783 #define FC(name, high, low, assertions) \
784 static inline void \
785 brw_compact_inst_set_##name(const struct gen_device_info *devinfo, \
786 brw_compact_inst *inst, unsigned v) \
787 { \
788 assert(assertions); \
789 (void) devinfo; \
790 brw_compact_inst_set_bits(inst, high, low, v); \
791 } \
792 static inline unsigned \
793 brw_compact_inst_##name(const struct gen_device_info *devinfo, \
794 const brw_compact_inst *inst) \
795 { \
796 assert(assertions); \
797 (void) devinfo; \
798 return brw_compact_inst_bits(inst, high, low); \
799 }
800
801 /* A simple macro for fields which stay in the same place on all generations. */
802 #define F(name, high, low) FC(name, high, low, true)
803
804 F(src1_reg_nr, 63, 56)
805 F(src0_reg_nr, 55, 48)
806 F(dst_reg_nr, 47, 40)
807 F(src1_index, 39, 35)
808 F(src0_index, 34, 30)
809 F(cmpt_control, 29, 29) /* Same location as brw_inst */
810 FC(flag_subreg_nr, 28, 28, devinfo->gen <= 6)
811 F(cond_modifier, 27, 24) /* Same location as brw_inst */
812 FC(acc_wr_control, 23, 23, devinfo->gen >= 6)
813 FC(mask_control_ex, 23, 23, devinfo->is_g4x || devinfo->gen == 5)
814 F(subreg_index, 22, 18)
815 F(datatype_index, 17, 13)
816 F(control_index, 12, 8)
817 F(debug_control, 7, 7)
818 F(opcode, 6, 0) /* Same location as brw_inst */
819
820 /**
821 * (Gen8+) Compacted three-source instructions:
822 * @{
823 */
824 FC(3src_src2_reg_nr, 63, 57, devinfo->gen >= 8)
825 FC(3src_src1_reg_nr, 56, 50, devinfo->gen >= 8)
826 FC(3src_src0_reg_nr, 49, 43, devinfo->gen >= 8)
827 FC(3src_src2_subreg_nr, 42, 40, devinfo->gen >= 8)
828 FC(3src_src1_subreg_nr, 39, 37, devinfo->gen >= 8)
829 FC(3src_src0_subreg_nr, 36, 34, devinfo->gen >= 8)
830 FC(3src_src2_rep_ctrl, 33, 33, devinfo->gen >= 8)
831 FC(3src_src1_rep_ctrl, 32, 32, devinfo->gen >= 8)
832 FC(3src_saturate, 31, 31, devinfo->gen >= 8)
833 FC(3src_debug_control, 30, 30, devinfo->gen >= 8)
834 FC(3src_cmpt_control, 29, 29, devinfo->gen >= 8)
835 FC(3src_src0_rep_ctrl, 28, 28, devinfo->gen >= 8)
836 /* Reserved */
837 FC(3src_dst_reg_nr, 18, 12, devinfo->gen >= 8)
838 FC(3src_source_index, 11, 10, devinfo->gen >= 8)
839 FC(3src_control_index, 9, 8, devinfo->gen >= 8)
840 /* Bit 7 is Reserved (for future Opcode expansion) */
841 FC(3src_opcode, 6, 0, devinfo->gen >= 8)
842 /** @} */
843
844 #undef F
845
846 #ifdef __cplusplus
847 }
848 #endif
849
850 #endif