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i965: Reduce cross-pollination between the DRI driver and compiler
[mesa.git] / src / mesa / drivers / dri / i965 / brw_inst.h
1 /*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /**
25 * @file brw_inst.h
26 *
27 * A representation of i965 EU assembly instructions, with helper methods to
28 * get and set various fields. This is the actual hardware format.
29 */
30
31 #ifndef BRW_INST_H
32 #define BRW_INST_H
33
34 #include <stdint.h>
35
36 #include "brw_defines.h"
37 #include "common/gen_device_info.h"
38
39 #ifdef __cplusplus
40 extern "C" {
41 #endif
42
43 /* brw_context.h has a forward declaration of brw_inst, so name the struct. */
44 typedef struct brw_inst {
45 uint64_t data[2];
46 } brw_inst;
47
48 static inline uint64_t brw_inst_bits(const brw_inst *inst,
49 unsigned high, unsigned low);
50 static inline void brw_inst_set_bits(brw_inst *inst,
51 unsigned high, unsigned low,
52 uint64_t value);
53
54 #define FC(name, high, low, assertions) \
55 static inline void \
56 brw_inst_set_##name(const struct gen_device_info *devinfo, \
57 brw_inst *inst, uint64_t v) \
58 { \
59 assert(assertions); \
60 (void) devinfo; \
61 brw_inst_set_bits(inst, high, low, v); \
62 } \
63 static inline uint64_t \
64 brw_inst_##name(const struct gen_device_info *devinfo, \
65 const brw_inst *inst) \
66 { \
67 assert(assertions); \
68 (void) devinfo; \
69 return brw_inst_bits(inst, high, low); \
70 }
71
72 /* A simple macro for fields which stay in the same place on all generations. */
73 #define F(name, high, low) FC(name, high, low, true)
74
75 #define BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, hi7, lo7, hi8, lo8) \
76 unsigned high, low; \
77 if (devinfo->gen >= 8) { \
78 high = hi8; low = lo8; \
79 } else if (devinfo->gen >= 7) { \
80 high = hi7; low = lo7; \
81 } else if (devinfo->gen >= 6) { \
82 high = hi6; low = lo6; \
83 } else if (devinfo->gen >= 5) { \
84 high = hi5; low = lo5; \
85 } else if (devinfo->is_g4x) { \
86 high = hi45; low = lo45; \
87 } else { \
88 high = hi4; low = lo4; \
89 } \
90 assert(((int) high) != -1 && ((int) low) != -1); \
91
92 /* A general macro for cases where the field has moved to several different
93 * bit locations across generations. GCC appears to combine cases where the
94 * bits are identical, removing some of the inefficiency.
95 */
96 #define FF(name, hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, hi7, lo7, hi8, lo8)\
97 static inline void \
98 brw_inst_set_##name(const struct gen_device_info *devinfo, \
99 brw_inst *inst, uint64_t value) \
100 { \
101 BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, hi7, lo7, hi8, lo8) \
102 brw_inst_set_bits(inst, high, low, value); \
103 } \
104 static inline uint64_t \
105 brw_inst_##name(const struct gen_device_info *devinfo, const brw_inst *inst) \
106 { \
107 BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, hi7, lo7, hi8, lo8) \
108 return brw_inst_bits(inst, high, low); \
109 }
110
111 /* A macro for fields which moved as of Gen8+. */
112 #define F8(name, gen4_high, gen4_low, gen8_high, gen8_low) \
113 FF(name, \
114 /* 4: */ gen4_high, gen4_low, \
115 /* 4.5: */ gen4_high, gen4_low, \
116 /* 5: */ gen4_high, gen4_low, \
117 /* 6: */ gen4_high, gen4_low, \
118 /* 7: */ gen4_high, gen4_low, \
119 /* 8: */ gen8_high, gen8_low);
120
121 F(src1_vstride, 120, 117)
122 F(src1_width, 116, 114)
123 F(src1_da16_swiz_w, 115, 114)
124 F(src1_da16_swiz_z, 113, 112)
125 F(src1_hstride, 113, 112)
126 F(src1_address_mode, 111, 111)
127 /** Src1.SrcMod @{ */
128 F(src1_negate, 110, 110)
129 F(src1_abs, 109, 109)
130 /** @} */
131 F8(src1_ia_subreg_nr, /* 4+ */ 108, 106, /* 8+ */ 108, 105)
132 F(src1_da_reg_nr, 108, 101)
133 F(src1_da16_subreg_nr, 100, 100)
134 F(src1_da1_subreg_nr, 100, 96)
135 F(src1_da16_swiz_y, 99, 98)
136 F(src1_da16_swiz_x, 97, 96)
137 F8(src1_reg_type, /* 4+ */ 46, 44, /* 8+ */ 94, 91)
138 F8(src1_reg_file, /* 4+ */ 43, 42, /* 8+ */ 90, 89)
139 F(src0_vstride, 88, 85)
140 F(src0_width, 84, 82)
141 F(src0_da16_swiz_w, 83, 82)
142 F(src0_da16_swiz_z, 81, 80)
143 F(src0_hstride, 81, 80)
144 F(src0_address_mode, 79, 79)
145 /** Src0.SrcMod @{ */
146 F(src0_negate, 78, 78)
147 F(src0_abs, 77, 77)
148 /** @} */
149 F8(src0_ia_subreg_nr, /* 4+ */ 76, 74, /* 8+ */ 76, 73)
150 F(src0_da_reg_nr, 76, 69)
151 F(src0_da16_subreg_nr, 68, 68)
152 F(src0_da1_subreg_nr, 68, 64)
153 F(src0_da16_swiz_y, 67, 66)
154 F(src0_da16_swiz_x, 65, 64)
155 F(dst_address_mode, 63, 63)
156 F(dst_hstride, 62, 61)
157 F8(dst_ia_subreg_nr, /* 4+ */ 60, 58, /* 8+ */ 60, 57)
158 F(dst_da_reg_nr, 60, 53)
159 F(dst_da16_subreg_nr, 52, 52)
160 F(dst_da1_subreg_nr, 52, 48)
161 F(da16_writemask, 51, 48) /* Dst.ChanEn */
162 F8(src0_reg_type, /* 4+ */ 41, 39, /* 8+ */ 46, 43)
163 F8(src0_reg_file, /* 4+ */ 38, 37, /* 8+ */ 42, 41)
164 F8(dst_reg_type, /* 4+ */ 36, 34, /* 8+ */ 40, 37)
165 F8(dst_reg_file, /* 4+ */ 33, 32, /* 8+ */ 36, 35)
166 F8(mask_control, /* 4+ */ 9, 9, /* 8+ */ 34, 34)
167 FF(flag_reg_nr,
168 /* 4-6: doesn't exist */ -1, -1, -1, -1, -1, -1, -1, -1,
169 /* 7: */ 90, 90,
170 /* 8: */ 33, 33)
171 F8(flag_subreg_nr, /* 4+ */ 89, 89, /* 8+ */ 32, 32)
172 F(saturate, 31, 31)
173 F(debug_control, 30, 30)
174 F(cmpt_control, 29, 29)
175 FC(branch_control, 28, 28, devinfo->gen >= 8)
176 FC(acc_wr_control, 28, 28, devinfo->gen >= 6)
177 FC(mask_control_ex, 28, 28, devinfo->is_g4x || devinfo->gen == 5)
178 F(cond_modifier, 27, 24)
179 FC(math_function, 27, 24, devinfo->gen >= 6)
180 F(exec_size, 23, 21)
181 F(pred_inv, 20, 20)
182 F(pred_control, 19, 16)
183 F(thread_control, 15, 14)
184 F(qtr_control, 13, 12)
185 FF(nib_control,
186 /* 4-6: doesn't exist */ -1, -1, -1, -1, -1, -1, -1, -1,
187 /* 7: */ 47, 47,
188 /* 8: */ 11, 11)
189 F8(no_dd_check, /* 4+ */ 11, 11, /* 8+ */ 10, 10)
190 F8(no_dd_clear, /* 4+ */ 10, 10, /* 8+ */ 9, 9)
191 F(access_mode, 8, 8)
192 /* Bit 7 is Reserved (for future Opcode expansion) */
193 F(opcode, 6, 0)
194
195 /**
196 * Three-source instructions:
197 * @{
198 */
199 F(3src_src2_reg_nr, 125, 118)
200 F(3src_src2_subreg_nr, 117, 115) /* Extra discontiguous bit on CHV? */
201 F(3src_src2_swizzle, 114, 107)
202 F(3src_src2_rep_ctrl, 106, 106)
203 F(3src_src1_reg_nr, 104, 97)
204 F(3src_src1_subreg_nr, 96, 94) /* Extra discontiguous bit on CHV? */
205 F(3src_src1_swizzle, 93, 86)
206 F(3src_src1_rep_ctrl, 85, 85)
207 F(3src_src0_reg_nr, 83, 76)
208 F(3src_src0_subreg_nr, 75, 73) /* Extra discontiguous bit on CHV? */
209 F(3src_src0_swizzle, 72, 65)
210 F(3src_src0_rep_ctrl, 64, 64)
211 F(3src_dst_reg_nr, 63, 56)
212 F(3src_dst_subreg_nr, 55, 53)
213 F(3src_dst_writemask, 52, 49)
214 F8(3src_nib_ctrl, 47, 47, 11, 11) /* only exists on IVB+ */
215 F8(3src_dst_type, 45, 44, 48, 46) /* only exists on IVB+ */
216 F8(3src_src_type, 43, 42, 45, 43)
217 F8(3src_src2_negate, 41, 41, 42, 42)
218 F8(3src_src2_abs, 40, 40, 41, 41)
219 F8(3src_src1_negate, 39, 39, 40, 40)
220 F8(3src_src1_abs, 38, 38, 39, 39)
221 F8(3src_src0_negate, 37, 37, 38, 38)
222 F8(3src_src0_abs, 36, 36, 37, 37)
223 F8(3src_flag_reg_nr, 34, 34, 33, 33)
224 F8(3src_flag_subreg_nr, 33, 33, 32, 32)
225 FF(3src_dst_reg_file,
226 /* 4-5: doesn't exist - no 3-source instructions */ -1, -1, -1, -1, -1, -1,
227 /* 6: */ 32, 32,
228 /* 7-8: doesn't exist - no MRFs */ -1, -1, -1, -1)
229 F(3src_saturate, 31, 31)
230 F(3src_debug_control, 30, 30)
231 F(3src_cmpt_control, 29, 29)
232 F(3src_acc_wr_control, 28, 28)
233 F(3src_cond_modifier, 27, 24)
234 F(3src_exec_size, 23, 21)
235 F(3src_pred_inv, 20, 20)
236 F(3src_pred_control, 19, 16)
237 F(3src_thread_control, 15, 14)
238 F(3src_qtr_control, 13, 12)
239 F8(3src_no_dd_check, 11, 11, 10, 10)
240 F8(3src_no_dd_clear, 10, 10, 9, 9)
241 F8(3src_mask_control, 9, 9, 34, 34)
242 F(3src_access_mode, 8, 8)
243 /* Bit 7 is Reserved (for future Opcode expansion) */
244 F(3src_opcode, 6, 0)
245 /** @} */
246
247 /**
248 * Flow control instruction bits:
249 * @{
250 */
251 static inline void
252 brw_inst_set_uip(const struct gen_device_info *devinfo,
253 brw_inst *inst, int32_t value)
254 {
255 assert(devinfo->gen >= 6);
256
257 if (devinfo->gen >= 8) {
258 brw_inst_set_bits(inst, 95, 64, (uint32_t)value);
259 } else {
260 assert(value <= (1 << 16) - 1);
261 assert(value > -(1 << 16));
262 brw_inst_set_bits(inst, 127, 112, (uint16_t)value);
263 }
264 }
265
266 static inline int32_t
267 brw_inst_uip(const struct gen_device_info *devinfo, const brw_inst *inst)
268 {
269 assert(devinfo->gen >= 6);
270
271 if (devinfo->gen >= 8) {
272 return brw_inst_bits(inst, 95, 64);
273 } else {
274 return (int16_t)brw_inst_bits(inst, 127, 112);
275 }
276 }
277
278 static inline void
279 brw_inst_set_jip(const struct gen_device_info *devinfo,
280 brw_inst *inst, int32_t value)
281 {
282 assert(devinfo->gen >= 6);
283
284 if (devinfo->gen >= 8) {
285 brw_inst_set_bits(inst, 127, 96, (uint32_t)value);
286 } else {
287 assert(value <= (1 << 15) - 1);
288 assert(value >= -(1 << 15));
289 brw_inst_set_bits(inst, 111, 96, (uint16_t)value);
290 }
291 }
292
293 static inline int32_t
294 brw_inst_jip(const struct gen_device_info *devinfo, const brw_inst *inst)
295 {
296 assert(devinfo->gen >= 6);
297
298 if (devinfo->gen >= 8) {
299 return brw_inst_bits(inst, 127, 96);
300 } else {
301 return (int16_t)brw_inst_bits(inst, 111, 96);
302 }
303 }
304
305 /** Like FC, but using int16_t to handle negative jump targets. */
306 #define FJ(name, high, low, assertions) \
307 static inline void \
308 brw_inst_set_##name(const struct gen_device_info *devinfo, brw_inst *inst, int16_t v) \
309 { \
310 assert(assertions); \
311 (void) devinfo; \
312 brw_inst_set_bits(inst, high, low, (uint16_t) v); \
313 } \
314 static inline int16_t \
315 brw_inst_##name(const struct gen_device_info *devinfo, const brw_inst *inst) \
316 { \
317 assert(assertions); \
318 (void) devinfo; \
319 return brw_inst_bits(inst, high, low); \
320 }
321
322 FJ(gen6_jump_count, 63, 48, devinfo->gen == 6)
323 FJ(gen4_jump_count, 111, 96, devinfo->gen < 6)
324 FC(gen4_pop_count, 115, 112, devinfo->gen < 6)
325 /** @} */
326
327 /* Message descriptor bits */
328 #define MD(x) ((x) + 96)
329
330 /**
331 * Fields for SEND messages:
332 * @{
333 */
334 F(eot, 127, 127)
335 FF(mlen,
336 /* 4: */ 119, 116,
337 /* 4.5: */ 119, 116,
338 /* 5: */ 124, 121,
339 /* 6: */ 124, 121,
340 /* 7: */ 124, 121,
341 /* 8: */ 124, 121);
342 FF(rlen,
343 /* 4: */ 115, 112,
344 /* 4.5: */ 115, 112,
345 /* 5: */ 120, 116,
346 /* 6: */ 120, 116,
347 /* 7: */ 120, 116,
348 /* 8: */ 120, 116);
349 FF(header_present,
350 /* 4: doesn't exist */ -1, -1, -1, -1,
351 /* 5: */ 115, 115,
352 /* 6: */ 115, 115,
353 /* 7: */ 115, 115,
354 /* 8: */ 115, 115)
355 F(gateway_notify, MD(16), MD(15))
356 FF(function_control,
357 /* 4: */ 111, 96,
358 /* 4.5: */ 111, 96,
359 /* 5: */ 114, 96,
360 /* 6: */ 114, 96,
361 /* 7: */ 114, 96,
362 /* 8: */ 114, 96)
363 FF(gateway_subfuncid,
364 /* 4: */ MD(1), MD(0),
365 /* 4.5: */ MD(1), MD(0),
366 /* 5: */ MD(1), MD(0), /* 2:0, but bit 2 is reserved MBZ */
367 /* 6: */ MD(2), MD(0),
368 /* 7: */ MD(2), MD(0),
369 /* 8: */ MD(2), MD(0))
370 FF(sfid,
371 /* 4: */ 123, 120, /* called msg_target */
372 /* 4.5 */ 123, 120,
373 /* 5: */ 95, 92,
374 /* 6: */ 27, 24,
375 /* 7: */ 27, 24,
376 /* 8: */ 27, 24)
377 FC(base_mrf, 27, 24, devinfo->gen < 6);
378 /** @} */
379
380 /**
381 * URB message function control bits:
382 * @{
383 */
384 FF(urb_per_slot_offset,
385 /* 4-6: */ -1, -1, -1, -1, -1, -1, -1, -1,
386 /* 7: */ MD(16), MD(16),
387 /* 8: */ MD(17), MD(17))
388 FC(urb_channel_mask_present, MD(15), MD(15), devinfo->gen >= 8)
389 FC(urb_complete, MD(15), MD(15), devinfo->gen < 8)
390 FC(urb_used, MD(14), MD(14), devinfo->gen < 7)
391 FC(urb_allocate, MD(13), MD(13), devinfo->gen < 7)
392 FF(urb_swizzle_control,
393 /* 4: */ MD(11), MD(10),
394 /* 4.5: */ MD(11), MD(10),
395 /* 5: */ MD(11), MD(10),
396 /* 6: */ MD(11), MD(10),
397 /* 7: */ MD(14), MD(14),
398 /* 8: */ MD(15), MD(15))
399 FF(urb_global_offset,
400 /* 4: */ MD( 9), MD(4),
401 /* 4.5: */ MD( 9), MD(4),
402 /* 5: */ MD( 9), MD(4),
403 /* 6: */ MD( 9), MD(4),
404 /* 7: */ MD(13), MD(3),
405 /* 8: */ MD(14), MD(4))
406 FF(urb_opcode,
407 /* 4: */ MD( 3), MD(0),
408 /* 4.5: */ MD( 3), MD(0),
409 /* 5: */ MD( 3), MD(0),
410 /* 6: */ MD( 3), MD(0),
411 /* 7: */ MD( 2), MD(0),
412 /* 8: */ MD( 3), MD(0))
413 /** @} */
414
415 /**
416 * Gen4-5 math messages:
417 * @{
418 */
419 FC(math_msg_data_type, MD(7), MD(7), devinfo->gen < 6)
420 FC(math_msg_saturate, MD(6), MD(6), devinfo->gen < 6)
421 FC(math_msg_precision, MD(5), MD(5), devinfo->gen < 6)
422 FC(math_msg_signed_int, MD(4), MD(4), devinfo->gen < 6)
423 FC(math_msg_function, MD(3), MD(0), devinfo->gen < 6)
424 /** @} */
425
426 /**
427 * Sampler message function control bits:
428 * @{
429 */
430 FF(sampler_simd_mode,
431 /* 4: doesn't exist */ -1, -1, -1, -1,
432 /* 5: */ MD(17), MD(16),
433 /* 6: */ MD(17), MD(16),
434 /* 7: */ MD(18), MD(17),
435 /* 8: */ MD(18), MD(17))
436 FF(sampler_msg_type,
437 /* 4: */ MD(15), MD(14),
438 /* 4.5: */ MD(15), MD(12),
439 /* 5: */ MD(15), MD(12),
440 /* 6: */ MD(15), MD(12),
441 /* 7: */ MD(16), MD(12),
442 /* 8: */ MD(16), MD(12))
443 FC(sampler_return_format, MD(13), MD(12), devinfo->gen == 4 && !devinfo->is_g4x)
444 F(sampler, MD(11), MD(8))
445 F(binding_table_index, MD( 7), MD(0)) /* also used by other messages */
446 /** @} */
447
448 /**
449 * Data port message function control bits:
450 * @{
451 */
452 FC(dp_category, MD(18), MD(18), devinfo->gen >= 7)
453
454 /* Gen4-5 store fields in different bits for read/write messages. */
455 FF(dp_read_msg_type,
456 /* 4: */ MD(13), MD(12),
457 /* 4.5: */ MD(13), MD(11),
458 /* 5: */ MD(13), MD(11),
459 /* 6: */ MD(16), MD(13),
460 /* 7: */ MD(17), MD(14),
461 /* 8: */ MD(17), MD(14))
462 FF(dp_write_msg_type,
463 /* 4: */ MD(14), MD(12),
464 /* 4.5: */ MD(14), MD(12),
465 /* 5: */ MD(14), MD(12),
466 /* 6: */ MD(16), MD(13),
467 /* 7: */ MD(17), MD(14),
468 /* 8: */ MD(17), MD(14))
469 FF(dp_read_msg_control,
470 /* 4: */ MD(11), MD( 8),
471 /* 4.5: */ MD(10), MD( 8),
472 /* 5: */ MD(10), MD( 8),
473 /* 6: */ MD(12), MD( 8),
474 /* 7: */ MD(13), MD( 8),
475 /* 8: */ MD(13), MD( 8))
476 FF(dp_write_msg_control,
477 /* 4: */ MD(11), MD( 8),
478 /* 4.5: */ MD(11), MD( 8),
479 /* 5: */ MD(11), MD( 8),
480 /* 6: */ MD(12), MD( 8),
481 /* 7: */ MD(13), MD( 8),
482 /* 8: */ MD(13), MD( 8))
483 FC(dp_read_target_cache, MD(15), MD(14), devinfo->gen < 6);
484
485 FF(dp_write_commit,
486 /* 4: */ MD(15), MD(15),
487 /* 4.5: */ MD(15), MD(15),
488 /* 5: */ MD(15), MD(15),
489 /* 6: */ MD(17), MD(17),
490 /* 7+: does not exist */ -1, -1, -1, -1)
491
492 /* Gen6+ use the same bit locations for everything. */
493 FF(dp_msg_type,
494 /* 4-5: use dp_read_msg_type or dp_write_msg_type instead */
495 -1, -1, -1, -1, -1, -1,
496 /* 6: */ MD(16), MD(13),
497 /* 7: */ MD(17), MD(14),
498 /* 8: */ MD(17), MD(14))
499 FF(dp_msg_control,
500 /* 4: */ MD(11), MD( 8),
501 /* 4.5-5: use dp_read_msg_control or dp_write_msg_control */ -1, -1, -1, -1,
502 /* 6: */ MD(12), MD( 8),
503 /* 7: */ MD(13), MD( 8),
504 /* 8: */ MD(13), MD( 8))
505 /** @} */
506
507 /**
508 * Scratch message bits (Gen7+):
509 * @{
510 */
511 FC(scratch_read_write, MD(17), MD(17), devinfo->gen >= 7) /* 0 = read, 1 = write */
512 FC(scratch_type, MD(16), MD(16), devinfo->gen >= 7) /* 0 = OWord, 1 = DWord */
513 FC(scratch_invalidate_after_read, MD(15), MD(15), devinfo->gen >= 7)
514 FC(scratch_block_size, MD(13), MD(12), devinfo->gen >= 7)
515 FC(scratch_addr_offset, MD(11), MD( 0), devinfo->gen >= 7)
516 /** @} */
517
518 /**
519 * Render Target message function control bits:
520 * @{
521 */
522 FF(rt_last,
523 /* 4: */ MD(11), MD(11),
524 /* 4.5: */ MD(11), MD(11),
525 /* 5: */ MD(11), MD(11),
526 /* 6: */ MD(12), MD(12),
527 /* 7: */ MD(12), MD(12),
528 /* 8: */ MD(12), MD(12))
529 FC(rt_slot_group, MD(11), MD(11), devinfo->gen >= 6)
530 F(rt_message_type, MD(10), MD( 8))
531 /** @} */
532
533 /**
534 * Thread Spawn message function control bits:
535 * @{
536 */
537 F(ts_resource_select, MD( 4), MD( 4))
538 F(ts_request_type, MD( 1), MD( 1))
539 F(ts_opcode, MD( 0), MD( 0))
540 /** @} */
541
542 /**
543 * Pixel Interpolator message function control bits:
544 * @{
545 */
546 F(pi_simd_mode, MD(16), MD(16))
547 F(pi_nopersp, MD(14), MD(14))
548 F(pi_message_type, MD(13), MD(12))
549 F(pi_slot_group, MD(11), MD(11))
550 F(pi_message_data, MD(7), MD(0))
551 /** @} */
552
553 /**
554 * Immediates:
555 * @{
556 */
557 static inline int
558 brw_inst_imm_d(const struct gen_device_info *devinfo, const brw_inst *insn)
559 {
560 (void) devinfo;
561 return brw_inst_bits(insn, 127, 96);
562 }
563
564 static inline unsigned
565 brw_inst_imm_ud(const struct gen_device_info *devinfo, const brw_inst *insn)
566 {
567 (void) devinfo;
568 return brw_inst_bits(insn, 127, 96);
569 }
570
571 static inline float
572 brw_inst_imm_f(const struct gen_device_info *devinfo, const brw_inst *insn)
573 {
574 union {
575 float f;
576 uint32_t u;
577 } ft;
578 (void) devinfo;
579 ft.u = brw_inst_bits(insn, 127, 96);
580 return ft.f;
581 }
582
583 static inline double
584 brw_inst_imm_df(const struct gen_device_info *devinfo, const brw_inst *insn)
585 {
586 union {
587 double d;
588 uint64_t u;
589 } dt;
590 (void) devinfo;
591 dt.u = brw_inst_bits(insn, 127, 64);
592 return dt.d;
593 }
594
595 static inline void
596 brw_inst_set_imm_d(const struct gen_device_info *devinfo,
597 brw_inst *insn, int value)
598 {
599 (void) devinfo;
600 return brw_inst_set_bits(insn, 127, 96, value);
601 }
602
603 static inline void
604 brw_inst_set_imm_ud(const struct gen_device_info *devinfo,
605 brw_inst *insn, unsigned value)
606 {
607 (void) devinfo;
608 return brw_inst_set_bits(insn, 127, 96, value);
609 }
610
611 static inline void
612 brw_inst_set_imm_f(const struct gen_device_info *devinfo,
613 brw_inst *insn, float value)
614 {
615 union {
616 float f;
617 uint32_t u;
618 } ft;
619 (void) devinfo;
620 ft.f = value;
621 brw_inst_set_bits(insn, 127, 96, ft.u);
622 }
623
624 static inline void
625 brw_inst_set_imm_df(const struct gen_device_info *devinfo,
626 brw_inst *insn, double value)
627 {
628 union {
629 double d;
630 uint64_t u;
631 } dt;
632 (void) devinfo;
633 dt.d = value;
634 brw_inst_set_bits(insn, 127, 64, dt.u);
635 }
636
637 static inline void
638 brw_inst_set_imm_uq(const struct gen_device_info *devinfo,
639 brw_inst *insn, uint64_t value)
640 {
641 (void) devinfo;
642 brw_inst_set_bits(insn, 127, 64, value);
643 }
644
645 /** @} */
646
647 /* The AddrImm fields are split into two discontiguous sections on Gen8+ */
648 #define BRW_IA1_ADDR_IMM(reg, g4_high, g4_low, g8_nine, g8_high, g8_low) \
649 static inline void \
650 brw_inst_set_##reg##_ia1_addr_imm(const struct gen_device_info *devinfo, \
651 brw_inst *inst, \
652 unsigned value) \
653 { \
654 assert((value & ~0x3ff) == 0); \
655 if (devinfo->gen >= 8) { \
656 brw_inst_set_bits(inst, g8_high, g8_low, value & 0x1ff); \
657 brw_inst_set_bits(inst, g8_nine, g8_nine, value >> 9); \
658 } else { \
659 brw_inst_set_bits(inst, g4_high, g4_low, value); \
660 } \
661 } \
662 static inline unsigned \
663 brw_inst_##reg##_ia1_addr_imm(const struct gen_device_info *devinfo, \
664 const brw_inst *inst) \
665 { \
666 if (devinfo->gen >= 8) { \
667 return brw_inst_bits(inst, g8_high, g8_low) | \
668 (brw_inst_bits(inst, g8_nine, g8_nine) << 9); \
669 } else { \
670 return brw_inst_bits(inst, g4_high, g4_low); \
671 } \
672 }
673
674 /* AddrImm[9:0] for Align1 Indirect Addressing */
675 /* -Gen 4- ----Gen8---- */
676 BRW_IA1_ADDR_IMM(src1, 105, 96, 121, 104, 96)
677 BRW_IA1_ADDR_IMM(src0, 73, 64, 95, 72, 64)
678 BRW_IA1_ADDR_IMM(dst, 57, 48, 47, 56, 48)
679
680 #define BRW_IA16_ADDR_IMM(reg, g4_high, g4_low, g8_nine, g8_high, g8_low) \
681 static inline void \
682 brw_inst_set_##reg##_ia16_addr_imm(const struct gen_device_info *devinfo, \
683 brw_inst *inst, unsigned value) \
684 { \
685 assert((value & ~0x3ff) == 0); \
686 if (devinfo->gen >= 8) { \
687 brw_inst_set_bits(inst, g8_high, g8_low, value & 0x1ff); \
688 brw_inst_set_bits(inst, g8_nine, g8_nine, value >> 9); \
689 } else { \
690 brw_inst_set_bits(inst, g4_high, g4_low, value >> 9); \
691 } \
692 } \
693 static inline unsigned \
694 brw_inst_##reg##_ia16_addr_imm(const struct gen_device_info *devinfo, \
695 const brw_inst *inst) \
696 { \
697 if (devinfo->gen >= 8) { \
698 return brw_inst_bits(inst, g8_high, g8_low) | \
699 (brw_inst_bits(inst, g8_nine, g8_nine) << 9); \
700 } else { \
701 return brw_inst_bits(inst, g4_high, g4_low); \
702 } \
703 }
704
705 /* AddrImm[9:0] for Align16 Indirect Addressing:
706 * Compared to Align1, these are missing the low 4 bits.
707 * -Gen 4- ----Gen8----
708 */
709 BRW_IA16_ADDR_IMM(src1, 105, 96, 121, 104, 100)
710 BRW_IA16_ADDR_IMM(src0, 73, 64, 95, 72, 68)
711 BRW_IA16_ADDR_IMM(dst, 57, 52, 47, 56, 52)
712
713 /**
714 * Fetch a set of contiguous bits from the instruction.
715 *
716 * Bits indices range from 0..127; fields may not cross 64-bit boundaries.
717 */
718 static inline uint64_t
719 brw_inst_bits(const brw_inst *inst, unsigned high, unsigned low)
720 {
721 /* We assume the field doesn't cross 64-bit boundaries. */
722 const unsigned word = high / 64;
723 assert(word == low / 64);
724
725 high %= 64;
726 low %= 64;
727
728 const uint64_t mask = (~0ull >> (64 - (high - low + 1)));
729
730 return (inst->data[word] >> low) & mask;
731 }
732
733 /**
734 * Set bits in the instruction, with proper shifting and masking.
735 *
736 * Bits indices range from 0..127; fields may not cross 64-bit boundaries.
737 */
738 static inline void
739 brw_inst_set_bits(brw_inst *inst, unsigned high, unsigned low, uint64_t value)
740 {
741 const unsigned word = high / 64;
742 assert(word == low / 64);
743
744 high %= 64;
745 low %= 64;
746
747 const uint64_t mask = (~0ull >> (64 - (high - low + 1))) << low;
748
749 /* Make sure the supplied value actually fits in the given bitfield. */
750 assert((value & (mask >> low)) == value);
751
752 inst->data[word] = (inst->data[word] & ~mask) | (value << low);
753 }
754
755 #undef BRW_IA16_ADDR_IMM
756 #undef BRW_IA1_ADDR_IMM
757 #undef MD
758 #undef F8
759 #undef FF
760 #undef BOUNDS
761 #undef F
762 #undef FC
763
764 typedef struct {
765 uint64_t data;
766 } brw_compact_inst;
767
768 /**
769 * Fetch a set of contiguous bits from the compacted instruction.
770 *
771 * Bits indices range from 0..63.
772 */
773 static inline unsigned
774 brw_compact_inst_bits(const brw_compact_inst *inst, unsigned high, unsigned low)
775 {
776 const uint64_t mask = (1ull << (high - low + 1)) - 1;
777
778 return (inst->data >> low) & mask;
779 }
780
781 /**
782 * Set bits in the compacted instruction.
783 *
784 * Bits indices range from 0..63.
785 */
786 static inline void
787 brw_compact_inst_set_bits(brw_compact_inst *inst, unsigned high, unsigned low,
788 uint64_t value)
789 {
790 const uint64_t mask = ((1ull << (high - low + 1)) - 1) << low;
791
792 /* Make sure the supplied value actually fits in the given bitfield. */
793 assert((value & (mask >> low)) == value);
794
795 inst->data = (inst->data & ~mask) | (value << low);
796 }
797
798 #define FC(name, high, low, assertions) \
799 static inline void \
800 brw_compact_inst_set_##name(const struct gen_device_info *devinfo, \
801 brw_compact_inst *inst, unsigned v) \
802 { \
803 assert(assertions); \
804 (void) devinfo; \
805 brw_compact_inst_set_bits(inst, high, low, v); \
806 } \
807 static inline unsigned \
808 brw_compact_inst_##name(const struct gen_device_info *devinfo, \
809 const brw_compact_inst *inst) \
810 { \
811 assert(assertions); \
812 (void) devinfo; \
813 return brw_compact_inst_bits(inst, high, low); \
814 }
815
816 /* A simple macro for fields which stay in the same place on all generations. */
817 #define F(name, high, low) FC(name, high, low, true)
818
819 F(src1_reg_nr, 63, 56)
820 F(src0_reg_nr, 55, 48)
821 F(dst_reg_nr, 47, 40)
822 F(src1_index, 39, 35)
823 F(src0_index, 34, 30)
824 F(cmpt_control, 29, 29) /* Same location as brw_inst */
825 FC(flag_subreg_nr, 28, 28, devinfo->gen <= 6)
826 F(cond_modifier, 27, 24) /* Same location as brw_inst */
827 FC(acc_wr_control, 23, 23, devinfo->gen >= 6)
828 FC(mask_control_ex, 23, 23, devinfo->is_g4x || devinfo->gen == 5)
829 F(subreg_index, 22, 18)
830 F(datatype_index, 17, 13)
831 F(control_index, 12, 8)
832 F(debug_control, 7, 7)
833 F(opcode, 6, 0) /* Same location as brw_inst */
834
835 /**
836 * (Gen8+) Compacted three-source instructions:
837 * @{
838 */
839 FC(3src_src2_reg_nr, 63, 57, devinfo->gen >= 8)
840 FC(3src_src1_reg_nr, 56, 50, devinfo->gen >= 8)
841 FC(3src_src0_reg_nr, 49, 43, devinfo->gen >= 8)
842 FC(3src_src2_subreg_nr, 42, 40, devinfo->gen >= 8)
843 FC(3src_src1_subreg_nr, 39, 37, devinfo->gen >= 8)
844 FC(3src_src0_subreg_nr, 36, 34, devinfo->gen >= 8)
845 FC(3src_src2_rep_ctrl, 33, 33, devinfo->gen >= 8)
846 FC(3src_src1_rep_ctrl, 32, 32, devinfo->gen >= 8)
847 FC(3src_saturate, 31, 31, devinfo->gen >= 8)
848 FC(3src_debug_control, 30, 30, devinfo->gen >= 8)
849 FC(3src_cmpt_control, 29, 29, devinfo->gen >= 8)
850 FC(3src_src0_rep_ctrl, 28, 28, devinfo->gen >= 8)
851 /* Reserved */
852 FC(3src_dst_reg_nr, 18, 12, devinfo->gen >= 8)
853 FC(3src_source_index, 11, 10, devinfo->gen >= 8)
854 FC(3src_control_index, 9, 8, devinfo->gen >= 8)
855 /* Bit 7 is Reserved (for future Opcode expansion) */
856 FC(3src_opcode, 6, 0, devinfo->gen >= 8)
857 /** @} */
858
859 #undef F
860
861 #ifdef __cplusplus
862 }
863 #endif
864
865 #endif