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i965: Maximum allowed size of SEND messages is 15 (4 bits)
[mesa.git] / src / mesa / drivers / dri / i965 / brw_inst.h
1 /*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /**
25 * @file brw_inst.h
26 *
27 * A representation of i965 EU assembly instructions, with helper methods to
28 * get and set various fields. This is the actual hardware format.
29 */
30
31 #ifndef BRW_INST_H
32 #define BRW_INST_H
33
34 #include <stdint.h>
35
36 #include "brw_context.h"
37
38 #ifdef __cplusplus
39 extern "C" {
40 #endif
41
42 /** Maximum SEND message length */
43 #define BRW_MAX_MSG_LENGTH 15
44
45 /* brw_context.h has a forward declaration of brw_inst, so name the struct. */
46 typedef struct brw_inst {
47 uint64_t data[2];
48 } brw_inst;
49
50 static inline uint64_t brw_inst_bits(const brw_inst *inst,
51 unsigned high, unsigned low);
52 static inline void brw_inst_set_bits(brw_inst *inst,
53 unsigned high, unsigned low,
54 uint64_t value);
55
56 #define FC(name, high, low, assertions) \
57 static inline void \
58 brw_inst_set_##name(const struct brw_device_info *devinfo, \
59 brw_inst *inst, uint64_t v) \
60 { \
61 assert(assertions); \
62 (void) devinfo; \
63 brw_inst_set_bits(inst, high, low, v); \
64 } \
65 static inline uint64_t \
66 brw_inst_##name(const struct brw_device_info *devinfo, \
67 const brw_inst *inst) \
68 { \
69 assert(assertions); \
70 (void) devinfo; \
71 return brw_inst_bits(inst, high, low); \
72 }
73
74 /* A simple macro for fields which stay in the same place on all generations. */
75 #define F(name, high, low) FC(name, high, low, true)
76
77 #define BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, hi7, lo7, hi8, lo8) \
78 unsigned high, low; \
79 if (devinfo->gen >= 8) { \
80 high = hi8; low = lo8; \
81 } else if (devinfo->gen >= 7) { \
82 high = hi7; low = lo7; \
83 } else if (devinfo->gen >= 6) { \
84 high = hi6; low = lo6; \
85 } else if (devinfo->gen >= 5) { \
86 high = hi5; low = lo5; \
87 } else if (devinfo->is_g4x) { \
88 high = hi45; low = lo45; \
89 } else { \
90 high = hi4; low = lo4; \
91 } \
92 assert(((int) high) != -1 && ((int) low) != -1); \
93
94 /* A general macro for cases where the field has moved to several different
95 * bit locations across generations. GCC appears to combine cases where the
96 * bits are identical, removing some of the inefficiency.
97 */
98 #define FF(name, hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, hi7, lo7, hi8, lo8)\
99 static inline void \
100 brw_inst_set_##name(const struct brw_device_info *devinfo, \
101 brw_inst *inst, uint64_t value) \
102 { \
103 BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, hi7, lo7, hi8, lo8) \
104 brw_inst_set_bits(inst, high, low, value); \
105 } \
106 static inline uint64_t \
107 brw_inst_##name(const struct brw_device_info *devinfo, const brw_inst *inst) \
108 { \
109 BOUNDS(hi4, lo4, hi45, lo45, hi5, lo5, hi6, lo6, hi7, lo7, hi8, lo8) \
110 return brw_inst_bits(inst, high, low); \
111 }
112
113 /* A macro for fields which moved as of Gen8+. */
114 #define F8(name, gen4_high, gen4_low, gen8_high, gen8_low) \
115 FF(name, \
116 /* 4: */ gen4_high, gen4_low, \
117 /* 4.5: */ gen4_high, gen4_low, \
118 /* 5: */ gen4_high, gen4_low, \
119 /* 6: */ gen4_high, gen4_low, \
120 /* 7: */ gen4_high, gen4_low, \
121 /* 8: */ gen8_high, gen8_low);
122
123 F(src1_vstride, 120, 117)
124 F(src1_width, 116, 114)
125 F(src1_da16_swiz_w, 115, 114)
126 F(src1_da16_swiz_z, 113, 112)
127 F(src1_hstride, 113, 112)
128 F(src1_address_mode, 111, 111)
129 /** Src1.SrcMod @{ */
130 F(src1_negate, 110, 110)
131 F(src1_abs, 109, 109)
132 /** @} */
133 F8(src1_ia_subreg_nr, /* 4+ */ 108, 106, /* 8+ */ 108, 105)
134 F(src1_da_reg_nr, 108, 101)
135 F(src1_da16_subreg_nr, 100, 100)
136 F(src1_da1_subreg_nr, 100, 96)
137 F(src1_da16_swiz_y, 99, 98)
138 F(src1_da16_swiz_x, 97, 96)
139 F8(src1_reg_type, /* 4+ */ 46, 44, /* 8+ */ 94, 91)
140 F8(src1_reg_file, /* 4+ */ 43, 42, /* 8+ */ 90, 89)
141 F(src0_vstride, 88, 85)
142 F(src0_width, 84, 82)
143 F(src0_da16_swiz_w, 83, 82)
144 F(src0_da16_swiz_z, 81, 80)
145 F(src0_hstride, 81, 80)
146 F(src0_address_mode, 79, 79)
147 /** Src0.SrcMod @{ */
148 F(src0_negate, 78, 78)
149 F(src0_abs, 77, 77)
150 /** @} */
151 F8(src0_ia_subreg_nr, /* 4+ */ 76, 74, /* 8+ */ 76, 73)
152 F(src0_da_reg_nr, 76, 69)
153 F(src0_da16_subreg_nr, 68, 68)
154 F(src0_da1_subreg_nr, 68, 64)
155 F(src0_da16_swiz_y, 67, 66)
156 F(src0_da16_swiz_x, 65, 64)
157 F(dst_address_mode, 63, 63)
158 F(dst_hstride, 62, 61)
159 F8(dst_ia_subreg_nr, /* 4+ */ 60, 58, /* 8+ */ 60, 57)
160 F(dst_da_reg_nr, 60, 53)
161 F(dst_da16_subreg_nr, 52, 52)
162 F(dst_da1_subreg_nr, 52, 48)
163 F(da16_writemask, 51, 48) /* Dst.ChanEn */
164 F8(src0_reg_type, /* 4+ */ 41, 39, /* 8+ */ 46, 43)
165 F8(src0_reg_file, /* 4+ */ 38, 37, /* 8+ */ 42, 41)
166 F8(dst_reg_type, /* 4+ */ 36, 34, /* 8+ */ 40, 37)
167 F8(dst_reg_file, /* 4+ */ 33, 32, /* 8+ */ 36, 35)
168 F8(mask_control, /* 4+ */ 9, 9, /* 8+ */ 34, 34)
169 FF(flag_reg_nr,
170 /* 4-6: doesn't exist */ -1, -1, -1, -1, -1, -1, -1, -1,
171 /* 7: */ 90, 90,
172 /* 8: */ 33, 33)
173 F8(flag_subreg_nr, /* 4+ */ 89, 89, /* 8+ */ 32, 32)
174 F(saturate, 31, 31)
175 F(debug_control, 30, 30)
176 F(cmpt_control, 29, 29)
177 FC(branch_control, 28, 28, devinfo->gen >= 8)
178 F(acc_wr_control, 28, 28)
179 F(cond_modifier, 27, 24)
180 FC(math_function, 27, 24, devinfo->gen >= 6)
181 F(exec_size, 23, 21)
182 F(pred_inv, 20, 20)
183 F(pred_control, 19, 16)
184 F(thread_control, 15, 14)
185 F(qtr_control, 13, 12)
186 FF(nib_control,
187 /* 4-6: doesn't exist */ -1, -1, -1, -1, -1, -1, -1, -1,
188 /* 7: */ 47, 47,
189 /* 8: */ 11, 11)
190 F8(no_dd_check, /* 4+ */ 11, 11, /* 8+ */ 10, 10)
191 F8(no_dd_clear, /* 4+ */ 10, 10, /* 8+ */ 9, 9)
192 F(access_mode, 8, 8)
193 /* Bit 7 is Reserved (for future Opcode expansion) */
194 F(opcode, 6, 0)
195
196 /**
197 * Three-source instructions:
198 * @{
199 */
200 F(3src_src2_reg_nr, 125, 118)
201 F(3src_src2_subreg_nr, 117, 115) /* Extra discontiguous bit on CHV? */
202 F(3src_src2_swizzle, 114, 107)
203 F(3src_src2_rep_ctrl, 106, 106)
204 F(3src_src1_reg_nr, 104, 97)
205 F(3src_src1_subreg_nr, 96, 94) /* Extra discontiguous bit on CHV? */
206 F(3src_src1_swizzle, 93, 86)
207 F(3src_src1_rep_ctrl, 85, 85)
208 F(3src_src0_reg_nr, 83, 76)
209 F(3src_src0_subreg_nr, 75, 73) /* Extra discontiguous bit on CHV? */
210 F(3src_src0_swizzle, 72, 65)
211 F(3src_src0_rep_ctrl, 64, 64)
212 F(3src_dst_reg_nr, 63, 56)
213 F(3src_dst_subreg_nr, 55, 53)
214 F(3src_dst_writemask, 52, 49)
215 F8(3src_nib_ctrl, 47, 47, 11, 11) /* only exists on IVB+ */
216 F8(3src_dst_type, 45, 44, 48, 46) /* only exists on IVB+ */
217 F8(3src_src_type, 43, 42, 45, 43)
218 F8(3src_src2_negate, 41, 41, 42, 42)
219 F8(3src_src2_abs, 40, 40, 41, 41)
220 F8(3src_src1_negate, 39, 39, 40, 40)
221 F8(3src_src1_abs, 38, 38, 39, 39)
222 F8(3src_src0_negate, 37, 37, 38, 38)
223 F8(3src_src0_abs, 36, 36, 37, 37)
224 F8(3src_flag_reg_nr, 34, 34, 33, 33)
225 F8(3src_flag_subreg_nr, 33, 33, 32, 32)
226 FF(3src_dst_reg_file,
227 /* 4-5: doesn't exist - no 3-source instructions */ -1, -1, -1, -1, -1, -1,
228 /* 6: */ 32, 32,
229 /* 7-8: doesn't exist - no MRFs */ -1, -1, -1, -1)
230 F(3src_saturate, 31, 31)
231 F(3src_debug_control, 30, 30)
232 F(3src_cmpt_control, 29, 29)
233 F(3src_acc_wr_control, 28, 28)
234 F(3src_cond_modifier, 27, 24)
235 F(3src_exec_size, 23, 21)
236 F(3src_pred_inv, 20, 20)
237 F(3src_pred_control, 19, 16)
238 F(3src_thread_control, 15, 14)
239 F(3src_qtr_control, 13, 12)
240 F8(3src_no_dd_check, 11, 11, 10, 10)
241 F8(3src_no_dd_clear, 10, 10, 9, 9)
242 F8(3src_mask_control, 9, 9, 34, 34)
243 F(3src_access_mode, 8, 8)
244 /* Bit 7 is Reserved (for future Opcode expansion) */
245 F(3src_opcode, 6, 0)
246 /** @} */
247
248 /**
249 * Flow control instruction bits:
250 * @{
251 */
252 static inline void
253 brw_inst_set_uip(const struct brw_device_info *devinfo,
254 brw_inst *inst, int32_t value)
255 {
256 assert(devinfo->gen >= 6);
257
258 if (devinfo->gen >= 8) {
259 brw_inst_set_bits(inst, 95, 64, (uint32_t)value);
260 } else {
261 assert(value <= (1 << 16) - 1);
262 assert(value > -(1 << 16));
263 brw_inst_set_bits(inst, 127, 112, (uint16_t)value);
264 }
265 }
266
267 static inline int32_t
268 brw_inst_uip(const struct brw_device_info *devinfo, const brw_inst *inst)
269 {
270 assert(devinfo->gen >= 6);
271
272 if (devinfo->gen >= 8) {
273 return brw_inst_bits(inst, 95, 64);
274 } else {
275 return (int16_t)brw_inst_bits(inst, 127, 112);
276 }
277 }
278
279 static inline void
280 brw_inst_set_jip(const struct brw_device_info *devinfo,
281 brw_inst *inst, int32_t value)
282 {
283 assert(devinfo->gen >= 6);
284
285 if (devinfo->gen >= 8) {
286 brw_inst_set_bits(inst, 127, 96, (uint32_t)value);
287 } else {
288 assert(value <= (1 << 16) - 1);
289 assert(value > -(1 << 16));
290 brw_inst_set_bits(inst, 111, 96, (uint16_t)value);
291 }
292 }
293
294 static inline int32_t
295 brw_inst_jip(const struct brw_device_info *devinfo, const brw_inst *inst)
296 {
297 assert(devinfo->gen >= 6);
298
299 if (devinfo->gen >= 8) {
300 return brw_inst_bits(inst, 127, 96);
301 } else {
302 return (int16_t)brw_inst_bits(inst, 111, 96);
303 }
304 }
305
306 /** Like FC, but using int16_t to handle negative jump targets. */
307 #define FJ(name, high, low, assertions) \
308 static inline void \
309 brw_inst_set_##name(const struct brw_device_info *devinfo, brw_inst *inst, int16_t v) \
310 { \
311 assert(assertions); \
312 (void) devinfo; \
313 brw_inst_set_bits(inst, high, low, (uint16_t) v); \
314 } \
315 static inline int16_t \
316 brw_inst_##name(const struct brw_device_info *devinfo, const brw_inst *inst) \
317 { \
318 assert(assertions); \
319 (void) devinfo; \
320 return brw_inst_bits(inst, high, low); \
321 }
322
323 FJ(gen6_jump_count, 63, 48, devinfo->gen == 6)
324 FJ(gen4_jump_count, 111, 96, devinfo->gen < 6)
325 FC(gen4_pop_count, 115, 112, devinfo->gen < 6)
326 /** @} */
327
328 /* Message descriptor bits */
329 #define MD(x) ((x) + 96)
330
331 /**
332 * Fields for SEND messages:
333 * @{
334 */
335 F(eot, 127, 127)
336 FF(mlen,
337 /* 4: */ 119, 116,
338 /* 4.5: */ 119, 116,
339 /* 5: */ 124, 121,
340 /* 6: */ 124, 121,
341 /* 7: */ 124, 121,
342 /* 8: */ 124, 121);
343 FF(rlen,
344 /* 4: */ 115, 112,
345 /* 4.5: */ 115, 112,
346 /* 5: */ 120, 116,
347 /* 6: */ 120, 116,
348 /* 7: */ 120, 116,
349 /* 8: */ 120, 116);
350 FF(header_present,
351 /* 4: doesn't exist */ -1, -1, -1, -1,
352 /* 5: */ 115, 115,
353 /* 6: */ 115, 115,
354 /* 7: */ 115, 115,
355 /* 8: */ 115, 115)
356 F(gateway_notify, MD(16), MD(15))
357 FF(function_control,
358 /* 4: */ 111, 96,
359 /* 4.5: */ 111, 96,
360 /* 5: */ 114, 96,
361 /* 6: */ 114, 96,
362 /* 7: */ 114, 96,
363 /* 8: */ 114, 96)
364 FF(gateway_subfuncid,
365 /* 4: */ MD(1), MD(0),
366 /* 4.5: */ MD(1), MD(0),
367 /* 5: */ MD(1), MD(0), /* 2:0, but bit 2 is reserved MBZ */
368 /* 6: */ MD(2), MD(0),
369 /* 7: */ MD(2), MD(0),
370 /* 8: */ MD(2), MD(0))
371 FF(sfid,
372 /* 4: */ 123, 120, /* called msg_target */
373 /* 4.5 */ 123, 120,
374 /* 5: */ 95, 92,
375 /* 6: */ 27, 24,
376 /* 7: */ 27, 24,
377 /* 8: */ 27, 24)
378 FC(base_mrf, 27, 24, devinfo->gen < 6);
379 /** @} */
380
381 /**
382 * URB message function control bits:
383 * @{
384 */
385 FF(urb_per_slot_offset,
386 /* 4-6: */ -1, -1, -1, -1, -1, -1, -1, -1,
387 /* 7: */ MD(16), MD(16),
388 /* 8: */ MD(17), MD(17))
389 FC(urb_complete, MD(15), MD(15), devinfo->gen < 8)
390 FC(urb_used, MD(14), MD(14), devinfo->gen < 7)
391 FC(urb_allocate, MD(13), MD(13), devinfo->gen < 7)
392 FF(urb_swizzle_control,
393 /* 4: */ MD(11), MD(10),
394 /* 4.5: */ MD(11), MD(10),
395 /* 5: */ MD(11), MD(10),
396 /* 6: */ MD(11), MD(10),
397 /* 7: */ MD(14), MD(14),
398 /* 8: */ MD(15), MD(15))
399 FF(urb_global_offset,
400 /* 4: */ MD( 9), MD(4),
401 /* 4.5: */ MD( 9), MD(4),
402 /* 5: */ MD( 9), MD(4),
403 /* 6: */ MD( 9), MD(4),
404 /* 7: */ MD(13), MD(3),
405 /* 8: */ MD(14), MD(4))
406 FF(urb_opcode,
407 /* 4: */ MD( 3), MD(0),
408 /* 4.5: */ MD( 3), MD(0),
409 /* 5: */ MD( 3), MD(0),
410 /* 6: */ MD( 3), MD(0),
411 /* 7: */ MD( 2), MD(0),
412 /* 8: */ MD( 3), MD(0))
413 /** @} */
414
415 /**
416 * Gen4-5 math messages:
417 * @{
418 */
419 FC(math_msg_data_type, MD(7), MD(7), devinfo->gen < 6)
420 FC(math_msg_saturate, MD(6), MD(6), devinfo->gen < 6)
421 FC(math_msg_precision, MD(5), MD(5), devinfo->gen < 6)
422 FC(math_msg_signed_int, MD(4), MD(4), devinfo->gen < 6)
423 FC(math_msg_function, MD(3), MD(0), devinfo->gen < 6)
424 /** @} */
425
426 /**
427 * Sampler message function control bits:
428 * @{
429 */
430 FF(sampler_simd_mode,
431 /* 4: doesn't exist */ -1, -1, -1, -1,
432 /* 5: */ MD(17), MD(16),
433 /* 6: */ MD(17), MD(16),
434 /* 7: */ MD(18), MD(17),
435 /* 8: */ MD(18), MD(17))
436 FF(sampler_msg_type,
437 /* 4: */ MD(15), MD(14),
438 /* 4.5: */ MD(15), MD(12),
439 /* 5: */ MD(15), MD(12),
440 /* 6: */ MD(15), MD(12),
441 /* 7: */ MD(16), MD(12),
442 /* 8: */ MD(16), MD(12))
443 FC(sampler_return_format, MD(13), MD(12), devinfo->gen == 4 && !devinfo->is_g4x)
444 F(sampler, MD(11), MD(8))
445 F(binding_table_index, MD( 7), MD(0)) /* also used by other messages */
446 /** @} */
447
448 /**
449 * Data port message function control bits:
450 * @{
451 */
452 FC(dp_category, MD(18), MD(18), devinfo->gen >= 7)
453
454 /* Gen4-5 store fields in different bits for read/write messages. */
455 FF(dp_read_msg_type,
456 /* 4: */ MD(13), MD(12),
457 /* 4.5: */ MD(13), MD(11),
458 /* 5: */ MD(13), MD(11),
459 /* 6: */ MD(16), MD(13),
460 /* 7: */ MD(17), MD(14),
461 /* 8: */ MD(17), MD(14))
462 FF(dp_write_msg_type,
463 /* 4: */ MD(14), MD(12),
464 /* 4.5: */ MD(14), MD(12),
465 /* 5: */ MD(14), MD(12),
466 /* 6: */ MD(16), MD(13),
467 /* 7: */ MD(17), MD(14),
468 /* 8: */ MD(17), MD(14))
469 FF(dp_read_msg_control,
470 /* 4: */ MD(11), MD( 8),
471 /* 4.5: */ MD(10), MD( 8),
472 /* 5: */ MD(10), MD( 8),
473 /* 6: */ MD(12), MD( 8),
474 /* 7: */ MD(13), MD( 8),
475 /* 8: */ MD(13), MD( 8))
476 FF(dp_write_msg_control,
477 /* 4: */ MD(11), MD( 8),
478 /* 4.5: */ MD(11), MD( 8),
479 /* 5: */ MD(11), MD( 8),
480 /* 6: */ MD(12), MD( 8),
481 /* 7: */ MD(13), MD( 8),
482 /* 8: */ MD(13), MD( 8))
483 FC(dp_read_target_cache, MD(15), MD(14), devinfo->gen < 6);
484
485 FF(dp_write_commit,
486 /* 4: */ MD(15), MD(15),
487 /* 4.5: */ MD(15), MD(15),
488 /* 5: */ MD(15), MD(15),
489 /* 6: */ MD(17), MD(17),
490 /* 7+: does not exist */ -1, -1, -1, -1)
491
492 /* Gen6+ use the same bit locations for everything. */
493 FF(dp_msg_type,
494 /* 4-5: use dp_read_msg_type or dp_write_msg_type instead */
495 -1, -1, -1, -1, -1, -1,
496 /* 6: */ MD(16), MD(13),
497 /* 7: */ MD(17), MD(14),
498 /* 8: */ MD(17), MD(14))
499 FF(dp_msg_control,
500 /* 4: */ MD(11), MD( 8),
501 /* 4.5-5: use dp_read_msg_control or dp_write_msg_control */ -1, -1, -1, -1,
502 /* 6: */ MD(12), MD( 8),
503 /* 7: */ MD(13), MD( 8),
504 /* 8: */ MD(13), MD( 8))
505 /** @} */
506
507 /**
508 * Scratch message bits (Gen7+):
509 * @{
510 */
511 FC(scratch_read_write, MD(17), MD(17), devinfo->gen >= 7) /* 0 = read, 1 = write */
512 FC(scratch_type, MD(16), MD(16), devinfo->gen >= 7) /* 0 = OWord, 1 = DWord */
513 FC(scratch_invalidate_after_read, MD(15), MD(15), devinfo->gen >= 7)
514 FC(scratch_block_size, MD(13), MD(12), devinfo->gen >= 7)
515 FC(scratch_addr_offset, MD(11), MD( 0), devinfo->gen >= 7)
516 /** @} */
517
518 /**
519 * Render Target message function control bits:
520 * @{
521 */
522 FF(rt_last,
523 /* 4: */ MD(11), MD(11),
524 /* 4.5: */ MD(11), MD(11),
525 /* 5: */ MD(11), MD(11),
526 /* 6: */ MD(12), MD(12),
527 /* 7: */ MD(12), MD(12),
528 /* 8: */ MD(12), MD(12))
529 FC(rt_slot_group, MD(11), MD(11), devinfo->gen >= 6)
530 F(rt_message_type, MD(10), MD( 8))
531 /** @} */
532
533 /**
534 * Thread Spawn message function control bits:
535 * @{
536 */
537 F(ts_resource_select, MD( 4), MD( 4))
538 F(ts_request_type, MD( 1), MD( 1))
539 F(ts_opcode, MD( 0), MD( 0))
540 /** @} */
541
542 /**
543 * Pixel Interpolator message function control bits:
544 * @{
545 */
546 F(pi_simd_mode, MD(16), MD(16))
547 F(pi_nopersp, MD(14), MD(14))
548 F(pi_message_type, MD(13), MD(12))
549 F(pi_slot_group, MD(11), MD(11))
550 F(pi_message_data, MD(7), MD(0))
551 /** @} */
552
553 /**
554 * Immediates:
555 * @{
556 */
557 static inline int
558 brw_inst_imm_d(const struct brw_device_info *devinfo, const brw_inst *insn)
559 {
560 (void) devinfo;
561 return brw_inst_bits(insn, 127, 96);
562 }
563
564 static inline unsigned
565 brw_inst_imm_ud(const struct brw_device_info *devinfo, const brw_inst *insn)
566 {
567 (void) devinfo;
568 return brw_inst_bits(insn, 127, 96);
569 }
570
571 static inline float
572 brw_inst_imm_f(const struct brw_device_info *devinfo, const brw_inst *insn)
573 {
574 fi_type ft;
575 (void) devinfo;
576 ft.u = brw_inst_bits(insn, 127, 96);
577 return ft.f;
578 }
579
580 static inline void
581 brw_inst_set_imm_d(const struct brw_device_info *devinfo,
582 brw_inst *insn, int value)
583 {
584 (void) devinfo;
585 return brw_inst_set_bits(insn, 127, 96, value);
586 }
587
588 static inline void
589 brw_inst_set_imm_ud(const struct brw_device_info *devinfo,
590 brw_inst *insn, unsigned value)
591 {
592 (void) devinfo;
593 return brw_inst_set_bits(insn, 127, 96, value);
594 }
595
596 static inline void
597 brw_inst_set_imm_f(const struct brw_device_info *devinfo,
598 brw_inst *insn, float value)
599 {
600 fi_type ft;
601 (void) devinfo;
602 ft.f = value;
603 brw_inst_set_bits(insn, 127, 96, ft.u);
604 }
605
606 /** @} */
607
608 /* The AddrImm fields are split into two discontiguous sections on Gen8+ */
609 #define BRW_IA1_ADDR_IMM(reg, g4_high, g4_low, g8_nine, g8_high, g8_low) \
610 static inline void \
611 brw_inst_set_##reg##_ia1_addr_imm(const struct brw_device_info *devinfo, \
612 brw_inst *inst, \
613 unsigned value) \
614 { \
615 assert((value & ~0x3ff) == 0); \
616 if (devinfo->gen >= 8) { \
617 brw_inst_set_bits(inst, g8_high, g8_low, value & 0x1ff); \
618 brw_inst_set_bits(inst, g8_nine, g8_nine, value >> 9); \
619 } else { \
620 brw_inst_set_bits(inst, g4_high, g4_low, value); \
621 } \
622 } \
623 static inline unsigned \
624 brw_inst_##reg##_ia1_addr_imm(const struct brw_device_info *devinfo, \
625 const brw_inst *inst) \
626 { \
627 if (devinfo->gen >= 8) { \
628 return brw_inst_bits(inst, g8_high, g8_low) | \
629 (brw_inst_bits(inst, g8_nine, g8_nine) << 9); \
630 } else { \
631 return brw_inst_bits(inst, g4_high, g4_low); \
632 } \
633 }
634
635 /* AddrImm[9:0] for Align1 Indirect Addressing */
636 /* -Gen 4- ----Gen8---- */
637 BRW_IA1_ADDR_IMM(src1, 105, 96, 121, 104, 96)
638 BRW_IA1_ADDR_IMM(src0, 73, 64, 95, 72, 64)
639 BRW_IA1_ADDR_IMM(dst, 57, 48, 47, 56, 48)
640
641 #define BRW_IA16_ADDR_IMM(reg, g4_high, g4_low, g8_nine, g8_high, g8_low) \
642 static inline void \
643 brw_inst_set_##reg##_ia16_addr_imm(const struct brw_device_info *devinfo, \
644 brw_inst *inst, unsigned value) \
645 { \
646 assert((value & ~0x3ff) == 0); \
647 if (devinfo->gen >= 8) { \
648 brw_inst_set_bits(inst, g8_high, g8_low, value & 0x1ff); \
649 brw_inst_set_bits(inst, g8_nine, g8_nine, value >> 9); \
650 } else { \
651 brw_inst_set_bits(inst, g4_high, g4_low, value >> 9); \
652 } \
653 } \
654 static inline unsigned \
655 brw_inst_##reg##_ia16_addr_imm(const struct brw_device_info *devinfo, \
656 const brw_inst *inst) \
657 { \
658 if (devinfo->gen >= 8) { \
659 return brw_inst_bits(inst, g8_high, g8_low) | \
660 (brw_inst_bits(inst, g8_nine, g8_nine) << 9); \
661 } else { \
662 return brw_inst_bits(inst, g4_high, g4_low); \
663 } \
664 }
665
666 /* AddrImm[9:0] for Align16 Indirect Addressing:
667 * Compared to Align1, these are missing the low 4 bits.
668 * -Gen 4- ----Gen8----
669 */
670 BRW_IA16_ADDR_IMM(src1, 105, 96, 121, 104, 100)
671 BRW_IA16_ADDR_IMM(src0, 73, 64, 95, 72, 68)
672 BRW_IA16_ADDR_IMM(dst, 57, 52, 47, 56, 52)
673
674 /**
675 * Fetch a set of contiguous bits from the instruction.
676 *
677 * Bits indices range from 0..127; fields may not cross 64-bit boundaries.
678 */
679 static inline uint64_t
680 brw_inst_bits(const brw_inst *inst, unsigned high, unsigned low)
681 {
682 /* We assume the field doesn't cross 64-bit boundaries. */
683 const unsigned word = high / 64;
684 assert(word == low / 64);
685
686 high %= 64;
687 low %= 64;
688
689 const uint64_t mask = (1ull << (high - low + 1)) - 1;
690
691 return (inst->data[word] >> low) & mask;
692 }
693
694 /**
695 * Set bits in the instruction, with proper shifting and masking.
696 *
697 * Bits indices range from 0..127; fields may not cross 64-bit boundaries.
698 */
699 static inline void
700 brw_inst_set_bits(brw_inst *inst, unsigned high, unsigned low, uint64_t value)
701 {
702 const unsigned word = high / 64;
703 assert(word == low / 64);
704
705 high %= 64;
706 low %= 64;
707
708 const uint64_t mask = ((1ull << (high - low + 1)) - 1) << low;
709
710 /* Make sure the supplied value actually fits in the given bitfield. */
711 assert((value & (mask >> low)) == value);
712
713 inst->data[word] = (inst->data[word] & ~mask) | (value << low);
714 }
715
716 #undef BRW_IA16_ADDR_IMM
717 #undef BRW_IA1_ADDR_IMM
718 #undef MD
719 #undef F8
720 #undef FF
721 #undef BOUNDS
722 #undef F
723 #undef FC
724
725 typedef struct {
726 uint64_t data;
727 } brw_compact_inst;
728
729 /**
730 * Fetch a set of contiguous bits from the compacted instruction.
731 *
732 * Bits indices range from 0..63.
733 */
734 static inline unsigned
735 brw_compact_inst_bits(brw_compact_inst *inst, unsigned high, unsigned low)
736 {
737 const uint64_t mask = (1ull << (high - low + 1)) - 1;
738
739 return (inst->data >> low) & mask;
740 }
741
742 /**
743 * Set bits in the compacted instruction.
744 *
745 * Bits indices range from 0..63.
746 */
747 static inline void
748 brw_compact_inst_set_bits(brw_compact_inst *inst, unsigned high, unsigned low,
749 uint64_t value)
750 {
751 const uint64_t mask = ((1ull << (high - low + 1)) - 1) << low;
752
753 /* Make sure the supplied value actually fits in the given bitfield. */
754 assert((value & (mask >> low)) == value);
755
756 inst->data = (inst->data & ~mask) | (value << low);
757 }
758
759 #define F(name, high, low) \
760 static inline void \
761 brw_compact_inst_set_##name(brw_compact_inst *inst, unsigned v) \
762 { \
763 brw_compact_inst_set_bits(inst, high, low, v); \
764 } \
765 \
766 static inline unsigned \
767 brw_compact_inst_##name(brw_compact_inst *inst) \
768 { \
769 return brw_compact_inst_bits(inst, high, low); \
770 }
771
772 F(src1_reg_nr, 63, 56)
773 F(src0_reg_nr, 55, 48)
774 F(dst_reg_nr, 47, 40)
775 F(src1_index, 39, 35)
776 F(src0_index, 34, 30)
777 F(cmpt_control, 29, 29) /* Same location as brw_inst */
778 F(flag_subreg_nr, 28, 28) /* <= Gen6 only */
779 F(cond_modifier, 27, 24) /* Same location as brw_inst */
780 F(acc_wr_control, 23, 23)
781 F(subreg_index, 22, 18)
782 F(datatype_index, 17, 13)
783 F(control_index, 12, 8)
784 F(debug_control, 7, 7)
785 F(opcode, 6, 0) /* Same location as brw_inst */
786
787 /**
788 * (Gen8+) Compacted three-source instructions:
789 * @{
790 */
791 F(3src_src2_reg_nr, 63, 57)
792 F(3src_src1_reg_nr, 56, 50)
793 F(3src_src0_reg_nr, 49, 43)
794 F(3src_src2_subreg_nr, 42, 40)
795 F(3src_src1_subreg_nr, 39, 37)
796 F(3src_src0_subreg_nr, 36, 34)
797 F(3src_src2_rep_ctrl, 33, 33)
798 F(3src_src1_rep_ctrl, 32, 32)
799 F(3src_saturate, 31, 31)
800 F(3src_debug_control, 30, 30)
801 F(3src_cmpt_control, 29, 29)
802 F(3src_src0_rep_ctrl, 28, 28)
803 /* Reserved */
804 F(3src_dst_reg_nr, 18, 12)
805 F(3src_source_index, 11, 10)
806 F(3src_control_index, 9, 8)
807 /* Bit 7 is Reserved (for future Opcode expansion) */
808 F(3src_opcode, 6, 0)
809 /** @} */
810
811 #undef F
812
813 #ifdef __cplusplus
814 }
815 #endif
816
817 #endif