src/mesa/drivers/dri/i965/brw_link.cpp

   1 /*
   2  * Copyright © 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "main/macros.h"
  25 #include "brw_context.h"
  26 #include "brw_vs.h"
  27 #include "brw_gs.h"
  28 #include "brw_fs.h"
  29 #include "brw_cfg.h"
  30 #include "brw_nir.h"
  31 #include "glsl/ir_optimization.h"
  32 #include "glsl/glsl_parser_extras.h"
  33 #include "main/shaderapi.h"
  34
  35 /**
  36  * Performs a compile of the shader stages even when we don't know
  37  * what non-orthogonal state will be set, in the hope that it reflects
  38  * the eventual NOS used, and thus allows us to produce link failures.
  39  */
  40 static bool
  41 brw_shader_precompile(struct gl_context *ctx,
  42                       struct gl_shader_program *sh_prog)
  43 {
  44    struct gl_shader *vs = sh_prog->_LinkedShaders[MESA_SHADER_VERTEX];
  45    struct gl_shader *gs = sh_prog->_LinkedShaders[MESA_SHADER_GEOMETRY];
  46    struct gl_shader *fs = sh_prog->_LinkedShaders[MESA_SHADER_FRAGMENT];
  47    struct gl_shader *cs = sh_prog->_LinkedShaders[MESA_SHADER_COMPUTE];
  48
  49    if (fs && !brw_fs_precompile(ctx, sh_prog, fs->Program))
  50       return false;
  51
  52    if (gs && !brw_gs_precompile(ctx, sh_prog, gs->Program))
  53       return false;
  54
  55    if (vs && !brw_vs_precompile(ctx, sh_prog, vs->Program))
  56       return false;
  57
  58    if (cs && !brw_cs_precompile(ctx, sh_prog, cs->Program))
  59       return false;
  60
  61    return true;
  62 }
  63
  64 static void
  65 brw_lower_packing_builtins(struct brw_context *brw,
  66                            gl_shader_stage shader_type,
  67                            exec_list *ir)
  68 {
  69    int ops = LOWER_PACK_SNORM_2x16
  70            | LOWER_UNPACK_SNORM_2x16
  71            | LOWER_PACK_UNORM_2x16
  72            | LOWER_UNPACK_UNORM_2x16;
  73
  74    if (is_scalar_shader_stage(brw->intelScreen->compiler, shader_type)) {
  75       ops |= LOWER_UNPACK_UNORM_4x8
  76            | LOWER_UNPACK_SNORM_4x8
  77            | LOWER_PACK_UNORM_4x8
  78            | LOWER_PACK_SNORM_4x8;
  79    }
  80
  81    if (brw->gen >= 7) {
  82       /* Gen7 introduced the f32to16 and f16to32 instructions, which can be
  83        * used to execute packHalf2x16 and unpackHalf2x16. For AOS code, no
  84        * lowering is needed. For SOA code, the Half2x16 ops must be
  85        * scalarized.
  86        */
  87       if (is_scalar_shader_stage(brw->intelScreen->compiler, shader_type)) {
  88          ops |= LOWER_PACK_HALF_2x16_TO_SPLIT
  89              |  LOWER_UNPACK_HALF_2x16_TO_SPLIT;
  90       }
  91    } else {
  92       ops |= LOWER_PACK_HALF_2x16
  93           |  LOWER_UNPACK_HALF_2x16;
  94    }
  95
  96    lower_packing_builtins(ir, ops);
  97 }
  98
  99 static void
 100 process_glsl_ir(gl_shader_stage stage,
 101                 struct brw_context *brw,
 102                 struct gl_shader_program *shader_prog,
 103                 struct gl_shader *shader)
 104 {
 105    struct gl_context *ctx = &brw->ctx;
 106    const struct gl_shader_compiler_options *options =
 107       &ctx->Const.ShaderCompilerOptions[shader->Stage];
 108
 109    /* Temporary memory context for any new IR. */
 110    void *mem_ctx = ralloc_context(NULL);
 111
 112    ralloc_adopt(mem_ctx, shader->ir);
 113
 114    /* lower_packing_builtins() inserts arithmetic instructions, so it
 115     * must precede lower_instructions().
 116     */
 117    brw_lower_packing_builtins(brw, shader->Stage, shader->ir);
 118    do_mat_op_to_vec(shader->ir);
 119    const int bitfield_insert = brw->gen >= 7 ? BITFIELD_INSERT_TO_BFM_BFI : 0;
 120    lower_instructions(shader->ir,
 121                       MOD_TO_FLOOR |
 122                       DIV_TO_MUL_RCP |
 123                       SUB_TO_ADD_NEG |
 124                       EXP_TO_EXP2 |
 125                       LOG_TO_LOG2 |
 126                       bitfield_insert |
 127                       LDEXP_TO_ARITH |
 128                       CARRY_TO_ARITH |
 129                       BORROW_TO_ARITH);
 130
 131    /* Pre-gen6 HW can only nest if-statements 16 deep.  Beyond this,
 132     * if-statements need to be flattened.
 133     */
 134    if (brw->gen < 6)
 135       lower_if_to_cond_assign(shader->ir, 16);
 136
 137    do_lower_texture_projection(shader->ir);
 138    brw_lower_texture_gradients(brw, shader->ir);
 139    do_vec_index_to_cond_assign(shader->ir);
 140    lower_vector_insert(shader->ir, true);
 141    lower_offset_arrays(shader->ir);
 142    brw_do_lower_unnormalized_offset(shader->ir);
 143    lower_noise(shader->ir);
 144    lower_quadop_vector(shader->ir, false);
 145
 146    bool lowered_variable_indexing =
 147       lower_variable_index_to_cond_assign((gl_shader_stage)stage,
 148                                           shader->ir,
 149                                           options->EmitNoIndirectInput,
 150                                           options->EmitNoIndirectOutput,
 151                                           options->EmitNoIndirectTemp,
 152                                           options->EmitNoIndirectUniform);
 153
 154    if (unlikely(brw->perf_debug && lowered_variable_indexing)) {
 155       perf_debug("Unsupported form of variable indexing in %s; falling "
 156                  "back to very inefficient code generation\n",
 157                  _mesa_shader_stage_to_abbrev(shader->Stage));
 158    }
 159
 160    lower_ubo_reference(shader);
 161
 162    bool progress;
 163    do {
 164       progress = false;
 165
 166       if (is_scalar_shader_stage(brw->intelScreen->compiler, shader->Stage)) {
 167          brw_do_channel_expressions(shader->ir);
 168          brw_do_vector_splitting(shader->ir);
 169       }
 170
 171       progress = do_lower_jumps(shader->ir, true, true,
 172                                 true, /* main return */
 173                                 false, /* continue */
 174                                 false /* loops */
 175                                 ) || progress;
 176
 177       progress = do_common_optimization(shader->ir, true, true,
 178                                         options, ctx->Const.NativeIntegers) || progress;
 179    } while (progress);
 180
 181    validate_ir_tree(shader->ir);
 182
 183    /* Now that we've finished altering the linked IR, reparent any live IR back
 184     * to the permanent memory context, and free the temporary one (discarding any
 185     * junk we optimized away).
 186     */
 187    reparent_ir(shader->ir, shader->ir);
 188    ralloc_free(mem_ctx);
 189
 190    if (ctx->_Shader->Flags & GLSL_DUMP) {
 191       fprintf(stderr, "\n");
 192       fprintf(stderr, "GLSL IR for linked %s program %d:\n",
 193               _mesa_shader_stage_to_string(shader->Stage),
 194               shader_prog->Name);
 195       _mesa_print_ir(stderr, shader->ir, NULL);
 196       fprintf(stderr, "\n");
 197    }
 198 }
 199
 200 GLboolean
 201 brw_link_shader(struct gl_context *ctx, struct gl_shader_program *shProg)
 202 {
 203    struct brw_context *brw = brw_context(ctx);
 204    const struct brw_compiler *compiler = brw->intelScreen->compiler;
 205    unsigned int stage;
 206
 207    for (stage = 0; stage < ARRAY_SIZE(shProg->_LinkedShaders); stage++) {
 208       struct gl_shader *shader = shProg->_LinkedShaders[stage];
 209       if (!shader)
 210          continue;
 211
 212       struct gl_program *prog =
 213          ctx->Driver.NewProgram(ctx, _mesa_shader_stage_to_program(stage),
 214                                 shader->Name);
 215       if (!prog)
 216         return false;
 217       prog->Parameters = _mesa_new_parameter_list();
 218
 219       _mesa_copy_linked_program_data((gl_shader_stage) stage, shProg, prog);
 220
 221       process_glsl_ir((gl_shader_stage) stage, brw, shProg, shader);
 222
 223       /* Make a pass over the IR to add state references for any built-in
 224        * uniforms that are used.  This has to be done now (during linking).
 225        * Code generation doesn't happen until the first time this shader is
 226        * used for rendering.  Waiting until then to generate the parameters is
 227        * too late.  At that point, the values for the built-in uniforms won't
 228        * get sent to the shader.
 229        */
 230       foreach_in_list(ir_instruction, node, shader->ir) {
 231          ir_variable *var = node->as_variable();
 232
 233          if ((var == NULL) || (var->data.mode != ir_var_uniform)
 234              || (strncmp(var->name, "gl_", 3) != 0))
 235             continue;
 236
 237          const ir_state_slot *const slots = var->get_state_slots();
 238          assert(slots != NULL);
 239
 240          for (unsigned int i = 0; i < var->get_num_state_slots(); i++) {
 241             _mesa_add_state_reference(prog->Parameters,
 242                                       (gl_state_index *) slots[i].tokens);
 243          }
 244       }
 245
 246       do_set_program_inouts(shader->ir, prog, shader->Stage);
 247
 248       prog->SamplersUsed = shader->active_samplers;
 249       prog->ShadowSamplers = shader->shadow_samplers;
 250       _mesa_update_shader_textures_used(shProg, prog);
 251
 252       _mesa_reference_program(ctx, &shader->Program, prog);
 253
 254       brw_add_texrect_params(prog);
 255
 256       prog->nir = brw_create_nir(brw, shProg, prog, (gl_shader_stage) stage,
 257                                  is_scalar_shader_stage(compiler, stage));
 258
 259       _mesa_reference_program(ctx, &prog, NULL);
 260    }
 261
 262    if ((ctx->_Shader->Flags & GLSL_DUMP) && shProg->Name != 0) {
 263       for (unsigned i = 0; i < shProg->NumShaders; i++) {
 264          const struct gl_shader *sh = shProg->Shaders[i];
 265          if (!sh)
 266             continue;
 267
 268          fprintf(stderr, "GLSL %s shader %d source for linked program %d:\n",
 269                  _mesa_shader_stage_to_string(sh->Stage),
 270                  i, shProg->Name);
 271          fprintf(stderr, "%s", sh->Source);
 272          fprintf(stderr, "\n");
 273       }
 274    }
 275
 276    if (brw->precompile && !brw_shader_precompile(ctx, shProg))
 277       return false;
 278
 279    return true;
 280 }