2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
34 #include "intel_batchbuffer.h"
35 #include "intel_fbo.h"
36 #include "intel_mipmap_tree.h"
38 #include "brw_context.h"
39 #include "brw_state.h"
40 #include "brw_defines.h"
42 #include "main/framebuffer.h"
43 #include "main/fbobject.h"
44 #include "main/glformats.h"
46 /* Constant single cliprect for framebuffer object or DRI2 drawing */
48 upload_drawing_rect(struct brw_context
*brw
)
50 struct gl_context
*ctx
= &brw
->ctx
;
51 const struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
52 const unsigned int fb_width
= _mesa_geometric_width(fb
);
53 const unsigned int fb_height
= _mesa_geometric_height(fb
);
56 OUT_BATCH(_3DSTATE_DRAWING_RECTANGLE
<< 16 | (4 - 2));
57 OUT_BATCH(0); /* xmin, ymin */
58 OUT_BATCH(((fb_width
- 1) & 0xffff) | ((fb_height
- 1) << 16));
63 const struct brw_tracked_state brw_drawing_rect
= {
66 .brw
= BRW_NEW_CONTEXT
,
68 .emit
= upload_drawing_rect
72 * Upload pointers to the per-stage state.
74 * The state pointers in this packet are all relative to the general state
75 * base address set by CMD_STATE_BASE_ADDRESS, which is 0.
78 upload_pipelined_state_pointers(struct brw_context
*brw
)
81 /* Need to flush before changing clip max threads for errata. */
88 OUT_BATCH(_3DSTATE_PIPELINED_POINTERS
<< 16 | (7 - 2));
89 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
90 brw
->vs
.base
.state_offset
);
91 if (brw
->ff_gs
.prog_active
)
92 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
93 brw
->ff_gs
.state_offset
| 1);
96 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
97 brw
->clip
.state_offset
| 1);
98 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
99 brw
->sf
.state_offset
);
100 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
101 brw
->wm
.base
.state_offset
);
102 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
103 brw
->cc
.state_offset
);
106 brw
->ctx
.NewDriverState
|= BRW_NEW_PSP
;
110 upload_psp_urb_cbs(struct brw_context
*brw
)
112 upload_pipelined_state_pointers(brw
);
113 brw_upload_urb_fence(brw
);
114 brw_upload_cs_urb_state(brw
);
117 const struct brw_tracked_state brw_psp_urb_cbs
= {
120 .brw
= BRW_NEW_BATCH
|
121 BRW_NEW_FF_GS_PROG_DATA
|
122 BRW_NEW_GEN4_UNIT_STATE
|
123 BRW_NEW_STATE_BASE_ADDRESS
|
126 .emit
= upload_psp_urb_cbs
,
130 brw_depthbuffer_format(struct brw_context
*brw
)
132 struct gl_context
*ctx
= &brw
->ctx
;
133 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
134 struct intel_renderbuffer
*drb
= intel_get_renderbuffer(fb
, BUFFER_DEPTH
);
135 struct intel_renderbuffer
*srb
;
138 (srb
= intel_get_renderbuffer(fb
, BUFFER_STENCIL
)) &&
139 !srb
->mt
->stencil_mt
&&
140 (intel_rb_format(srb
) == MESA_FORMAT_Z24_UNORM_S8_UINT
||
141 intel_rb_format(srb
) == MESA_FORMAT_Z32_FLOAT_S8X24_UINT
)) {
146 return BRW_DEPTHFORMAT_D32_FLOAT
;
148 return brw_depth_format(brw
, drb
->mt
->format
);
152 * Returns the mask of how many bits of x and y must be handled through the
153 * depthbuffer's draw offset x and y fields.
155 * The draw offset x/y field of the depthbuffer packet is unfortunately shared
156 * between the depth, hiz, and stencil buffers. Because it can be hard to get
157 * all 3 to agree on this value, we want to do as much drawing offset
158 * adjustment as possible by moving the base offset of the 3 buffers, which is
159 * restricted to tile boundaries.
161 * For each buffer, the remainder must be applied through the x/y draw offset.
162 * This returns the worst-case mask of the low bits that have to go into the
163 * packet. If the 3 buffers don't agree on the drawing offset ANDed with this
164 * mask, then we're in trouble.
167 brw_get_depthstencil_tile_masks(struct intel_mipmap_tree
*depth_mt
,
168 uint32_t depth_level
,
169 uint32_t depth_layer
,
170 struct intel_mipmap_tree
*stencil_mt
,
171 uint32_t *out_tile_mask_x
,
172 uint32_t *out_tile_mask_y
)
174 uint32_t tile_mask_x
= 0, tile_mask_y
= 0;
177 intel_miptree_get_tile_masks(depth_mt
, &tile_mask_x
, &tile_mask_y
, false);
179 if (intel_miptree_level_has_hiz(depth_mt
, depth_level
)) {
180 uint32_t hiz_tile_mask_x
, hiz_tile_mask_y
;
181 intel_miptree_get_tile_masks(depth_mt
->hiz_buf
->mt
,
182 &hiz_tile_mask_x
, &hiz_tile_mask_y
,
185 /* Each HiZ row represents 2 rows of pixels */
186 hiz_tile_mask_y
= hiz_tile_mask_y
<< 1 | 1;
188 tile_mask_x
|= hiz_tile_mask_x
;
189 tile_mask_y
|= hiz_tile_mask_y
;
194 if (stencil_mt
->stencil_mt
)
195 stencil_mt
= stencil_mt
->stencil_mt
;
197 if (stencil_mt
->format
== MESA_FORMAT_S_UINT8
) {
198 /* Separate stencil buffer uses 64x64 tiles. */
202 uint32_t stencil_tile_mask_x
, stencil_tile_mask_y
;
203 intel_miptree_get_tile_masks(stencil_mt
,
204 &stencil_tile_mask_x
,
205 &stencil_tile_mask_y
, false);
207 tile_mask_x
|= stencil_tile_mask_x
;
208 tile_mask_y
|= stencil_tile_mask_y
;
212 *out_tile_mask_x
= tile_mask_x
;
213 *out_tile_mask_y
= tile_mask_y
;
216 static struct intel_mipmap_tree
*
217 get_stencil_miptree(struct intel_renderbuffer
*irb
)
221 if (irb
->mt
->stencil_mt
)
222 return irb
->mt
->stencil_mt
;
227 brw_workaround_depthstencil_alignment(struct brw_context
*brw
,
228 GLbitfield clear_mask
)
230 struct gl_context
*ctx
= &brw
->ctx
;
231 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
232 bool rebase_depth
= false;
233 bool rebase_stencil
= false;
234 struct intel_renderbuffer
*depth_irb
= intel_get_renderbuffer(fb
, BUFFER_DEPTH
);
235 struct intel_renderbuffer
*stencil_irb
= intel_get_renderbuffer(fb
, BUFFER_STENCIL
);
236 struct intel_mipmap_tree
*depth_mt
= NULL
;
237 struct intel_mipmap_tree
*stencil_mt
= get_stencil_miptree(stencil_irb
);
238 uint32_t tile_x
= 0, tile_y
= 0, stencil_tile_x
= 0, stencil_tile_y
= 0;
239 uint32_t stencil_draw_x
= 0, stencil_draw_y
= 0;
240 bool invalidate_depth
= clear_mask
& BUFFER_BIT_DEPTH
;
241 bool invalidate_stencil
= clear_mask
& BUFFER_BIT_STENCIL
;
244 depth_mt
= depth_irb
->mt
;
246 /* Initialize brw->depthstencil to 'nop' workaround state.
248 brw
->depthstencil
.tile_x
= 0;
249 brw
->depthstencil
.tile_y
= 0;
250 brw
->depthstencil
.depth_offset
= 0;
251 brw
->depthstencil
.stencil_offset
= 0;
252 brw
->depthstencil
.hiz_offset
= 0;
253 brw
->depthstencil
.depth_mt
= NULL
;
254 brw
->depthstencil
.stencil_mt
= NULL
;
256 brw
->depthstencil
.depth_mt
= depth_mt
;
258 brw
->depthstencil
.stencil_mt
= get_stencil_miptree(stencil_irb
);
260 /* Gen6+ doesn't require the workarounds, since we always program the
261 * surface state at the start of the whole surface.
266 /* Check if depth buffer is in depth/stencil format. If so, then it's only
267 * safe to invalidate it if we're also clearing stencil, and both depth_irb
268 * and stencil_irb point to the same miptree.
270 * Note: it's not sufficient to check for the case where
271 * _mesa_get_format_base_format(depth_mt->format) == GL_DEPTH_STENCIL,
272 * because this fails to catch depth/stencil buffers on hardware that uses
273 * separate stencil. To catch that case, we check whether
274 * depth_mt->stencil_mt is non-NULL.
276 if (depth_irb
&& invalidate_depth
&&
277 (_mesa_get_format_base_format(depth_mt
->format
) == GL_DEPTH_STENCIL
||
278 depth_mt
->stencil_mt
)) {
279 invalidate_depth
= invalidate_stencil
&& depth_irb
&& stencil_irb
280 && depth_irb
->mt
== stencil_irb
->mt
;
283 uint32_t tile_mask_x
, tile_mask_y
;
284 brw_get_depthstencil_tile_masks(depth_mt
,
285 depth_mt
? depth_irb
->mt_level
: 0,
286 depth_mt
? depth_irb
->mt_layer
: 0,
288 &tile_mask_x
, &tile_mask_y
);
291 tile_x
= depth_irb
->draw_x
& tile_mask_x
;
292 tile_y
= depth_irb
->draw_y
& tile_mask_y
;
294 /* According to the Sandy Bridge PRM, volume 2 part 1, pp326-327
295 * (3DSTATE_DEPTH_BUFFER dw5), in the documentation for "Depth
296 * Coordinate Offset X/Y":
298 * "The 3 LSBs of both offsets must be zero to ensure correct
301 if (tile_x
& 7 || tile_y
& 7)
304 /* We didn't even have intra-tile offsets before g45. */
305 if (!brw
->has_surface_tile_offset
) {
306 if (tile_x
|| tile_y
)
311 perf_debug("HW workaround: blitting depth level %d to a temporary "
312 "to fix alignment (depth tile offset %d,%d)\n",
313 depth_irb
->mt_level
, tile_x
, tile_y
);
314 intel_renderbuffer_move_to_temp(brw
, depth_irb
, invalidate_depth
);
315 /* In the case of stencil_irb being the same packed depth/stencil
316 * texture but not the same rb, make it point at our rebased mt, too.
319 stencil_irb
!= depth_irb
&&
320 stencil_irb
->mt
== depth_mt
) {
321 intel_miptree_reference(&stencil_irb
->mt
, depth_irb
->mt
);
322 intel_renderbuffer_set_draw_offset(stencil_irb
);
325 stencil_mt
= get_stencil_miptree(stencil_irb
);
327 tile_x
= depth_irb
->draw_x
& tile_mask_x
;
328 tile_y
= depth_irb
->draw_y
& tile_mask_y
;
332 stencil_mt
= get_stencil_miptree(stencil_irb
);
333 intel_miptree_get_image_offset(stencil_mt
,
334 stencil_irb
->mt_level
,
335 stencil_irb
->mt_layer
,
336 &stencil_draw_x
, &stencil_draw_y
);
337 int stencil_tile_x
= stencil_draw_x
& tile_mask_x
;
338 int stencil_tile_y
= stencil_draw_y
& tile_mask_y
;
340 /* If stencil doesn't match depth, then we'll need to rebase stencil
341 * as well. (if we hadn't decided to rebase stencil before, the
342 * post-stencil depth test will also rebase depth to try to match it
345 if (tile_x
!= stencil_tile_x
||
346 tile_y
!= stencil_tile_y
) {
347 rebase_stencil
= true;
352 /* If we have (just) stencil, check it for ignored low bits as well */
354 intel_miptree_get_image_offset(stencil_mt
,
355 stencil_irb
->mt_level
,
356 stencil_irb
->mt_layer
,
357 &stencil_draw_x
, &stencil_draw_y
);
358 stencil_tile_x
= stencil_draw_x
& tile_mask_x
;
359 stencil_tile_y
= stencil_draw_y
& tile_mask_y
;
361 if (stencil_tile_x
& 7 || stencil_tile_y
& 7)
362 rebase_stencil
= true;
364 if (!brw
->has_surface_tile_offset
) {
365 if (stencil_tile_x
|| stencil_tile_y
)
366 rebase_stencil
= true;
370 if (rebase_stencil
) {
371 perf_debug("HW workaround: blitting stencil level %d to a temporary "
372 "to fix alignment (stencil tile offset %d,%d)\n",
373 stencil_irb
->mt_level
, stencil_tile_x
, stencil_tile_y
);
375 intel_renderbuffer_move_to_temp(brw
, stencil_irb
, invalidate_stencil
);
376 stencil_mt
= get_stencil_miptree(stencil_irb
);
378 intel_miptree_get_image_offset(stencil_mt
,
379 stencil_irb
->mt_level
,
380 stencil_irb
->mt_layer
,
381 &stencil_draw_x
, &stencil_draw_y
);
382 stencil_tile_x
= stencil_draw_x
& tile_mask_x
;
383 stencil_tile_y
= stencil_draw_y
& tile_mask_y
;
385 if (depth_irb
&& depth_irb
->mt
== stencil_irb
->mt
) {
386 intel_miptree_reference(&depth_irb
->mt
, stencil_irb
->mt
);
387 intel_renderbuffer_set_draw_offset(depth_irb
);
388 } else if (depth_irb
&& !rebase_depth
) {
389 if (tile_x
!= stencil_tile_x
||
390 tile_y
!= stencil_tile_y
) {
391 perf_debug("HW workaround: blitting depth level %d to a temporary "
392 "to match stencil level %d alignment (depth tile offset "
393 "%d,%d, stencil offset %d,%d)\n",
395 stencil_irb
->mt_level
,
397 stencil_tile_x
, stencil_tile_y
);
399 intel_renderbuffer_move_to_temp(brw
, depth_irb
, invalidate_depth
);
401 tile_x
= depth_irb
->draw_x
& tile_mask_x
;
402 tile_y
= depth_irb
->draw_y
& tile_mask_y
;
404 if (stencil_irb
&& stencil_irb
->mt
== depth_mt
) {
405 intel_miptree_reference(&stencil_irb
->mt
, depth_irb
->mt
);
406 intel_renderbuffer_set_draw_offset(stencil_irb
);
409 WARN_ONCE(stencil_tile_x
!= tile_x
||
410 stencil_tile_y
!= tile_y
,
411 "Rebased stencil tile offset (%d,%d) doesn't match depth "
412 "tile offset (%d,%d).\n",
413 stencil_tile_x
, stencil_tile_y
,
420 tile_x
= stencil_tile_x
;
421 tile_y
= stencil_tile_y
;
424 /* While we just tried to get everything aligned, we may have failed to do
425 * so in the case of rendering to array or 3D textures, where nonzero faces
426 * will still have an offset post-rebase. At least give an informative
429 WARN_ONCE((tile_x
& 7) || (tile_y
& 7),
430 "Depth/stencil buffer needs alignment to 8-pixel boundaries.\n"
431 "Truncating offset, bad rendering may occur.\n");
435 /* Now, after rebasing, save off the new dephtstencil state so the hardware
436 * packets can just dereference that without re-calculating tile offsets.
438 brw
->depthstencil
.tile_x
= tile_x
;
439 brw
->depthstencil
.tile_y
= tile_y
;
441 depth_mt
= depth_irb
->mt
;
442 brw
->depthstencil
.depth_mt
= depth_mt
;
443 brw
->depthstencil
.depth_offset
=
444 intel_miptree_get_aligned_offset(depth_mt
,
445 depth_irb
->draw_x
& ~tile_mask_x
,
446 depth_irb
->draw_y
& ~tile_mask_y
,
448 if (intel_renderbuffer_has_hiz(depth_irb
)) {
449 brw
->depthstencil
.hiz_offset
=
450 intel_miptree_get_aligned_offset(depth_mt
,
451 depth_irb
->draw_x
& ~tile_mask_x
,
452 (depth_irb
->draw_y
& ~tile_mask_y
) / 2,
457 stencil_mt
= get_stencil_miptree(stencil_irb
);
459 brw
->depthstencil
.stencil_mt
= stencil_mt
;
460 if (stencil_mt
->format
== MESA_FORMAT_S_UINT8
) {
461 /* Note: we can't compute the stencil offset using
462 * intel_region_get_aligned_offset(), because stencil_region claims
463 * that the region is untiled even though it's W tiled.
465 brw
->depthstencil
.stencil_offset
=
466 (stencil_draw_y
& ~tile_mask_y
) * stencil_mt
->pitch
+
467 (stencil_draw_x
& ~tile_mask_x
) * 64;
473 brw_emit_depthbuffer(struct brw_context
*brw
)
475 struct gl_context
*ctx
= &brw
->ctx
;
476 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
478 struct intel_renderbuffer
*depth_irb
= intel_get_renderbuffer(fb
, BUFFER_DEPTH
);
479 struct intel_renderbuffer
*stencil_irb
= intel_get_renderbuffer(fb
, BUFFER_STENCIL
);
480 struct intel_mipmap_tree
*depth_mt
= brw
->depthstencil
.depth_mt
;
481 struct intel_mipmap_tree
*stencil_mt
= brw
->depthstencil
.stencil_mt
;
482 uint32_t tile_x
= brw
->depthstencil
.tile_x
;
483 uint32_t tile_y
= brw
->depthstencil
.tile_y
;
484 bool hiz
= depth_irb
&& intel_renderbuffer_has_hiz(depth_irb
);
485 bool separate_stencil
= false;
486 uint32_t depth_surface_type
= BRW_SURFACE_NULL
;
487 uint32_t depthbuffer_format
= BRW_DEPTHFORMAT_D32_FLOAT
;
488 uint32_t depth_offset
= 0;
489 uint32_t width
= 1, height
= 1;
492 separate_stencil
= stencil_mt
->format
== MESA_FORMAT_S_UINT8
;
494 /* Gen7 supports only separate stencil */
495 assert(separate_stencil
|| brw
->gen
< 7);
498 /* If there's a packed depth/stencil bound to stencil only, we need to
499 * emit the packed depth/stencil buffer packet.
501 if (!depth_irb
&& stencil_irb
&& !separate_stencil
) {
502 depth_irb
= stencil_irb
;
503 depth_mt
= stencil_mt
;
506 if (depth_irb
&& depth_mt
) {
507 /* When 3DSTATE_DEPTH_BUFFER.Separate_Stencil_Enable is set, then
508 * 3DSTATE_DEPTH_BUFFER.Surface_Format is not permitted to be a packed
509 * depthstencil format.
511 * Gens prior to 7 require that HiZ_Enable and Separate_Stencil_Enable be
512 * set to the same value. Gens after 7 implicitly always set
513 * Separate_Stencil_Enable; software cannot disable it.
515 if ((brw
->gen
< 7 && hiz
) || brw
->gen
>= 7) {
516 assert(!_mesa_is_format_packed_depth_stencil(depth_mt
->format
));
519 /* Prior to Gen7, if using separate stencil, hiz must be enabled. */
520 assert(brw
->gen
>= 7 || !separate_stencil
|| hiz
);
522 assert(brw
->gen
< 6 || depth_mt
->tiling
== I915_TILING_Y
);
523 assert(!hiz
|| depth_mt
->tiling
== I915_TILING_Y
);
525 depthbuffer_format
= brw_depthbuffer_format(brw
);
526 depth_surface_type
= BRW_SURFACE_2D
;
527 depth_offset
= brw
->depthstencil
.depth_offset
;
528 width
= depth_irb
->Base
.Base
.Width
;
529 height
= depth_irb
->Base
.Base
.Height
;
530 } else if (separate_stencil
) {
532 * There exists a separate stencil buffer but no depth buffer.
534 * The stencil buffer inherits most of its fields from
535 * 3DSTATE_DEPTH_BUFFER: namely the tile walk, surface type, width, and
538 * The tiled bit must be set. From the Sandybridge PRM, Volume 2, Part 1,
539 * Section 7.5.5.1.1 3DSTATE_DEPTH_BUFFER, Bit 1.27 Tiled Surface:
540 * [DevGT+]: This field must be set to TRUE.
542 assert(brw
->has_separate_stencil
);
544 depth_surface_type
= BRW_SURFACE_2D
;
545 width
= stencil_irb
->Base
.Base
.Width
;
546 height
= stencil_irb
->Base
.Base
.Height
;
550 brw_render_cache_set_check_flush(brw
, depth_mt
->bo
);
552 brw_render_cache_set_check_flush(brw
, stencil_mt
->bo
);
554 brw
->vtbl
.emit_depth_stencil_hiz(brw
, depth_mt
, depth_offset
,
555 depthbuffer_format
, depth_surface_type
,
556 stencil_mt
, hiz
, separate_stencil
,
557 width
, height
, tile_x
, tile_y
);
561 brw_emit_depth_stencil_hiz(struct brw_context
*brw
,
562 struct intel_mipmap_tree
*depth_mt
,
563 uint32_t depth_offset
, uint32_t depthbuffer_format
,
564 uint32_t depth_surface_type
,
565 struct intel_mipmap_tree
*stencil_mt
,
566 bool hiz
, bool separate_stencil
,
567 uint32_t width
, uint32_t height
,
568 uint32_t tile_x
, uint32_t tile_y
)
570 /* Enable the hiz bit if we're doing separate stencil, because it and the
571 * separate stencil bit must have the same value. From Section 2.11.5.6.1.1
572 * 3DSTATE_DEPTH_BUFFER, Bit 1.21 "Separate Stencil Enable":
573 * [DevIL]: If this field is enabled, Hierarchical Depth Buffer
574 * Enable must also be enabled.
576 * [DevGT]: This field must be set to the same value (enabled or
577 * disabled) as Hierarchical Depth Buffer Enable
579 bool enable_hiz_ss
= hiz
|| separate_stencil
;
582 /* 3DSTATE_DEPTH_BUFFER, 3DSTATE_STENCIL_BUFFER are both
583 * non-pipelined state that will need the PIPE_CONTROL workaround.
586 brw_emit_depth_stall_flushes(brw
);
592 else if (brw
->is_g4x
|| brw
->gen
== 5)
598 OUT_BATCH(_3DSTATE_DEPTH_BUFFER
<< 16 | (len
- 2));
599 OUT_BATCH((depth_mt
? depth_mt
->pitch
- 1 : 0) |
600 (depthbuffer_format
<< 18) |
601 ((enable_hiz_ss
? 1 : 0) << 21) | /* separate stencil enable */
602 ((enable_hiz_ss
? 1 : 0) << 22) | /* hiz enable */
603 (BRW_TILEWALK_YMAJOR
<< 26) |
604 ((depth_mt
? depth_mt
->tiling
!= I915_TILING_NONE
: 1)
606 (depth_surface_type
<< 29));
609 OUT_RELOC(depth_mt
->bo
,
610 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
616 OUT_BATCH(((width
+ tile_x
- 1) << 6) |
617 ((height
+ tile_y
- 1) << 19));
620 if (brw
->is_g4x
|| brw
->gen
>= 5)
621 OUT_BATCH(tile_x
| (tile_y
<< 16));
623 assert(tile_x
== 0 && tile_y
== 0);
630 if (hiz
|| separate_stencil
) {
632 * In the 3DSTATE_DEPTH_BUFFER batch emitted above, the 'separate
633 * stencil enable' and 'hiz enable' bits were set. Therefore we must
634 * emit 3DSTATE_HIER_DEPTH_BUFFER and 3DSTATE_STENCIL_BUFFER. Even if
635 * there is no stencil buffer, 3DSTATE_STENCIL_BUFFER must be emitted;
636 * failure to do so causes hangs on gen5 and a stall on gen6.
639 /* Emit hiz buffer. */
641 struct intel_mipmap_tree
*hiz_mt
= depth_mt
->hiz_buf
->mt
;
643 OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER
<< 16) | (3 - 2));
644 OUT_BATCH(hiz_mt
->pitch
- 1);
645 OUT_RELOC(hiz_mt
->bo
,
646 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
647 brw
->depthstencil
.hiz_offset
);
651 OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER
<< 16) | (3 - 2));
657 /* Emit stencil buffer. */
658 if (separate_stencil
) {
660 OUT_BATCH((_3DSTATE_STENCIL_BUFFER
<< 16) | (3 - 2));
661 /* The stencil buffer has quirky pitch requirements. From Vol 2a,
662 * 11.5.6.2.1 3DSTATE_STENCIL_BUFFER, field "Surface Pitch":
663 * The pitch must be set to 2x the value computed based on width, as
664 * the stencil buffer is stored with two rows interleaved.
666 OUT_BATCH(2 * stencil_mt
->pitch
- 1);
667 OUT_RELOC(stencil_mt
->bo
,
668 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
669 brw
->depthstencil
.stencil_offset
);
673 OUT_BATCH((_3DSTATE_STENCIL_BUFFER
<< 16) | (3 - 2));
681 * On Gen >= 6, emit clear params for safety. If using hiz, then clear
682 * params must be emitted.
684 * From Section 2.11.5.6.4.1 3DSTATE_CLEAR_PARAMS:
685 * 3DSTATE_CLEAR_PARAMS packet must follow the DEPTH_BUFFER_STATE packet
686 * when HiZ is enabled and the DEPTH_BUFFER_STATE changes.
688 if (brw
->gen
>= 6 || hiz
) {
690 OUT_BATCH(_3DSTATE_CLEAR_PARAMS
<< 16 |
691 GEN5_DEPTH_CLEAR_VALID
|
693 OUT_BATCH(depth_mt
? depth_mt
->depth_clear_value
: 0);
698 const struct brw_tracked_state brw_depthbuffer
= {
700 .mesa
= _NEW_BUFFERS
,
701 .brw
= BRW_NEW_BATCH
,
703 .emit
= brw_emit_depthbuffer
,
707 * Polygon stipple packet
710 upload_polygon_stipple(struct brw_context
*brw
)
712 struct gl_context
*ctx
= &brw
->ctx
;
716 if (!ctx
->Polygon
.StippleFlag
)
720 OUT_BATCH(_3DSTATE_POLY_STIPPLE_PATTERN
<< 16 | (33 - 2));
722 /* Polygon stipple is provided in OpenGL order, i.e. bottom
723 * row first. If we're rendering to a window (i.e. the
724 * default frame buffer object, 0), then we need to invert
725 * it to match our pixel layout. But if we're rendering
726 * to a FBO (i.e. any named frame buffer object), we *don't*
727 * need to invert - we already match the layout.
729 if (_mesa_is_winsys_fbo(ctx
->DrawBuffer
)) {
730 for (i
= 0; i
< 32; i
++)
731 OUT_BATCH(ctx
->PolygonStipple
[31 - i
]); /* invert */
733 for (i
= 0; i
< 32; i
++)
734 OUT_BATCH(ctx
->PolygonStipple
[i
]);
739 const struct brw_tracked_state brw_polygon_stipple
= {
741 .mesa
= _NEW_POLYGON
|
743 .brw
= BRW_NEW_CONTEXT
,
745 .emit
= upload_polygon_stipple
749 * Polygon stipple offset packet
752 upload_polygon_stipple_offset(struct brw_context
*brw
)
754 struct gl_context
*ctx
= &brw
->ctx
;
757 if (!ctx
->Polygon
.StippleFlag
)
761 OUT_BATCH(_3DSTATE_POLY_STIPPLE_OFFSET
<< 16 | (2-2));
765 * If we're drawing to a system window we have to invert the Y axis
766 * in order to match the OpenGL pixel coordinate system, and our
767 * offset must be matched to the window position. If we're drawing
768 * to a user-created FBO then our native pixel coordinate system
769 * works just fine, and there's no window system to worry about.
771 if (_mesa_is_winsys_fbo(ctx
->DrawBuffer
))
772 OUT_BATCH((32 - (_mesa_geometric_height(ctx
->DrawBuffer
) & 31)) & 31);
778 const struct brw_tracked_state brw_polygon_stipple_offset
= {
780 .mesa
= _NEW_BUFFERS
|
782 .brw
= BRW_NEW_CONTEXT
,
784 .emit
= upload_polygon_stipple_offset
791 upload_aa_line_parameters(struct brw_context
*brw
)
793 struct gl_context
*ctx
= &brw
->ctx
;
795 if (!ctx
->Line
.SmoothFlag
)
798 /* Original Gen4 doesn't have 3DSTATE_AA_LINE_PARAMETERS. */
799 if (brw
->gen
== 4 && !brw
->is_g4x
)
803 OUT_BATCH(_3DSTATE_AA_LINE_PARAMETERS
<< 16 | (3 - 2));
804 /* use legacy aa line coverage computation */
810 const struct brw_tracked_state brw_aa_line_parameters
= {
813 .brw
= BRW_NEW_CONTEXT
,
815 .emit
= upload_aa_line_parameters
819 * Line stipple packet
822 upload_line_stipple(struct brw_context
*brw
)
824 struct gl_context
*ctx
= &brw
->ctx
;
828 if (!ctx
->Line
.StippleFlag
)
832 OUT_BATCH(_3DSTATE_LINE_STIPPLE_PATTERN
<< 16 | (3 - 2));
833 OUT_BATCH(ctx
->Line
.StipplePattern
);
837 tmp
= 1.0f
/ ctx
->Line
.StippleFactor
;
838 tmpi
= tmp
* (1<<16);
839 OUT_BATCH(tmpi
<< 15 | ctx
->Line
.StippleFactor
);
842 tmp
= 1.0f
/ ctx
->Line
.StippleFactor
;
843 tmpi
= tmp
* (1<<13);
844 OUT_BATCH(tmpi
<< 16 | ctx
->Line
.StippleFactor
);
850 const struct brw_tracked_state brw_line_stipple
= {
853 .brw
= BRW_NEW_CONTEXT
,
855 .emit
= upload_line_stipple
859 brw_emit_select_pipeline(struct brw_context
*brw
, enum brw_pipeline pipeline
)
861 const bool is_965
= brw
->gen
== 4 && !brw
->is_g4x
;
862 const uint32_t _3DSTATE_PIPELINE_SELECT
=
863 is_965
? CMD_PIPELINE_SELECT_965
: CMD_PIPELINE_SELECT_GM45
;
865 /* Select the pipeline */
867 OUT_BATCH(_3DSTATE_PIPELINE_SELECT
<< 16 |
868 (brw
->gen
>= 9 ? (3 << 8) : 0) |
869 (pipeline
== BRW_COMPUTE_PIPELINE
? 2 : 0));
874 * Misc invariant state packets
877 brw_upload_invariant_state(struct brw_context
*brw
)
879 const bool is_965
= brw
->gen
== 4 && !brw
->is_g4x
;
881 brw_emit_select_pipeline(brw
, BRW_RENDER_PIPELINE
);
882 brw
->last_pipeline
= BRW_RENDER_PIPELINE
;
885 /* Disable depth offset clamping. */
887 OUT_BATCH(_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP
<< 16 | (2 - 2));
894 OUT_BATCH(CMD_STATE_SIP
<< 16 | (3 - 2));
900 OUT_BATCH(CMD_STATE_SIP
<< 16 | (2 - 2));
905 const uint32_t _3DSTATE_VF_STATISTICS
=
906 is_965
? GEN4_3DSTATE_VF_STATISTICS
: GM45_3DSTATE_VF_STATISTICS
;
908 OUT_BATCH(_3DSTATE_VF_STATISTICS
<< 16 | 1);
912 const struct brw_tracked_state brw_invariant_state
= {
915 .brw
= BRW_NEW_CONTEXT
,
917 .emit
= brw_upload_invariant_state
921 * Define the base addresses which some state is referenced from.
923 * This allows us to avoid having to emit relocations for the objects,
924 * and is actually required for binding table pointers on gen6.
926 * Surface state base address covers binding table pointers and
927 * surface state objects, but not the surfaces that the surface state
931 upload_state_base_address(struct brw_context
*brw
)
933 /* FINISHME: According to section 3.6.1 "STATE_BASE_ADDRESS" of
934 * vol1a of the G45 PRM, MI_FLUSH with the ISC invalidate should be
935 * programmed prior to STATE_BASE_ADDRESS.
937 * However, given that the instruction SBA (general state base
938 * address) on this chipset is always set to 0 across X and GL,
939 * maybe this isn't required for us in particular.
943 uint8_t mocs
= brw
->gen
== 7 ? GEN7_MOCS_L3
: 0;
946 OUT_BATCH(CMD_STATE_BASE_ADDRESS
<< 16 | (10 - 2));
947 OUT_BATCH(mocs
<< 8 | /* General State Memory Object Control State */
948 mocs
<< 4 | /* Stateless Data Port Access Memory Object Control State */
949 1); /* General State Base Address Modify Enable */
950 /* Surface state base address:
951 * BINDING_TABLE_STATE
954 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_SAMPLER
, 0, 1);
955 /* Dynamic state base address:
957 * SAMPLER_BORDER_COLOR_STATE
958 * CLIP, SF, WM/CC viewport state
960 * DEPTH_STENCIL_STATE
962 * Push constants (when INSTPM: CONSTANT_BUFFER Address Offset
963 * Disable is clear, which we rely on)
965 OUT_RELOC(brw
->batch
.bo
, (I915_GEM_DOMAIN_RENDER
|
966 I915_GEM_DOMAIN_INSTRUCTION
), 0, 1);
968 OUT_BATCH(1); /* Indirect object base address: MEDIA_OBJECT data */
969 OUT_RELOC(brw
->cache
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
970 1); /* Instruction base address: shader kernels (incl. SIP) */
972 OUT_BATCH(1); /* General state upper bound */
973 /* Dynamic state upper bound. Although the documentation says that
974 * programming it to zero will cause it to be ignored, that is a lie.
975 * If this isn't programmed to a real bound, the sampler border color
976 * pointer is rejected, causing border color to mysteriously fail.
978 OUT_BATCH(0xfffff001);
979 OUT_BATCH(1); /* Indirect object upper bound */
980 OUT_BATCH(1); /* Instruction access upper bound */
982 } else if (brw
->gen
== 5) {
984 OUT_BATCH(CMD_STATE_BASE_ADDRESS
<< 16 | (8 - 2));
985 OUT_BATCH(1); /* General state base address */
986 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_SAMPLER
, 0,
987 1); /* Surface state base address */
988 OUT_BATCH(1); /* Indirect object base address */
989 OUT_RELOC(brw
->cache
.bo
, I915_GEM_DOMAIN_INSTRUCTION
, 0,
990 1); /* Instruction base address */
991 OUT_BATCH(0xfffff001); /* General state upper bound */
992 OUT_BATCH(1); /* Indirect object upper bound */
993 OUT_BATCH(1); /* Instruction access upper bound */
997 OUT_BATCH(CMD_STATE_BASE_ADDRESS
<< 16 | (6 - 2));
998 OUT_BATCH(1); /* General state base address */
999 OUT_RELOC(brw
->batch
.bo
, I915_GEM_DOMAIN_SAMPLER
, 0,
1000 1); /* Surface state base address */
1001 OUT_BATCH(1); /* Indirect object base address */
1002 OUT_BATCH(1); /* General state upper bound */
1003 OUT_BATCH(1); /* Indirect object upper bound */
1007 /* According to section 3.6.1 of VOL1 of the 965 PRM,
1008 * STATE_BASE_ADDRESS updates require a reissue of:
1010 * 3DSTATE_PIPELINE_POINTERS
1011 * 3DSTATE_BINDING_TABLE_POINTERS
1012 * MEDIA_STATE_POINTERS
1014 * and this continues through Ironlake. The Sandy Bridge PRM, vol
1015 * 1 part 1 says that the folowing packets must be reissued:
1017 * 3DSTATE_CC_POINTERS
1018 * 3DSTATE_BINDING_TABLE_POINTERS
1019 * 3DSTATE_SAMPLER_STATE_POINTERS
1020 * 3DSTATE_VIEWPORT_STATE_POINTERS
1021 * MEDIA_STATE_POINTERS
1023 * Those are always reissued following SBA updates anyway (new
1024 * batch time), except in the case of the program cache BO
1025 * changing. Having a separate state flag makes the sequence more
1029 brw
->ctx
.NewDriverState
|= BRW_NEW_STATE_BASE_ADDRESS
;
1032 const struct brw_tracked_state brw_state_base_address
= {
1035 .brw
= BRW_NEW_BATCH
|
1036 BRW_NEW_PROGRAM_CACHE
,
1038 .emit
= upload_state_base_address