src/mesa/drivers/dri/i965/brw_misc_state.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33
  34 #include "intel_batchbuffer.h"
  35 #include "intel_regions.h"
  36
  37 #include "brw_context.h"
  38 #include "brw_state.h"
  39 #include "brw_defines.h"
  40
  41
  42
  43
  44
  45 /***********************************************************************
  46  * Blend color
  47  */
  48
  49 static void upload_blend_constant_color(struct brw_context *brw)
  50 {
  51    GLcontext *ctx = &brw->intel.ctx;
  52    struct brw_blend_constant_color bcc;
  53
  54    memset(&bcc, 0, sizeof(bcc));
  55    bcc.header.opcode = CMD_BLEND_CONSTANT_COLOR;
  56    bcc.header.length = sizeof(bcc)/4-2;
  57    bcc.blend_constant_color[0] = ctx->Color.BlendColor[0];
  58    bcc.blend_constant_color[1] = ctx->Color.BlendColor[1];
  59    bcc.blend_constant_color[2] = ctx->Color.BlendColor[2];
  60    bcc.blend_constant_color[3] = ctx->Color.BlendColor[3];
  61
  62    BRW_CACHED_BATCH_STRUCT(brw, &bcc);
  63 }
  64
  65
  66 const struct brw_tracked_state brw_blend_constant_color = {
  67    .dirty = {
  68       .mesa = _NEW_COLOR,
  69       .brw = 0,
  70       .cache = 0
  71    },
  72    .emit = upload_blend_constant_color
  73 };
  74
  75 /* Constant single cliprect for framebuffer object or DRI2 drawing */
  76 static void upload_drawing_rect(struct brw_context *brw)
  77 {
  78    struct intel_context *intel = &brw->intel;
  79    GLcontext *ctx = &intel->ctx;
  80
  81    if (!intel->constant_cliprect)
  82       return;
  83
  84    BEGIN_BATCH(4, NO_LOOP_CLIPRECTS);
  85    OUT_BATCH(_3DSTATE_DRAWRECT_INFO_I965);
  86    OUT_BATCH(0); /* xmin, ymin */
  87    OUT_BATCH(((ctx->DrawBuffer->Width - 1) & 0xffff) |
  88             ((ctx->DrawBuffer->Height - 1) << 16));
  89    OUT_BATCH(0);
  90    ADVANCE_BATCH();
  91 }
  92
  93 const struct brw_tracked_state brw_drawing_rect = {
  94    .dirty = {
  95       .mesa = _NEW_BUFFERS,
  96       .brw = 0,
  97       .cache = 0
  98    },
  99    .emit = upload_drawing_rect
 100 };
 101
 102 static void prepare_binding_table_pointers(struct brw_context *brw)
 103 {
 104    brw_add_validated_bo(brw, brw->vs.bind_bo);
 105    brw_add_validated_bo(brw, brw->wm.bind_bo);
 106 }
 107
 108 /**
 109  * Upload the binding table pointers, which point each stage's array of surface
 110  * state pointers.
 111  *
 112  * The binding table pointers are relative to the surface state base address,
 113  * which is 0.
 114  */
 115 static void upload_binding_table_pointers(struct brw_context *brw)
 116 {
 117    struct intel_context *intel = &brw->intel;
 118
 119    BEGIN_BATCH(6, IGNORE_CLIPRECTS);
 120    OUT_BATCH(CMD_BINDING_TABLE_PTRS << 16 | (6 - 2));
 121    if (brw->vs.bind_bo != NULL)
 122       OUT_RELOC(brw->vs.bind_bo, I915_GEM_DOMAIN_SAMPLER, 0, 0); /* vs */
 123    else
 124       OUT_BATCH(0);
 125    OUT_BATCH(0); /* gs */
 126    OUT_BATCH(0); /* clip */
 127    OUT_BATCH(0); /* sf */
 128    OUT_RELOC(brw->wm.bind_bo, I915_GEM_DOMAIN_SAMPLER, 0, 0); /* wm/ps */
 129    ADVANCE_BATCH();
 130 }
 131
 132 const struct brw_tracked_state brw_binding_table_pointers = {
 133    .dirty = {
 134       .mesa = 0,
 135       .brw = BRW_NEW_BATCH,
 136       .cache = CACHE_NEW_SURF_BIND,
 137    },
 138    .prepare = prepare_binding_table_pointers,
 139    .emit = upload_binding_table_pointers,
 140 };
 141
 142
 143 /**
 144  * Upload pointers to the per-stage state.
 145  *
 146  * The state pointers in this packet are all relative to the general state
 147  * base address set by CMD_STATE_BASE_ADDRESS, which is 0.
 148  */
 149 static void upload_pipelined_state_pointers(struct brw_context *brw )
 150 {
 151    struct intel_context *intel = &brw->intel;
 152
 153    BEGIN_BATCH(7, IGNORE_CLIPRECTS);
 154    OUT_BATCH(CMD_PIPELINED_STATE_POINTERS << 16 | (7 - 2));
 155    OUT_RELOC(brw->vs.state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
 156    if (brw->gs.prog_active)
 157       OUT_RELOC(brw->gs.state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
 158    else
 159       OUT_BATCH(0);
 160    OUT_RELOC(brw->clip.state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
 161    OUT_RELOC(brw->sf.state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
 162    OUT_RELOC(brw->wm.state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
 163    OUT_RELOC(brw->cc.state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
 164    ADVANCE_BATCH();
 165
 166    brw->state.dirty.brw |= BRW_NEW_PSP;
 167 }
 168
 169
 170 static void prepare_psp_urb_cbs(struct brw_context *brw)
 171 {
 172    brw_add_validated_bo(brw, brw->vs.state_bo);
 173    brw_add_validated_bo(brw, brw->gs.state_bo);
 174    brw_add_validated_bo(brw, brw->clip.state_bo);
 175    brw_add_validated_bo(brw, brw->wm.state_bo);
 176    brw_add_validated_bo(brw, brw->cc.state_bo);
 177 }
 178
 179 static void upload_psp_urb_cbs(struct brw_context *brw )
 180 {
 181    upload_pipelined_state_pointers(brw);
 182    brw_upload_urb_fence(brw);
 183    brw_upload_cs_urb_state(brw);
 184 }
 185
 186 const struct brw_tracked_state brw_psp_urb_cbs = {
 187    .dirty = {
 188       .mesa = 0,
 189       .brw = BRW_NEW_URB_FENCE | BRW_NEW_BATCH,
 190       .cache = (CACHE_NEW_VS_UNIT |
 191                 CACHE_NEW_GS_UNIT |
 192                 CACHE_NEW_GS_PROG |
 193                 CACHE_NEW_CLIP_UNIT |
 194                 CACHE_NEW_SF_UNIT |
 195                 CACHE_NEW_WM_UNIT |
 196                 CACHE_NEW_CC_UNIT)
 197    },
 198    .prepare = prepare_psp_urb_cbs,
 199    .emit = upload_psp_urb_cbs,
 200 };
 201
 202 static void prepare_depthbuffer(struct brw_context *brw)
 203 {
 204    struct intel_region *region = brw->state.depth_region;
 205
 206    if (region != NULL)
 207       brw_add_validated_bo(brw, region->buffer);
 208 }
 209
 210 static void emit_depthbuffer(struct brw_context *brw)
 211 {
 212    struct intel_context *intel = &brw->intel;
 213    struct intel_region *region = brw->state.depth_region;
 214    unsigned int len = BRW_IS_G4X(brw) ? 6 : 5;
 215
 216    if (region == NULL) {
 217       BEGIN_BATCH(len, IGNORE_CLIPRECTS);
 218       OUT_BATCH(CMD_DEPTH_BUFFER << 16 | (len - 2));
 219       OUT_BATCH((BRW_DEPTHFORMAT_D32_FLOAT << 18) |
 220                 (BRW_SURFACE_NULL << 29));
 221       OUT_BATCH(0);
 222       OUT_BATCH(0);
 223       OUT_BATCH(0);
 224
 225       if (BRW_IS_G4X(brw))
 226          OUT_BATCH(0);
 227
 228       ADVANCE_BATCH();
 229    } else {
 230       unsigned int format;
 231
 232       switch (region->cpp) {
 233       case 2:
 234          format = BRW_DEPTHFORMAT_D16_UNORM;
 235          break;
 236       case 4:
 237          if (intel->depth_buffer_is_float)
 238             format = BRW_DEPTHFORMAT_D32_FLOAT;
 239          else
 240             format = BRW_DEPTHFORMAT_D24_UNORM_S8_UINT;
 241          break;
 242       default:
 243          assert(0);
 244          return;
 245       }
 246
 247       assert(region->tiling != I915_TILING_X);
 248
 249       BEGIN_BATCH(len, IGNORE_CLIPRECTS);
 250       OUT_BATCH(CMD_DEPTH_BUFFER << 16 | (len - 2));
 251       OUT_BATCH(((region->pitch * region->cpp) - 1) |
 252                 (format << 18) |
 253                 (BRW_TILEWALK_YMAJOR << 26) |
 254                 ((region->tiling != I915_TILING_NONE) << 27) |
 255                 (BRW_SURFACE_2D << 29));
 256       OUT_RELOC(region->buffer,
 257                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 258                 0);
 259       OUT_BATCH((BRW_SURFACE_MIPMAPLAYOUT_BELOW << 1) |
 260                 ((region->pitch - 1) << 6) |
 261                 ((region->height - 1) << 19));
 262       OUT_BATCH(0);
 263
 264       if (BRW_IS_G4X(brw))
 265          OUT_BATCH(0);
 266
 267       ADVANCE_BATCH();
 268    }
 269 }
 270
 271 const struct brw_tracked_state brw_depthbuffer = {
 272    .dirty = {
 273       .mesa = 0,
 274       .brw = BRW_NEW_DEPTH_BUFFER | BRW_NEW_BATCH,
 275       .cache = 0,
 276    },
 277    .prepare = prepare_depthbuffer,
 278    .emit = emit_depthbuffer,
 279 };
 280
 281
 282
 283 /***********************************************************************
 284  * Polygon stipple packet
 285  */
 286
 287 static void upload_polygon_stipple(struct brw_context *brw)
 288 {
 289    GLcontext *ctx = &brw->intel.ctx;
 290    struct brw_polygon_stipple bps;
 291    GLuint i;
 292
 293    memset(&bps, 0, sizeof(bps));
 294    bps.header.opcode = CMD_POLY_STIPPLE_PATTERN;
 295    bps.header.length = sizeof(bps)/4-2;
 296
 297    /* Polygon stipple is provided in OpenGL order, i.e. bottom
 298     * row first.  If we're rendering to a window (i.e. the
 299     * default frame buffer object, 0), then we need to invert
 300     * it to match our pixel layout.  But if we're rendering
 301     * to a FBO (i.e. any named frame buffer object), we *don't*
 302     * need to invert - we already match the layout.
 303     */
 304    if (ctx->DrawBuffer->Name == 0) {
 305       for (i = 0; i < 32; i++)
 306          bps.stipple[i] = ctx->PolygonStipple[31 - i]; /* invert */
 307    }
 308    else {
 309       for (i = 0; i < 32; i++)
 310          bps.stipple[i] = ctx->PolygonStipple[i]; /* don't invert */
 311    }
 312
 313    BRW_CACHED_BATCH_STRUCT(brw, &bps);
 314 }
 315
 316 const struct brw_tracked_state brw_polygon_stipple = {
 317    .dirty = {
 318       .mesa = _NEW_POLYGONSTIPPLE,
 319       .brw = 0,
 320       .cache = 0
 321    },
 322    .emit = upload_polygon_stipple
 323 };
 324
 325
 326 /***********************************************************************
 327  * Polygon stipple offset packet
 328  */
 329
 330 static void upload_polygon_stipple_offset(struct brw_context *brw)
 331 {
 332    __DRIdrawablePrivate *dPriv = brw->intel.driDrawable;
 333    struct brw_polygon_stipple_offset bpso;
 334
 335    memset(&bpso, 0, sizeof(bpso));
 336    bpso.header.opcode = CMD_POLY_STIPPLE_OFFSET;
 337    bpso.header.length = sizeof(bpso)/4-2;
 338
 339    /* If we're drawing to a system window (ctx->DrawBuffer->Name == 0),
 340     * we have to invert the Y axis in order to match the OpenGL
 341     * pixel coordinate system, and our offset must be matched
 342     * to the window position.  If we're drawing to a FBO
 343     * (ctx->DrawBuffer->Name != 0), then our native pixel coordinate
 344     * system works just fine, and there's no window system to
 345     * worry about.
 346     */
 347    if (brw->intel.ctx.DrawBuffer->Name == 0) {
 348       bpso.bits0.x_offset = (32 - (dPriv->x & 31)) & 31;
 349       bpso.bits0.y_offset = (32 - ((dPriv->y + dPriv->h) & 31)) & 31;
 350    }
 351    else {
 352       bpso.bits0.y_offset = 0;
 353       bpso.bits0.x_offset = 0;
 354    }
 355
 356    BRW_CACHED_BATCH_STRUCT(brw, &bpso);
 357 }
 358
 359 #define _NEW_WINDOW_POS 0x40000000
 360
 361 const struct brw_tracked_state brw_polygon_stipple_offset = {
 362    .dirty = {
 363       .mesa = _NEW_WINDOW_POS,
 364       .brw = 0,
 365       .cache = 0
 366    },
 367    .emit = upload_polygon_stipple_offset
 368 };
 369
 370 /**********************************************************************
 371  * AA Line parameters
 372  */
 373 static void upload_aa_line_parameters(struct brw_context *brw)
 374 {
 375    struct brw_aa_line_parameters balp;
 376
 377    if (!BRW_IS_G4X(brw))
 378       return;
 379
 380    /* use legacy aa line coverage computation */
 381    memset(&balp, 0, sizeof(balp));
 382    balp.header.opcode = CMD_AA_LINE_PARAMETERS;
 383    balp.header.length = sizeof(balp) / 4 - 2;
 384
 385    BRW_CACHED_BATCH_STRUCT(brw, &balp);
 386 }
 387
 388 const struct brw_tracked_state brw_aa_line_parameters = {
 389    .dirty = {
 390       .mesa = 0,
 391       .brw = BRW_NEW_CONTEXT,
 392       .cache = 0
 393    },
 394    .emit = upload_aa_line_parameters
 395 };
 396
 397 /***********************************************************************
 398  * Line stipple packet
 399  */
 400
 401 static void upload_line_stipple(struct brw_context *brw)
 402 {
 403    GLcontext *ctx = &brw->intel.ctx;
 404    struct brw_line_stipple bls;
 405    GLfloat tmp;
 406    GLint tmpi;
 407
 408    memset(&bls, 0, sizeof(bls));
 409    bls.header.opcode = CMD_LINE_STIPPLE_PATTERN;
 410    bls.header.length = sizeof(bls)/4 - 2;
 411
 412    bls.bits0.pattern = ctx->Line.StipplePattern;
 413    bls.bits1.repeat_count = ctx->Line.StippleFactor;
 414
 415    tmp = 1.0 / (GLfloat) ctx->Line.StippleFactor;
 416    tmpi = tmp * (1<<13);
 417
 418
 419    bls.bits1.inverse_repeat_count = tmpi;
 420
 421    BRW_CACHED_BATCH_STRUCT(brw, &bls);
 422 }
 423
 424 const struct brw_tracked_state brw_line_stipple = {
 425    .dirty = {
 426       .mesa = _NEW_LINE,
 427       .brw = 0,
 428       .cache = 0
 429    },
 430    .emit = upload_line_stipple
 431 };
 432
 433
 434 /***********************************************************************
 435  * Misc invarient state packets
 436  */
 437
 438 static void upload_invarient_state( struct brw_context *brw )
 439 {
 440    {
 441       /* 0x61040000  Pipeline Select */
 442       /*     PipelineSelect            : 0 */
 443       struct brw_pipeline_select ps;
 444
 445       memset(&ps, 0, sizeof(ps));
 446       ps.header.opcode = CMD_PIPELINE_SELECT(brw);
 447       ps.header.pipeline_select = 0;
 448       BRW_BATCH_STRUCT(brw, &ps);
 449    }
 450
 451    {
 452       struct brw_global_depth_offset_clamp gdo;
 453       memset(&gdo, 0, sizeof(gdo));
 454
 455       /* Disable depth offset clamping.
 456        */
 457       gdo.header.opcode = CMD_GLOBAL_DEPTH_OFFSET_CLAMP;
 458       gdo.header.length = sizeof(gdo)/4 - 2;
 459       gdo.depth_offset_clamp = 0.0;
 460
 461       BRW_BATCH_STRUCT(brw, &gdo);
 462    }
 463
 464
 465    /* 0x61020000  State Instruction Pointer */
 466    {
 467       struct brw_system_instruction_pointer sip;
 468       memset(&sip, 0, sizeof(sip));
 469
 470       sip.header.opcode = CMD_STATE_INSN_POINTER;
 471       sip.header.length = 0;
 472       sip.bits0.pad = 0;
 473       sip.bits0.system_instruction_pointer = 0;
 474       BRW_BATCH_STRUCT(brw, &sip);
 475    }
 476
 477
 478    {
 479       struct brw_vf_statistics vfs;
 480       memset(&vfs, 0, sizeof(vfs));
 481
 482       vfs.opcode = CMD_VF_STATISTICS(brw);
 483       if (INTEL_DEBUG & DEBUG_STATS)
 484          vfs.statistics_enable = 1;
 485
 486       BRW_BATCH_STRUCT(brw, &vfs);
 487    }
 488 }
 489
 490 const struct brw_tracked_state brw_invarient_state = {
 491    .dirty = {
 492       .mesa = 0,
 493       .brw = BRW_NEW_CONTEXT,
 494       .cache = 0
 495    },
 496    .emit = upload_invarient_state
 497 };
 498
 499 /**
 500  * Define the base addresses which some state is referenced from.
 501  *
 502  * This allows us to avoid having to emit relocations in many places for
 503  * cached state, and instead emit pointers inside of large, mostly-static
 504  * state pools.  This comes at the expense of memory, and more expensive cache
 505  * misses.
 506  */
 507 static void upload_state_base_address( struct brw_context *brw )
 508 {
 509    struct intel_context *intel = &brw->intel;
 510
 511    /* Output the structure (brw_state_base_address) directly to the
 512     * batchbuffer, so we can emit relocations inline.
 513     */
 514    BEGIN_BATCH(6, IGNORE_CLIPRECTS);
 515    OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (6 - 2));
 516    OUT_BATCH(1); /* General state base address */
 517    OUT_BATCH(1); /* Surface state base address */
 518    OUT_BATCH(1); /* Indirect object base address */
 519    OUT_BATCH(1); /* General state upper bound */
 520    OUT_BATCH(1); /* Indirect object upper bound */
 521    ADVANCE_BATCH();
 522 }
 523
 524 const struct brw_tracked_state brw_state_base_address = {
 525    .dirty = {
 526       .mesa = 0,
 527       .brw = BRW_NEW_CONTEXT,
 528       .cache = 0,
 529    },
 530    .emit = upload_state_base_address
 531 };