i965/nir: Disable alu_to_scalar pass on non-scalar shaders
[mesa.git] / src / mesa / drivers / dri / i965 / brw_nir.c
1 /*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "brw_nir.h"
25 #include "glsl/glsl_parser_extras.h"
26 #include "glsl/nir/glsl_to_nir.h"
27 #include "program/prog_to_nir.h"
28
29 static void
30 nir_optimize(nir_shader *nir, bool is_scalar)
31 {
32 bool progress;
33 do {
34 progress = false;
35 nir_lower_vars_to_ssa(nir);
36 nir_validate_shader(nir);
37
38 if (is_scalar) {
39 nir_lower_alu_to_scalar(nir);
40 nir_validate_shader(nir);
41 }
42
43 progress |= nir_copy_prop(nir);
44 nir_validate_shader(nir);
45 nir_lower_phis_to_scalar(nir);
46 nir_validate_shader(nir);
47 progress |= nir_copy_prop(nir);
48 nir_validate_shader(nir);
49 progress |= nir_opt_dce(nir);
50 nir_validate_shader(nir);
51 progress |= nir_opt_cse(nir);
52 nir_validate_shader(nir);
53 progress |= nir_opt_peephole_select(nir);
54 nir_validate_shader(nir);
55 progress |= nir_opt_algebraic(nir);
56 nir_validate_shader(nir);
57 progress |= nir_opt_constant_folding(nir);
58 nir_validate_shader(nir);
59 progress |= nir_opt_remove_phis(nir);
60 nir_validate_shader(nir);
61 } while (progress);
62 }
63
64 nir_shader *
65 brw_create_nir(struct brw_context *brw,
66 const struct gl_shader_program *shader_prog,
67 const struct gl_program *prog,
68 gl_shader_stage stage,
69 bool is_scalar)
70 {
71 struct gl_context *ctx = &brw->ctx;
72 const nir_shader_compiler_options *options =
73 ctx->Const.ShaderCompilerOptions[stage].NirOptions;
74 struct gl_shader *shader = shader_prog ? shader_prog->_LinkedShaders[stage] : NULL;
75 bool debug_enabled = INTEL_DEBUG & intel_debug_flag_for_shader_stage(stage);
76 nir_shader *nir;
77
78 /* First, lower the GLSL IR or Mesa IR to NIR */
79 if (shader_prog) {
80 nir = glsl_to_nir(shader, options);
81 } else {
82 nir = prog_to_nir(prog, options);
83 nir_convert_to_ssa(nir); /* turn registers into SSA */
84 }
85 nir_validate_shader(nir);
86
87 nir_lower_global_vars_to_local(nir);
88 nir_validate_shader(nir);
89
90 nir_lower_tex_projector(nir);
91 nir_validate_shader(nir);
92
93 nir_normalize_cubemap_coords(nir);
94 nir_validate_shader(nir);
95
96 nir_split_var_copies(nir);
97 nir_validate_shader(nir);
98
99 nir_optimize(nir, is_scalar);
100
101 /* Lower a bunch of stuff */
102 nir_lower_var_copies(nir);
103 nir_validate_shader(nir);
104
105 /* Get rid of split copies */
106 nir_optimize(nir, is_scalar);
107
108 if (is_scalar) {
109 nir_assign_var_locations_direct_first(nir, &nir->uniforms,
110 &nir->num_direct_uniforms,
111 &nir->num_uniforms,
112 is_scalar);
113 nir_assign_var_locations(&nir->outputs, &nir->num_outputs, is_scalar);
114 } else {
115 nir_assign_var_locations(&nir->uniforms,
116 &nir->num_uniforms,
117 is_scalar);
118
119 foreach_list_typed(nir_variable, var, node, &nir->outputs)
120 var->data.driver_location = var->data.location;
121 }
122 nir_assign_var_locations(&nir->inputs, &nir->num_inputs, is_scalar);
123
124 nir_lower_io(nir, is_scalar);
125
126 nir_validate_shader(nir);
127
128 nir_remove_dead_variables(nir);
129 nir_validate_shader(nir);
130
131 if (shader_prog) {
132 nir_lower_samplers(nir, shader_prog, stage);
133 nir_validate_shader(nir);
134 }
135
136 nir_lower_system_values(nir);
137 nir_validate_shader(nir);
138
139 nir_lower_atomics(nir);
140 nir_validate_shader(nir);
141
142 nir_optimize(nir, is_scalar);
143
144 if (brw->gen >= 6) {
145 /* Try and fuse multiply-adds */
146 nir_opt_peephole_ffma(nir);
147 nir_validate_shader(nir);
148 }
149
150 nir_opt_algebraic_late(nir);
151 nir_validate_shader(nir);
152
153 nir_lower_locals_to_regs(nir);
154 nir_validate_shader(nir);
155
156 nir_lower_to_source_mods(nir);
157 nir_validate_shader(nir);
158 nir_copy_prop(nir);
159 nir_validate_shader(nir);
160 nir_opt_dce(nir);
161 nir_validate_shader(nir);
162
163 if (unlikely(debug_enabled)) {
164 /* Re-index SSA defs so we print more sensible numbers. */
165 nir_foreach_overload(nir, overload) {
166 if (overload->impl)
167 nir_index_ssa_defs(overload->impl);
168 }
169
170 fprintf(stderr, "NIR (SSA form) for %s shader:\n",
171 _mesa_shader_stage_to_string(stage));
172 nir_print_shader(nir, stderr);
173 }
174
175 nir_convert_from_ssa(nir, is_scalar);
176 nir_validate_shader(nir);
177
178 /* This is the last pass we run before we start emitting stuff. It
179 * determines when we need to insert boolean resolves on Gen <= 5. We
180 * run it last because it stashes data in instr->pass_flags and we don't
181 * want that to be squashed by other NIR passes.
182 */
183 if (brw->gen <= 5)
184 brw_nir_analyze_boolean_resolves(nir);
185
186 nir_sweep(nir);
187
188 if (unlikely(debug_enabled)) {
189 fprintf(stderr, "NIR (final form) for %s shader:\n",
190 _mesa_shader_stage_to_string(stage));
191 nir_print_shader(nir, stderr);
192 }
193
194 return nir;
195 }
196
197 enum brw_reg_type
198 brw_type_for_nir_type(nir_alu_type type)
199 {
200 switch (type) {
201 case nir_type_unsigned:
202 return BRW_REGISTER_TYPE_UD;
203 case nir_type_bool:
204 case nir_type_int:
205 return BRW_REGISTER_TYPE_D;
206 case nir_type_float:
207 return BRW_REGISTER_TYPE_F;
208 default:
209 unreachable("unknown type");
210 }
211
212 return BRW_REGISTER_TYPE_F;
213 }