Merge branch 'mesa_7_5_branch' into mesa_7_6_branch
[mesa.git] / src / mesa / drivers / dri / i965 / brw_sf_state.c
1 /*
2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
5
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
13
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
17
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25
26 **********************************************************************/
27 /*
28 * Authors:
29 * Keith Whitwell <keith@tungstengraphics.com>
30 */
31
32
33
34 #include "brw_context.h"
35 #include "brw_state.h"
36 #include "brw_defines.h"
37 #include "main/macros.h"
38 #include "intel_fbo.h"
39
40 static void upload_sf_vp(struct brw_context *brw)
41 {
42 GLcontext *ctx = &brw->intel.ctx;
43 const GLfloat depth_scale = 1.0F / ctx->DrawBuffer->_DepthMaxF;
44 struct brw_sf_viewport sfv;
45 GLfloat y_scale, y_bias;
46 const GLboolean render_to_fbo = (ctx->DrawBuffer->Name != 0);
47 const GLfloat *v = ctx->Viewport._WindowMap.m;
48
49 memset(&sfv, 0, sizeof(sfv));
50
51 if (render_to_fbo) {
52 y_scale = 1.0;
53 y_bias = 0;
54 }
55 else {
56 y_scale = -1.0;
57 y_bias = ctx->DrawBuffer->Height;
58 }
59
60 /* _NEW_VIEWPORT */
61
62 sfv.viewport.m00 = v[MAT_SX];
63 sfv.viewport.m11 = v[MAT_SY] * y_scale;
64 sfv.viewport.m22 = v[MAT_SZ] * depth_scale;
65 sfv.viewport.m30 = v[MAT_TX];
66 sfv.viewport.m31 = v[MAT_TY] * y_scale + y_bias;
67 sfv.viewport.m32 = v[MAT_TZ] * depth_scale;
68
69 /* _NEW_SCISSOR | _NEW_BUFFERS | _NEW_VIEWPORT
70 * for DrawBuffer->_[XY]{min,max}
71 */
72
73 /* The scissor only needs to handle the intersection of drawable and
74 * scissor rect. Clipping to the boundaries of static shared buffers
75 * for front/back/depth is covered by looping over cliprects in brw_draw.c.
76 *
77 * Note that the hardware's coordinates are inclusive, while Mesa's min is
78 * inclusive but max is exclusive.
79 */
80 if (render_to_fbo) {
81 /* texmemory: Y=0=bottom */
82 sfv.scissor.xmin = ctx->DrawBuffer->_Xmin;
83 sfv.scissor.xmax = ctx->DrawBuffer->_Xmax - 1;
84 sfv.scissor.ymin = ctx->DrawBuffer->_Ymin;
85 sfv.scissor.ymax = ctx->DrawBuffer->_Ymax - 1;
86 }
87 else {
88 /* memory: Y=0=top */
89 sfv.scissor.xmin = ctx->DrawBuffer->_Xmin;
90 sfv.scissor.xmax = ctx->DrawBuffer->_Xmax - 1;
91 sfv.scissor.ymin = ctx->DrawBuffer->Height - ctx->DrawBuffer->_Ymax;
92 sfv.scissor.ymax = ctx->DrawBuffer->Height - ctx->DrawBuffer->_Ymin - 1;
93 }
94
95 dri_bo_unreference(brw->sf.vp_bo);
96 brw->sf.vp_bo = brw_cache_data( &brw->cache, BRW_SF_VP, &sfv, NULL, 0 );
97 }
98
99 const struct brw_tracked_state brw_sf_vp = {
100 .dirty = {
101 .mesa = (_NEW_VIEWPORT |
102 _NEW_SCISSOR |
103 _NEW_BUFFERS),
104 .brw = 0,
105 .cache = 0
106 },
107 .prepare = upload_sf_vp
108 };
109
110 struct brw_sf_unit_key {
111 unsigned int total_grf;
112 unsigned int urb_entry_read_length;
113
114 unsigned int nr_urb_entries, urb_size, sfsize;
115
116 GLenum front_face, cull_face, provoking_vertex;
117 unsigned scissor:1;
118 unsigned line_smooth:1;
119 unsigned point_sprite:1;
120 unsigned point_attenuated:1;
121 unsigned render_to_fbo:1;
122 float line_width;
123 float point_size;
124 };
125
126 static void
127 sf_unit_populate_key(struct brw_context *brw, struct brw_sf_unit_key *key)
128 {
129 GLcontext *ctx = &brw->intel.ctx;
130 memset(key, 0, sizeof(*key));
131
132 /* CACHE_NEW_SF_PROG */
133 key->total_grf = brw->sf.prog_data->total_grf;
134 key->urb_entry_read_length = brw->sf.prog_data->urb_read_length;
135
136 /* BRW_NEW_URB_FENCE */
137 key->nr_urb_entries = brw->urb.nr_sf_entries;
138 key->urb_size = brw->urb.vsize;
139 key->sfsize = brw->urb.sfsize;
140
141 key->scissor = ctx->Scissor.Enabled;
142 key->front_face = ctx->Polygon.FrontFace;
143
144 if (ctx->Polygon.CullFlag)
145 key->cull_face = ctx->Polygon.CullFaceMode;
146 else
147 key->cull_face = GL_NONE;
148
149 key->line_width = ctx->Line.Width;
150 key->line_smooth = ctx->Line.SmoothFlag;
151
152 key->point_sprite = ctx->Point.PointSprite;
153 key->point_size = CLAMP(ctx->Point.Size, ctx->Point.MinSize, ctx->Point.MaxSize);
154 key->point_attenuated = ctx->Point._Attenuated;
155
156 /* _NEW_LIGHT */
157 key->provoking_vertex = ctx->Light.ProvokingVertex;
158
159 key->render_to_fbo = brw->intel.ctx.DrawBuffer->Name != 0;
160 }
161
162 static dri_bo *
163 sf_unit_create_from_key(struct brw_context *brw, struct brw_sf_unit_key *key,
164 dri_bo **reloc_bufs)
165 {
166 struct brw_sf_unit_state sf;
167 dri_bo *bo;
168 int chipset_max_threads;
169 memset(&sf, 0, sizeof(sf));
170
171 sf.thread0.grf_reg_count = ALIGN(key->total_grf, 16) / 16 - 1;
172 sf.thread0.kernel_start_pointer = brw->sf.prog_bo->offset >> 6; /* reloc */
173
174 sf.thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754;
175
176 sf.thread3.dispatch_grf_start_reg = 3;
177
178 if (BRW_IS_IGDNG(brw))
179 sf.thread3.urb_entry_read_offset = 3;
180 else
181 sf.thread3.urb_entry_read_offset = 1;
182
183 sf.thread3.urb_entry_read_length = key->urb_entry_read_length;
184
185 sf.thread4.nr_urb_entries = key->nr_urb_entries;
186 sf.thread4.urb_entry_allocation_size = key->sfsize - 1;
187
188 /* Each SF thread produces 1 PUE, and there can be up to 24(Pre-IGDNG) or
189 * 48(IGDNG) threads
190 */
191 if (BRW_IS_IGDNG(brw))
192 chipset_max_threads = 48;
193 else
194 chipset_max_threads = 24;
195
196 sf.thread4.max_threads = MIN2(chipset_max_threads, key->nr_urb_entries) - 1;
197
198 if (INTEL_DEBUG & DEBUG_SINGLE_THREAD)
199 sf.thread4.max_threads = 0;
200
201 if (INTEL_DEBUG & DEBUG_STATS)
202 sf.thread4.stats_enable = 1;
203
204 /* CACHE_NEW_SF_VP */
205 sf.sf5.sf_viewport_state_offset = brw->sf.vp_bo->offset >> 5; /* reloc */
206
207 sf.sf5.viewport_transform = 1;
208
209 /* _NEW_SCISSOR */
210 if (key->scissor)
211 sf.sf6.scissor = 1;
212
213 /* _NEW_POLYGON */
214 if (key->front_face == GL_CCW)
215 sf.sf5.front_winding = BRW_FRONTWINDING_CCW;
216 else
217 sf.sf5.front_winding = BRW_FRONTWINDING_CW;
218
219 /* The viewport is inverted for rendering to a FBO, and that inverts
220 * polygon front/back orientation.
221 */
222 sf.sf5.front_winding ^= key->render_to_fbo;
223
224 switch (key->cull_face) {
225 case GL_FRONT:
226 sf.sf6.cull_mode = BRW_CULLMODE_FRONT;
227 break;
228 case GL_BACK:
229 sf.sf6.cull_mode = BRW_CULLMODE_BACK;
230 break;
231 case GL_FRONT_AND_BACK:
232 sf.sf6.cull_mode = BRW_CULLMODE_BOTH;
233 break;
234 case GL_NONE:
235 sf.sf6.cull_mode = BRW_CULLMODE_NONE;
236 break;
237 default:
238 assert(0);
239 break;
240 }
241
242 /* _NEW_LINE */
243 /* XXX use ctx->Const.Min/MaxLineWidth here */
244 sf.sf6.line_width = CLAMP(key->line_width, 1.0, 5.0) * (1<<1);
245
246 sf.sf6.line_endcap_aa_region_width = 1;
247 if (key->line_smooth)
248 sf.sf6.aa_enable = 1;
249 else if (sf.sf6.line_width <= 0x2)
250 sf.sf6.line_width = 0;
251
252 /* _NEW_BUFFERS */
253 key->render_to_fbo = brw->intel.ctx.DrawBuffer->Name != 0;
254 if (!key->render_to_fbo) {
255 /* Rendering to an OpenGL window */
256 sf.sf6.point_rast_rule = BRW_RASTRULE_UPPER_RIGHT;
257 }
258 else {
259 /* If rendering to an FBO, the pixel coordinate system is
260 * inverted with respect to the normal OpenGL coordinate
261 * system, so BRW_RASTRULE_LOWER_RIGHT is correct.
262 * But this value is listed as "Reserved, but not seen as useful"
263 * in Intel documentation (page 212, "Point Rasterization Rule",
264 * section 7.4 "SF Pipeline State Summary", of document
265 * "IntelĀ® 965 Express Chipset Family and IntelĀ® G35 Express
266 * Chipset Graphics Controller Programmer's Reference Manual,
267 * Volume 2: 3D/Media", Revision 1.0b as of January 2008,
268 * available at
269 * http://intellinuxgraphics.org/documentation.html
270 * at the time of this writing).
271 *
272 * It does work on at least some devices, if not all;
273 * if devices that don't support it can be identified,
274 * the likely failure case is that points are rasterized
275 * incorrectly, which is no worse than occurs without
276 * the value, so we're using it here.
277 */
278 sf.sf6.point_rast_rule = BRW_RASTRULE_LOWER_RIGHT;
279 }
280 /* XXX clamp max depends on AA vs. non-AA */
281
282 /* _NEW_POINT */
283 sf.sf7.sprite_point = key->point_sprite;
284 sf.sf7.point_size = CLAMP(rint(key->point_size), 1, 255) * (1<<3);
285 sf.sf7.use_point_size_state = !key->point_attenuated;
286 sf.sf7.aa_line_distance_mode = 0;
287
288 /* might be BRW_NEW_PRIMITIVE if we have to adjust pv for polygons:
289 */
290 if (key->provoking_vertex == GL_LAST_VERTEX_CONVENTION) {
291 sf.sf7.trifan_pv = 2;
292 sf.sf7.linestrip_pv = 1;
293 sf.sf7.tristrip_pv = 2;
294 } else {
295 sf.sf7.trifan_pv = 1;
296 sf.sf7.linestrip_pv = 0;
297 sf.sf7.tristrip_pv = 0;
298 }
299 sf.sf7.line_last_pixel_enable = 0;
300
301 /* Set bias for OpenGL rasterization rules:
302 */
303 sf.sf6.dest_org_vbias = 0x8;
304 sf.sf6.dest_org_hbias = 0x8;
305
306 bo = brw_upload_cache(&brw->cache, BRW_SF_UNIT,
307 key, sizeof(*key),
308 reloc_bufs, 2,
309 &sf, sizeof(sf),
310 NULL, NULL);
311
312 /* STATE_PREFETCH command description describes this state as being
313 * something loaded through the GPE (L2 ISC), so it's INSTRUCTION domain.
314 */
315 /* Emit SF program relocation */
316 dri_bo_emit_reloc(bo,
317 I915_GEM_DOMAIN_INSTRUCTION, 0,
318 sf.thread0.grf_reg_count << 1,
319 offsetof(struct brw_sf_unit_state, thread0),
320 brw->sf.prog_bo);
321
322 /* Emit SF viewport relocation */
323 dri_bo_emit_reloc(bo,
324 I915_GEM_DOMAIN_INSTRUCTION, 0,
325 sf.sf5.front_winding | (sf.sf5.viewport_transform << 1),
326 offsetof(struct brw_sf_unit_state, sf5),
327 brw->sf.vp_bo);
328
329 return bo;
330 }
331
332 static void upload_sf_unit( struct brw_context *brw )
333 {
334 struct brw_sf_unit_key key;
335 dri_bo *reloc_bufs[2];
336
337 sf_unit_populate_key(brw, &key);
338
339 reloc_bufs[0] = brw->sf.prog_bo;
340 reloc_bufs[1] = brw->sf.vp_bo;
341
342 dri_bo_unreference(brw->sf.state_bo);
343 brw->sf.state_bo = brw_search_cache(&brw->cache, BRW_SF_UNIT,
344 &key, sizeof(key),
345 reloc_bufs, 2,
346 NULL);
347 if (brw->sf.state_bo == NULL) {
348 brw->sf.state_bo = sf_unit_create_from_key(brw, &key, reloc_bufs);
349 }
350 }
351
352 const struct brw_tracked_state brw_sf_unit = {
353 .dirty = {
354 .mesa = (_NEW_POLYGON |
355 _NEW_LIGHT |
356 _NEW_LINE |
357 _NEW_POINT |
358 _NEW_SCISSOR |
359 _NEW_BUFFERS),
360 .brw = BRW_NEW_URB_FENCE,
361 .cache = (CACHE_NEW_SF_VP |
362 CACHE_NEW_SF_PROG)
363 },
364 .prepare = upload_sf_unit,
365 };