i965: Always pass the size argument to brw_cache_data.
[mesa.git] / src / mesa / drivers / dri / i965 / brw_sf_state.c
1 /*
2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
5
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
13
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
17
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25
26 **********************************************************************/
27 /*
28 * Authors:
29 * Keith Whitwell <keith@tungstengraphics.com>
30 */
31
32
33
34 #include "brw_context.h"
35 #include "brw_state.h"
36 #include "brw_defines.h"
37 #include "main/macros.h"
38 #include "intel_fbo.h"
39
40 static void upload_sf_vp(struct brw_context *brw)
41 {
42 GLcontext *ctx = &brw->intel.ctx;
43 const GLfloat depth_scale = 1.0F / ctx->DrawBuffer->_DepthMaxF;
44 struct brw_sf_viewport sfv;
45 GLfloat y_scale, y_bias;
46 const GLboolean render_to_fbo = (ctx->DrawBuffer->Name != 0);
47 const GLfloat *v = ctx->Viewport._WindowMap.m;
48
49 memset(&sfv, 0, sizeof(sfv));
50
51 if (render_to_fbo) {
52 y_scale = 1.0;
53 y_bias = 0;
54 }
55 else {
56 y_scale = -1.0;
57 y_bias = ctx->DrawBuffer->Height;
58 }
59
60 /* _NEW_VIEWPORT */
61
62 sfv.viewport.m00 = v[MAT_SX];
63 sfv.viewport.m11 = v[MAT_SY] * y_scale;
64 sfv.viewport.m22 = v[MAT_SZ] * depth_scale;
65 sfv.viewport.m30 = v[MAT_TX];
66 sfv.viewport.m31 = v[MAT_TY] * y_scale + y_bias;
67 sfv.viewport.m32 = v[MAT_TZ] * depth_scale;
68
69 /* _NEW_SCISSOR | _NEW_BUFFERS | _NEW_VIEWPORT
70 * for DrawBuffer->_[XY]{min,max}
71 */
72
73 /* The scissor only needs to handle the intersection of drawable and
74 * scissor rect. Clipping to the boundaries of static shared buffers
75 * for front/back/depth is covered by looping over cliprects in brw_draw.c.
76 *
77 * Note that the hardware's coordinates are inclusive, while Mesa's min is
78 * inclusive but max is exclusive.
79 */
80 if (render_to_fbo) {
81 /* texmemory: Y=0=bottom */
82 sfv.scissor.xmin = ctx->DrawBuffer->_Xmin;
83 sfv.scissor.xmax = ctx->DrawBuffer->_Xmax - 1;
84 sfv.scissor.ymin = ctx->DrawBuffer->_Ymin;
85 sfv.scissor.ymax = ctx->DrawBuffer->_Ymax - 1;
86 }
87 else {
88 /* memory: Y=0=top */
89 sfv.scissor.xmin = ctx->DrawBuffer->_Xmin;
90 sfv.scissor.xmax = ctx->DrawBuffer->_Xmax - 1;
91 sfv.scissor.ymin = ctx->DrawBuffer->Height - ctx->DrawBuffer->_Ymax;
92 sfv.scissor.ymax = ctx->DrawBuffer->Height - ctx->DrawBuffer->_Ymin - 1;
93 }
94
95 dri_bo_unreference(brw->sf.vp_bo);
96 brw->sf.vp_bo = brw_cache_data(&brw->cache, BRW_SF_VP, &sfv, sizeof(sfv),
97 NULL, 0);
98 }
99
100 const struct brw_tracked_state brw_sf_vp = {
101 .dirty = {
102 .mesa = (_NEW_VIEWPORT |
103 _NEW_SCISSOR |
104 _NEW_BUFFERS),
105 .brw = 0,
106 .cache = 0
107 },
108 .prepare = upload_sf_vp
109 };
110
111 struct brw_sf_unit_key {
112 unsigned int total_grf;
113 unsigned int urb_entry_read_length;
114
115 unsigned int nr_urb_entries, urb_size, sfsize;
116
117 GLenum front_face, cull_face, provoking_vertex;
118 unsigned scissor:1;
119 unsigned line_smooth:1;
120 unsigned point_sprite:1;
121 unsigned point_attenuated:1;
122 unsigned render_to_fbo:1;
123 float line_width;
124 float point_size;
125 };
126
127 static void
128 sf_unit_populate_key(struct brw_context *brw, struct brw_sf_unit_key *key)
129 {
130 GLcontext *ctx = &brw->intel.ctx;
131 memset(key, 0, sizeof(*key));
132
133 /* CACHE_NEW_SF_PROG */
134 key->total_grf = brw->sf.prog_data->total_grf;
135 key->urb_entry_read_length = brw->sf.prog_data->urb_read_length;
136
137 /* BRW_NEW_URB_FENCE */
138 key->nr_urb_entries = brw->urb.nr_sf_entries;
139 key->urb_size = brw->urb.vsize;
140 key->sfsize = brw->urb.sfsize;
141
142 key->scissor = ctx->Scissor.Enabled;
143 key->front_face = ctx->Polygon.FrontFace;
144
145 if (ctx->Polygon.CullFlag)
146 key->cull_face = ctx->Polygon.CullFaceMode;
147 else
148 key->cull_face = GL_NONE;
149
150 key->line_width = ctx->Line.Width;
151 key->line_smooth = ctx->Line.SmoothFlag;
152
153 key->point_sprite = ctx->Point.PointSprite;
154 key->point_size = CLAMP(ctx->Point.Size, ctx->Point.MinSize, ctx->Point.MaxSize);
155 key->point_attenuated = ctx->Point._Attenuated;
156
157 /* _NEW_LIGHT */
158 key->provoking_vertex = ctx->Light.ProvokingVertex;
159
160 key->render_to_fbo = brw->intel.ctx.DrawBuffer->Name != 0;
161 }
162
163 static dri_bo *
164 sf_unit_create_from_key(struct brw_context *brw, struct brw_sf_unit_key *key,
165 dri_bo **reloc_bufs)
166 {
167 struct brw_sf_unit_state sf;
168 dri_bo *bo;
169 int chipset_max_threads;
170 memset(&sf, 0, sizeof(sf));
171
172 sf.thread0.grf_reg_count = ALIGN(key->total_grf, 16) / 16 - 1;
173 sf.thread0.kernel_start_pointer = brw->sf.prog_bo->offset >> 6; /* reloc */
174
175 sf.thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754;
176
177 sf.thread3.dispatch_grf_start_reg = 3;
178
179 if (BRW_IS_IGDNG(brw))
180 sf.thread3.urb_entry_read_offset = 3;
181 else
182 sf.thread3.urb_entry_read_offset = 1;
183
184 sf.thread3.urb_entry_read_length = key->urb_entry_read_length;
185
186 sf.thread4.nr_urb_entries = key->nr_urb_entries;
187 sf.thread4.urb_entry_allocation_size = key->sfsize - 1;
188
189 /* Each SF thread produces 1 PUE, and there can be up to 24(Pre-IGDNG) or
190 * 48(IGDNG) threads
191 */
192 if (BRW_IS_IGDNG(brw))
193 chipset_max_threads = 48;
194 else
195 chipset_max_threads = 24;
196
197 sf.thread4.max_threads = MIN2(chipset_max_threads, key->nr_urb_entries) - 1;
198
199 if (INTEL_DEBUG & DEBUG_SINGLE_THREAD)
200 sf.thread4.max_threads = 0;
201
202 if (INTEL_DEBUG & DEBUG_STATS)
203 sf.thread4.stats_enable = 1;
204
205 /* CACHE_NEW_SF_VP */
206 sf.sf5.sf_viewport_state_offset = brw->sf.vp_bo->offset >> 5; /* reloc */
207
208 sf.sf5.viewport_transform = 1;
209
210 /* _NEW_SCISSOR */
211 if (key->scissor)
212 sf.sf6.scissor = 1;
213
214 /* _NEW_POLYGON */
215 if (key->front_face == GL_CCW)
216 sf.sf5.front_winding = BRW_FRONTWINDING_CCW;
217 else
218 sf.sf5.front_winding = BRW_FRONTWINDING_CW;
219
220 /* The viewport is inverted for rendering to a FBO, and that inverts
221 * polygon front/back orientation.
222 */
223 sf.sf5.front_winding ^= key->render_to_fbo;
224
225 switch (key->cull_face) {
226 case GL_FRONT:
227 sf.sf6.cull_mode = BRW_CULLMODE_FRONT;
228 break;
229 case GL_BACK:
230 sf.sf6.cull_mode = BRW_CULLMODE_BACK;
231 break;
232 case GL_FRONT_AND_BACK:
233 sf.sf6.cull_mode = BRW_CULLMODE_BOTH;
234 break;
235 case GL_NONE:
236 sf.sf6.cull_mode = BRW_CULLMODE_NONE;
237 break;
238 default:
239 assert(0);
240 break;
241 }
242
243 /* _NEW_LINE */
244 /* XXX use ctx->Const.Min/MaxLineWidth here */
245 sf.sf6.line_width = CLAMP(key->line_width, 1.0, 5.0) * (1<<1);
246
247 sf.sf6.line_endcap_aa_region_width = 1;
248 if (key->line_smooth)
249 sf.sf6.aa_enable = 1;
250 else if (sf.sf6.line_width <= 0x2)
251 sf.sf6.line_width = 0;
252
253 /* _NEW_BUFFERS */
254 key->render_to_fbo = brw->intel.ctx.DrawBuffer->Name != 0;
255 if (!key->render_to_fbo) {
256 /* Rendering to an OpenGL window */
257 sf.sf6.point_rast_rule = BRW_RASTRULE_UPPER_RIGHT;
258 }
259 else {
260 /* If rendering to an FBO, the pixel coordinate system is
261 * inverted with respect to the normal OpenGL coordinate
262 * system, so BRW_RASTRULE_LOWER_RIGHT is correct.
263 * But this value is listed as "Reserved, but not seen as useful"
264 * in Intel documentation (page 212, "Point Rasterization Rule",
265 * section 7.4 "SF Pipeline State Summary", of document
266 * "IntelĀ® 965 Express Chipset Family and IntelĀ® G35 Express
267 * Chipset Graphics Controller Programmer's Reference Manual,
268 * Volume 2: 3D/Media", Revision 1.0b as of January 2008,
269 * available at
270 * http://intellinuxgraphics.org/documentation.html
271 * at the time of this writing).
272 *
273 * It does work on at least some devices, if not all;
274 * if devices that don't support it can be identified,
275 * the likely failure case is that points are rasterized
276 * incorrectly, which is no worse than occurs without
277 * the value, so we're using it here.
278 */
279 sf.sf6.point_rast_rule = BRW_RASTRULE_LOWER_RIGHT;
280 }
281 /* XXX clamp max depends on AA vs. non-AA */
282
283 /* _NEW_POINT */
284 sf.sf7.sprite_point = key->point_sprite;
285 sf.sf7.point_size = CLAMP(rint(key->point_size), 1, 255) * (1<<3);
286 sf.sf7.use_point_size_state = !key->point_attenuated;
287 sf.sf7.aa_line_distance_mode = 0;
288
289 /* might be BRW_NEW_PRIMITIVE if we have to adjust pv for polygons:
290 */
291 if (key->provoking_vertex == GL_LAST_VERTEX_CONVENTION) {
292 sf.sf7.trifan_pv = 2;
293 sf.sf7.linestrip_pv = 1;
294 sf.sf7.tristrip_pv = 2;
295 } else {
296 sf.sf7.trifan_pv = 1;
297 sf.sf7.linestrip_pv = 0;
298 sf.sf7.tristrip_pv = 0;
299 }
300 sf.sf7.line_last_pixel_enable = 0;
301
302 /* Set bias for OpenGL rasterization rules:
303 */
304 sf.sf6.dest_org_vbias = 0x8;
305 sf.sf6.dest_org_hbias = 0x8;
306
307 bo = brw_upload_cache(&brw->cache, BRW_SF_UNIT,
308 key, sizeof(*key),
309 reloc_bufs, 2,
310 &sf, sizeof(sf),
311 NULL, NULL);
312
313 /* STATE_PREFETCH command description describes this state as being
314 * something loaded through the GPE (L2 ISC), so it's INSTRUCTION domain.
315 */
316 /* Emit SF program relocation */
317 dri_bo_emit_reloc(bo,
318 I915_GEM_DOMAIN_INSTRUCTION, 0,
319 sf.thread0.grf_reg_count << 1,
320 offsetof(struct brw_sf_unit_state, thread0),
321 brw->sf.prog_bo);
322
323 /* Emit SF viewport relocation */
324 dri_bo_emit_reloc(bo,
325 I915_GEM_DOMAIN_INSTRUCTION, 0,
326 sf.sf5.front_winding | (sf.sf5.viewport_transform << 1),
327 offsetof(struct brw_sf_unit_state, sf5),
328 brw->sf.vp_bo);
329
330 return bo;
331 }
332
333 static void upload_sf_unit( struct brw_context *brw )
334 {
335 struct brw_sf_unit_key key;
336 dri_bo *reloc_bufs[2];
337
338 sf_unit_populate_key(brw, &key);
339
340 reloc_bufs[0] = brw->sf.prog_bo;
341 reloc_bufs[1] = brw->sf.vp_bo;
342
343 dri_bo_unreference(brw->sf.state_bo);
344 brw->sf.state_bo = brw_search_cache(&brw->cache, BRW_SF_UNIT,
345 &key, sizeof(key),
346 reloc_bufs, 2,
347 NULL);
348 if (brw->sf.state_bo == NULL) {
349 brw->sf.state_bo = sf_unit_create_from_key(brw, &key, reloc_bufs);
350 }
351 }
352
353 const struct brw_tracked_state brw_sf_unit = {
354 .dirty = {
355 .mesa = (_NEW_POLYGON |
356 _NEW_LIGHT |
357 _NEW_LINE |
358 _NEW_POINT |
359 _NEW_SCISSOR |
360 _NEW_BUFFERS),
361 .brw = BRW_NEW_URB_FENCE,
362 .cache = (CACHE_NEW_SF_VP |
363 CACHE_NEW_SF_PROG)
364 },
365 .prepare = upload_sf_unit,
366 };