src/mesa/drivers/dri/i965/brw_shader.cpp

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_context.h"
  25 #include "brw_cfg.h"
  26 #include "brw_eu.h"
  27 #include "brw_fs.h"
  28 #include "brw_nir.h"
  29 #include "brw_vec4_tes.h"
  30 #include "main/uniforms.h"
  31
  32 enum brw_reg_type
  33 brw_type_for_base_type(const struct glsl_type *type)
  34 {
  35    switch (type->base_type) {
  36    case GLSL_TYPE_FLOAT:
  37       return BRW_REGISTER_TYPE_F;
  38    case GLSL_TYPE_INT:
  39    case GLSL_TYPE_BOOL:
  40    case GLSL_TYPE_SUBROUTINE:
  41       return BRW_REGISTER_TYPE_D;
  42    case GLSL_TYPE_UINT:
  43       return BRW_REGISTER_TYPE_UD;
  44    case GLSL_TYPE_ARRAY:
  45       return brw_type_for_base_type(type->fields.array);
  46    case GLSL_TYPE_STRUCT:
  47    case GLSL_TYPE_SAMPLER:
  48    case GLSL_TYPE_ATOMIC_UINT:
  49       /* These should be overridden with the type of the member when
  50        * dereferenced into.  BRW_REGISTER_TYPE_UD seems like a likely
  51        * way to trip up if we don't.
  52        */
  53       return BRW_REGISTER_TYPE_UD;
  54    case GLSL_TYPE_IMAGE:
  55       return BRW_REGISTER_TYPE_UD;
  56    case GLSL_TYPE_DOUBLE:
  57       return BRW_REGISTER_TYPE_DF;
  58    case GLSL_TYPE_UINT64:
  59       return BRW_REGISTER_TYPE_UQ;
  60    case GLSL_TYPE_INT64:
  61       return BRW_REGISTER_TYPE_Q;
  62    case GLSL_TYPE_VOID:
  63    case GLSL_TYPE_ERROR:
  64    case GLSL_TYPE_INTERFACE:
  65    case GLSL_TYPE_FUNCTION:
  66       unreachable("not reached");
  67    }
  68
  69    return BRW_REGISTER_TYPE_F;
  70 }
  71
  72 enum brw_conditional_mod
  73 brw_conditional_for_comparison(unsigned int op)
  74 {
  75    switch (op) {
  76    case ir_binop_less:
  77       return BRW_CONDITIONAL_L;
  78    case ir_binop_greater:
  79       return BRW_CONDITIONAL_G;
  80    case ir_binop_lequal:
  81       return BRW_CONDITIONAL_LE;
  82    case ir_binop_gequal:
  83       return BRW_CONDITIONAL_GE;
  84    case ir_binop_equal:
  85    case ir_binop_all_equal: /* same as equal for scalars */
  86       return BRW_CONDITIONAL_Z;
  87    case ir_binop_nequal:
  88    case ir_binop_any_nequal: /* same as nequal for scalars */
  89       return BRW_CONDITIONAL_NZ;
  90    default:
  91       unreachable("not reached: bad operation for comparison");
  92    }
  93 }
  94
  95 uint32_t
  96 brw_math_function(enum opcode op)
  97 {
  98    switch (op) {
  99    case SHADER_OPCODE_RCP:
 100       return BRW_MATH_FUNCTION_INV;
 101    case SHADER_OPCODE_RSQ:
 102       return BRW_MATH_FUNCTION_RSQ;
 103    case SHADER_OPCODE_SQRT:
 104       return BRW_MATH_FUNCTION_SQRT;
 105    case SHADER_OPCODE_EXP2:
 106       return BRW_MATH_FUNCTION_EXP;
 107    case SHADER_OPCODE_LOG2:
 108       return BRW_MATH_FUNCTION_LOG;
 109    case SHADER_OPCODE_POW:
 110       return BRW_MATH_FUNCTION_POW;
 111    case SHADER_OPCODE_SIN:
 112       return BRW_MATH_FUNCTION_SIN;
 113    case SHADER_OPCODE_COS:
 114       return BRW_MATH_FUNCTION_COS;
 115    case SHADER_OPCODE_INT_QUOTIENT:
 116       return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT;
 117    case SHADER_OPCODE_INT_REMAINDER:
 118       return BRW_MATH_FUNCTION_INT_DIV_REMAINDER;
 119    default:
 120       unreachable("not reached: unknown math function");
 121    }
 122 }
 123
 124 bool
 125 brw_texture_offset(int *offsets, unsigned num_components, uint32_t *offset_bits)
 126 {
 127    if (!offsets) return false;  /* nonconstant offset; caller will handle it. */
 128
 129    /* offset out of bounds; caller will handle it. */
 130    for (unsigned i = 0; i < num_components; i++)
 131       if (offsets[i] > 7 || offsets[i] < -8)
 132          return false;
 133
 134    /* Combine all three offsets into a single unsigned dword:
 135     *
 136     *    bits 11:8 - U Offset (X component)
 137     *    bits  7:4 - V Offset (Y component)
 138     *    bits  3:0 - R Offset (Z component)
 139     */
 140    *offset_bits = 0;
 141    for (unsigned i = 0; i < num_components; i++) {
 142       const unsigned shift = 4 * (2 - i);
 143       *offset_bits |= (offsets[i] << shift) & (0xF << shift);
 144    }
 145    return true;
 146 }
 147
 148 const char *
 149 brw_instruction_name(const struct gen_device_info *devinfo, enum opcode op)
 150 {
 151    switch (op) {
 152    case BRW_OPCODE_ILLEGAL ... BRW_OPCODE_NOP:
 153       /* The DO instruction doesn't exist on Gen6+, but we use it to mark the
 154        * start of a loop in the IR.
 155        */
 156       if (devinfo->gen >= 6 && op == BRW_OPCODE_DO)
 157          return "do";
 158
 159       assert(brw_opcode_desc(devinfo, op)->name);
 160       return brw_opcode_desc(devinfo, op)->name;
 161    case FS_OPCODE_FB_WRITE:
 162       return "fb_write";
 163    case FS_OPCODE_FB_WRITE_LOGICAL:
 164       return "fb_write_logical";
 165    case FS_OPCODE_REP_FB_WRITE:
 166       return "rep_fb_write";
 167    case FS_OPCODE_FB_READ:
 168       return "fb_read";
 169    case FS_OPCODE_FB_READ_LOGICAL:
 170       return "fb_read_logical";
 171
 172    case SHADER_OPCODE_RCP:
 173       return "rcp";
 174    case SHADER_OPCODE_RSQ:
 175       return "rsq";
 176    case SHADER_OPCODE_SQRT:
 177       return "sqrt";
 178    case SHADER_OPCODE_EXP2:
 179       return "exp2";
 180    case SHADER_OPCODE_LOG2:
 181       return "log2";
 182    case SHADER_OPCODE_POW:
 183       return "pow";
 184    case SHADER_OPCODE_INT_QUOTIENT:
 185       return "int_quot";
 186    case SHADER_OPCODE_INT_REMAINDER:
 187       return "int_rem";
 188    case SHADER_OPCODE_SIN:
 189       return "sin";
 190    case SHADER_OPCODE_COS:
 191       return "cos";
 192
 193    case SHADER_OPCODE_TEX:
 194       return "tex";
 195    case SHADER_OPCODE_TEX_LOGICAL:
 196       return "tex_logical";
 197    case SHADER_OPCODE_TXD:
 198       return "txd";
 199    case SHADER_OPCODE_TXD_LOGICAL:
 200       return "txd_logical";
 201    case SHADER_OPCODE_TXF:
 202       return "txf";
 203    case SHADER_OPCODE_TXF_LOGICAL:
 204       return "txf_logical";
 205    case SHADER_OPCODE_TXF_LZ:
 206       return "txf_lz";
 207    case SHADER_OPCODE_TXL:
 208       return "txl";
 209    case SHADER_OPCODE_TXL_LOGICAL:
 210       return "txl_logical";
 211    case SHADER_OPCODE_TXL_LZ:
 212       return "txl_lz";
 213    case SHADER_OPCODE_TXS:
 214       return "txs";
 215    case SHADER_OPCODE_TXS_LOGICAL:
 216       return "txs_logical";
 217    case FS_OPCODE_TXB:
 218       return "txb";
 219    case FS_OPCODE_TXB_LOGICAL:
 220       return "txb_logical";
 221    case SHADER_OPCODE_TXF_CMS:
 222       return "txf_cms";
 223    case SHADER_OPCODE_TXF_CMS_LOGICAL:
 224       return "txf_cms_logical";
 225    case SHADER_OPCODE_TXF_CMS_W:
 226       return "txf_cms_w";
 227    case SHADER_OPCODE_TXF_CMS_W_LOGICAL:
 228       return "txf_cms_w_logical";
 229    case SHADER_OPCODE_TXF_UMS:
 230       return "txf_ums";
 231    case SHADER_OPCODE_TXF_UMS_LOGICAL:
 232       return "txf_ums_logical";
 233    case SHADER_OPCODE_TXF_MCS:
 234       return "txf_mcs";
 235    case SHADER_OPCODE_TXF_MCS_LOGICAL:
 236       return "txf_mcs_logical";
 237    case SHADER_OPCODE_LOD:
 238       return "lod";
 239    case SHADER_OPCODE_LOD_LOGICAL:
 240       return "lod_logical";
 241    case SHADER_OPCODE_TG4:
 242       return "tg4";
 243    case SHADER_OPCODE_TG4_LOGICAL:
 244       return "tg4_logical";
 245    case SHADER_OPCODE_TG4_OFFSET:
 246       return "tg4_offset";
 247    case SHADER_OPCODE_TG4_OFFSET_LOGICAL:
 248       return "tg4_offset_logical";
 249    case SHADER_OPCODE_SAMPLEINFO:
 250       return "sampleinfo";
 251    case SHADER_OPCODE_SAMPLEINFO_LOGICAL:
 252       return "sampleinfo_logical";
 253
 254    case SHADER_OPCODE_SHADER_TIME_ADD:
 255       return "shader_time_add";
 256
 257    case SHADER_OPCODE_UNTYPED_ATOMIC:
 258       return "untyped_atomic";
 259    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
 260       return "untyped_atomic_logical";
 261    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
 262       return "untyped_surface_read";
 263    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
 264       return "untyped_surface_read_logical";
 265    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
 266       return "untyped_surface_write";
 267    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
 268       return "untyped_surface_write_logical";
 269    case SHADER_OPCODE_TYPED_ATOMIC:
 270       return "typed_atomic";
 271    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
 272       return "typed_atomic_logical";
 273    case SHADER_OPCODE_TYPED_SURFACE_READ:
 274       return "typed_surface_read";
 275    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
 276       return "typed_surface_read_logical";
 277    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
 278       return "typed_surface_write";
 279    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
 280       return "typed_surface_write_logical";
 281    case SHADER_OPCODE_MEMORY_FENCE:
 282       return "memory_fence";
 283
 284    case SHADER_OPCODE_LOAD_PAYLOAD:
 285       return "load_payload";
 286    case FS_OPCODE_PACK:
 287       return "pack";
 288
 289    case SHADER_OPCODE_GEN4_SCRATCH_READ:
 290       return "gen4_scratch_read";
 291    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 292       return "gen4_scratch_write";
 293    case SHADER_OPCODE_GEN7_SCRATCH_READ:
 294       return "gen7_scratch_read";
 295    case SHADER_OPCODE_URB_WRITE_SIMD8:
 296       return "gen8_urb_write_simd8";
 297    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
 298       return "gen8_urb_write_simd8_per_slot";
 299    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
 300       return "gen8_urb_write_simd8_masked";
 301    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
 302       return "gen8_urb_write_simd8_masked_per_slot";
 303    case SHADER_OPCODE_URB_READ_SIMD8:
 304       return "urb_read_simd8";
 305    case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
 306       return "urb_read_simd8_per_slot";
 307
 308    case SHADER_OPCODE_FIND_LIVE_CHANNEL:
 309       return "find_live_channel";
 310    case SHADER_OPCODE_BROADCAST:
 311       return "broadcast";
 312
 313    case VEC4_OPCODE_MOV_BYTES:
 314       return "mov_bytes";
 315    case VEC4_OPCODE_PACK_BYTES:
 316       return "pack_bytes";
 317    case VEC4_OPCODE_UNPACK_UNIFORM:
 318       return "unpack_uniform";
 319    case VEC4_OPCODE_FROM_DOUBLE:
 320       return "double_to_single";
 321    case VEC4_OPCODE_TO_DOUBLE:
 322       return "single_to_double";
 323    case VEC4_OPCODE_PICK_LOW_32BIT:
 324       return "pick_low_32bit";
 325    case VEC4_OPCODE_PICK_HIGH_32BIT:
 326       return "pick_high_32bit";
 327    case VEC4_OPCODE_SET_LOW_32BIT:
 328       return "set_low_32bit";
 329    case VEC4_OPCODE_SET_HIGH_32BIT:
 330       return "set_high_32bit";
 331
 332    case FS_OPCODE_DDX_COARSE:
 333       return "ddx_coarse";
 334    case FS_OPCODE_DDX_FINE:
 335       return "ddx_fine";
 336    case FS_OPCODE_DDY_COARSE:
 337       return "ddy_coarse";
 338    case FS_OPCODE_DDY_FINE:
 339       return "ddy_fine";
 340
 341    case FS_OPCODE_CINTERP:
 342       return "cinterp";
 343    case FS_OPCODE_LINTERP:
 344       return "linterp";
 345
 346    case FS_OPCODE_PIXEL_X:
 347       return "pixel_x";
 348    case FS_OPCODE_PIXEL_Y:
 349       return "pixel_y";
 350
 351    case FS_OPCODE_GET_BUFFER_SIZE:
 352       return "fs_get_buffer_size";
 353
 354    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
 355       return "uniform_pull_const";
 356    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
 357       return "uniform_pull_const_gen7";
 358    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4:
 359       return "varying_pull_const_gen4";
 360    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
 361       return "varying_pull_const_gen7";
 362    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL:
 363       return "varying_pull_const_logical";
 364
 365    case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
 366       return "mov_dispatch_to_flags";
 367    case FS_OPCODE_DISCARD_JUMP:
 368       return "discard_jump";
 369
 370    case FS_OPCODE_SET_SAMPLE_ID:
 371       return "set_sample_id";
 372
 373    case FS_OPCODE_PACK_HALF_2x16_SPLIT:
 374       return "pack_half_2x16_split";
 375    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
 376       return "unpack_half_2x16_split_x";
 377    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
 378       return "unpack_half_2x16_split_y";
 379
 380    case FS_OPCODE_PLACEHOLDER_HALT:
 381       return "placeholder_halt";
 382
 383    case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
 384       return "interp_sample";
 385    case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
 386       return "interp_shared_offset";
 387    case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
 388       return "interp_per_slot_offset";
 389
 390    case VS_OPCODE_URB_WRITE:
 391       return "vs_urb_write";
 392    case VS_OPCODE_PULL_CONSTANT_LOAD:
 393       return "pull_constant_load";
 394    case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
 395       return "pull_constant_load_gen7";
 396
 397    case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
 398       return "set_simd4x2_header_gen9";
 399
 400    case VS_OPCODE_GET_BUFFER_SIZE:
 401       return "vs_get_buffer_size";
 402
 403    case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
 404       return "unpack_flags_simd4x2";
 405
 406    case GS_OPCODE_URB_WRITE:
 407       return "gs_urb_write";
 408    case GS_OPCODE_URB_WRITE_ALLOCATE:
 409       return "gs_urb_write_allocate";
 410    case GS_OPCODE_THREAD_END:
 411       return "gs_thread_end";
 412    case GS_OPCODE_SET_WRITE_OFFSET:
 413       return "set_write_offset";
 414    case GS_OPCODE_SET_VERTEX_COUNT:
 415       return "set_vertex_count";
 416    case GS_OPCODE_SET_DWORD_2:
 417       return "set_dword_2";
 418    case GS_OPCODE_PREPARE_CHANNEL_MASKS:
 419       return "prepare_channel_masks";
 420    case GS_OPCODE_SET_CHANNEL_MASKS:
 421       return "set_channel_masks";
 422    case GS_OPCODE_GET_INSTANCE_ID:
 423       return "get_instance_id";
 424    case GS_OPCODE_FF_SYNC:
 425       return "ff_sync";
 426    case GS_OPCODE_SET_PRIMITIVE_ID:
 427       return "set_primitive_id";
 428    case GS_OPCODE_SVB_WRITE:
 429       return "gs_svb_write";
 430    case GS_OPCODE_SVB_SET_DST_INDEX:
 431       return "gs_svb_set_dst_index";
 432    case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
 433       return "gs_ff_sync_set_primitives";
 434    case CS_OPCODE_CS_TERMINATE:
 435       return "cs_terminate";
 436    case SHADER_OPCODE_BARRIER:
 437       return "barrier";
 438    case SHADER_OPCODE_MULH:
 439       return "mulh";
 440    case SHADER_OPCODE_MOV_INDIRECT:
 441       return "mov_indirect";
 442
 443    case VEC4_OPCODE_URB_READ:
 444       return "urb_read";
 445    case TCS_OPCODE_GET_INSTANCE_ID:
 446       return "tcs_get_instance_id";
 447    case TCS_OPCODE_URB_WRITE:
 448       return "tcs_urb_write";
 449    case TCS_OPCODE_SET_INPUT_URB_OFFSETS:
 450       return "tcs_set_input_urb_offsets";
 451    case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS:
 452       return "tcs_set_output_urb_offsets";
 453    case TCS_OPCODE_GET_PRIMITIVE_ID:
 454       return "tcs_get_primitive_id";
 455    case TCS_OPCODE_CREATE_BARRIER_HEADER:
 456       return "tcs_create_barrier_header";
 457    case TCS_OPCODE_SRC0_010_IS_ZERO:
 458       return "tcs_src0<0,1,0>_is_zero";
 459    case TCS_OPCODE_RELEASE_INPUT:
 460       return "tcs_release_input";
 461    case TCS_OPCODE_THREAD_END:
 462       return "tcs_thread_end";
 463    case TES_OPCODE_CREATE_INPUT_READ_HEADER:
 464       return "tes_create_input_read_header";
 465    case TES_OPCODE_ADD_INDIRECT_URB_OFFSET:
 466       return "tes_add_indirect_urb_offset";
 467    case TES_OPCODE_GET_PRIMITIVE_ID:
 468       return "tes_get_primitive_id";
 469    }
 470
 471    unreachable("not reached");
 472 }
 473
 474 bool
 475 brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 476 {
 477    union {
 478       unsigned ud;
 479       int d;
 480       float f;
 481       double df;
 482    } imm, sat_imm = { 0 };
 483
 484    const unsigned size = type_sz(type);
 485
 486    /* We want to either do a 32-bit or 64-bit data copy, the type is otherwise
 487     * irrelevant, so just check the size of the type and copy from/to an
 488     * appropriately sized field.
 489     */
 490    if (size < 8)
 491       imm.ud = reg->ud;
 492    else
 493       imm.df = reg->df;
 494
 495    switch (type) {
 496    case BRW_REGISTER_TYPE_UD:
 497    case BRW_REGISTER_TYPE_D:
 498    case BRW_REGISTER_TYPE_UW:
 499    case BRW_REGISTER_TYPE_W:
 500    case BRW_REGISTER_TYPE_UQ:
 501    case BRW_REGISTER_TYPE_Q:
 502       /* Nothing to do. */
 503       return false;
 504    case BRW_REGISTER_TYPE_F:
 505       sat_imm.f = CLAMP(imm.f, 0.0f, 1.0f);
 506       break;
 507    case BRW_REGISTER_TYPE_DF:
 508       sat_imm.df = CLAMP(imm.df, 0.0, 1.0);
 509       break;
 510    case BRW_REGISTER_TYPE_UB:
 511    case BRW_REGISTER_TYPE_B:
 512       unreachable("no UB/B immediates");
 513    case BRW_REGISTER_TYPE_V:
 514    case BRW_REGISTER_TYPE_UV:
 515    case BRW_REGISTER_TYPE_VF:
 516       unreachable("unimplemented: saturate vector immediate");
 517    case BRW_REGISTER_TYPE_HF:
 518       unreachable("unimplemented: saturate HF immediate");
 519    }
 520
 521    if (size < 8) {
 522       if (imm.ud != sat_imm.ud) {
 523          reg->ud = sat_imm.ud;
 524          return true;
 525       }
 526    } else {
 527       if (imm.df != sat_imm.df) {
 528          reg->df = sat_imm.df;
 529          return true;
 530       }
 531    }
 532    return false;
 533 }
 534
 535 bool
 536 brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 537 {
 538    switch (type) {
 539    case BRW_REGISTER_TYPE_D:
 540    case BRW_REGISTER_TYPE_UD:
 541       reg->d = -reg->d;
 542       return true;
 543    case BRW_REGISTER_TYPE_W:
 544    case BRW_REGISTER_TYPE_UW:
 545       reg->d = -(int16_t)reg->ud;
 546       return true;
 547    case BRW_REGISTER_TYPE_F:
 548       reg->f = -reg->f;
 549       return true;
 550    case BRW_REGISTER_TYPE_VF:
 551       reg->ud ^= 0x80808080;
 552       return true;
 553    case BRW_REGISTER_TYPE_DF:
 554       reg->df = -reg->df;
 555       return true;
 556    case BRW_REGISTER_TYPE_UQ:
 557    case BRW_REGISTER_TYPE_Q:
 558       reg->d64 = -reg->d64;
 559       return true;
 560    case BRW_REGISTER_TYPE_UB:
 561    case BRW_REGISTER_TYPE_B:
 562       unreachable("no UB/B immediates");
 563    case BRW_REGISTER_TYPE_UV:
 564    case BRW_REGISTER_TYPE_V:
 565       assert(!"unimplemented: negate UV/V immediate");
 566    case BRW_REGISTER_TYPE_HF:
 567       assert(!"unimplemented: negate HF immediate");
 568    }
 569
 570    return false;
 571 }
 572
 573 bool
 574 brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg)
 575 {
 576    switch (type) {
 577    case BRW_REGISTER_TYPE_D:
 578       reg->d = abs(reg->d);
 579       return true;
 580    case BRW_REGISTER_TYPE_W:
 581       reg->d = abs((int16_t)reg->ud);
 582       return true;
 583    case BRW_REGISTER_TYPE_F:
 584       reg->f = fabsf(reg->f);
 585       return true;
 586    case BRW_REGISTER_TYPE_DF:
 587       reg->df = fabs(reg->df);
 588       return true;
 589    case BRW_REGISTER_TYPE_VF:
 590       reg->ud &= ~0x80808080;
 591       return true;
 592    case BRW_REGISTER_TYPE_Q:
 593       reg->d64 = imaxabs(reg->d64);
 594       return true;
 595    case BRW_REGISTER_TYPE_UB:
 596    case BRW_REGISTER_TYPE_B:
 597       unreachable("no UB/B immediates");
 598    case BRW_REGISTER_TYPE_UQ:
 599    case BRW_REGISTER_TYPE_UD:
 600    case BRW_REGISTER_TYPE_UW:
 601    case BRW_REGISTER_TYPE_UV:
 602       /* Presumably the absolute value modifier on an unsigned source is a
 603        * nop, but it would be nice to confirm.
 604        */
 605       assert(!"unimplemented: abs unsigned immediate");
 606    case BRW_REGISTER_TYPE_V:
 607       assert(!"unimplemented: abs V immediate");
 608    case BRW_REGISTER_TYPE_HF:
 609       assert(!"unimplemented: abs HF immediate");
 610    }
 611
 612    return false;
 613 }
 614
 615 /**
 616  * Get the appropriate atomic op for an image atomic intrinsic.
 617  */
 618 unsigned
 619 get_atomic_counter_op(nir_intrinsic_op op)
 620 {
 621    switch (op) {
 622    case nir_intrinsic_atomic_counter_inc:
 623       return BRW_AOP_INC;
 624    case nir_intrinsic_atomic_counter_dec:
 625       return BRW_AOP_PREDEC;
 626    case nir_intrinsic_atomic_counter_add:
 627       return BRW_AOP_ADD;
 628    case nir_intrinsic_atomic_counter_min:
 629       return BRW_AOP_UMIN;
 630    case nir_intrinsic_atomic_counter_max:
 631       return BRW_AOP_UMAX;
 632    case nir_intrinsic_atomic_counter_and:
 633       return BRW_AOP_AND;
 634    case nir_intrinsic_atomic_counter_or:
 635       return BRW_AOP_OR;
 636    case nir_intrinsic_atomic_counter_xor:
 637       return BRW_AOP_XOR;
 638    case nir_intrinsic_atomic_counter_exchange:
 639       return BRW_AOP_MOV;
 640    case nir_intrinsic_atomic_counter_comp_swap:
 641       return BRW_AOP_CMPWR;
 642    default:
 643       unreachable("Not reachable.");
 644    }
 645 }
 646
 647 backend_shader::backend_shader(const struct brw_compiler *compiler,
 648                                void *log_data,
 649                                void *mem_ctx,
 650                                const nir_shader *shader,
 651                                struct brw_stage_prog_data *stage_prog_data)
 652    : compiler(compiler),
 653      log_data(log_data),
 654      devinfo(compiler->devinfo),
 655      nir(shader),
 656      stage_prog_data(stage_prog_data),
 657      mem_ctx(mem_ctx),
 658      cfg(NULL),
 659      stage(shader->stage)
 660 {
 661    debug_enabled = INTEL_DEBUG & intel_debug_flag_for_shader_stage(stage);
 662    stage_name = _mesa_shader_stage_to_string(stage);
 663    stage_abbrev = _mesa_shader_stage_to_abbrev(stage);
 664 }
 665
 666 bool
 667 backend_reg::equals(const backend_reg &r) const
 668 {
 669    return brw_regs_equal(this, &r) && offset == r.offset;
 670 }
 671
 672 bool
 673 backend_reg::is_zero() const
 674 {
 675    if (file != IMM)
 676       return false;
 677
 678    switch (type) {
 679    case BRW_REGISTER_TYPE_F:
 680       return f == 0;
 681    case BRW_REGISTER_TYPE_DF:
 682       return df == 0;
 683    case BRW_REGISTER_TYPE_D:
 684    case BRW_REGISTER_TYPE_UD:
 685       return d == 0;
 686    case BRW_REGISTER_TYPE_UQ:
 687    case BRW_REGISTER_TYPE_Q:
 688       return u64 == 0;
 689    default:
 690       return false;
 691    }
 692 }
 693
 694 bool
 695 backend_reg::is_one() const
 696 {
 697    if (file != IMM)
 698       return false;
 699
 700    switch (type) {
 701    case BRW_REGISTER_TYPE_F:
 702       return f == 1.0f;
 703    case BRW_REGISTER_TYPE_DF:
 704       return df == 1.0;
 705    case BRW_REGISTER_TYPE_D:
 706    case BRW_REGISTER_TYPE_UD:
 707       return d == 1;
 708    case BRW_REGISTER_TYPE_UQ:
 709    case BRW_REGISTER_TYPE_Q:
 710       return u64 == 1;
 711    default:
 712       return false;
 713    }
 714 }
 715
 716 bool
 717 backend_reg::is_negative_one() const
 718 {
 719    if (file != IMM)
 720       return false;
 721
 722    switch (type) {
 723    case BRW_REGISTER_TYPE_F:
 724       return f == -1.0;
 725    case BRW_REGISTER_TYPE_DF:
 726       return df == -1.0;
 727    case BRW_REGISTER_TYPE_D:
 728       return d == -1;
 729    case BRW_REGISTER_TYPE_Q:
 730       return d64 == -1;
 731    default:
 732       return false;
 733    }
 734 }
 735
 736 bool
 737 backend_reg::is_null() const
 738 {
 739    return file == ARF && nr == BRW_ARF_NULL;
 740 }
 741
 742
 743 bool
 744 backend_reg::is_accumulator() const
 745 {
 746    return file == ARF && nr == BRW_ARF_ACCUMULATOR;
 747 }
 748
 749 bool
 750 backend_instruction::is_commutative() const
 751 {
 752    switch (opcode) {
 753    case BRW_OPCODE_AND:
 754    case BRW_OPCODE_OR:
 755    case BRW_OPCODE_XOR:
 756    case BRW_OPCODE_ADD:
 757    case BRW_OPCODE_MUL:
 758    case SHADER_OPCODE_MULH:
 759       return true;
 760    case BRW_OPCODE_SEL:
 761       /* MIN and MAX are commutative. */
 762       if (conditional_mod == BRW_CONDITIONAL_GE ||
 763           conditional_mod == BRW_CONDITIONAL_L) {
 764          return true;
 765       }
 766       /* fallthrough */
 767    default:
 768       return false;
 769    }
 770 }
 771
 772 bool
 773 backend_instruction::is_3src(const struct gen_device_info *devinfo) const
 774 {
 775    return ::is_3src(devinfo, opcode);
 776 }
 777
 778 bool
 779 backend_instruction::is_tex() const
 780 {
 781    return (opcode == SHADER_OPCODE_TEX ||
 782            opcode == FS_OPCODE_TXB ||
 783            opcode == SHADER_OPCODE_TXD ||
 784            opcode == SHADER_OPCODE_TXF ||
 785            opcode == SHADER_OPCODE_TXF_LZ ||
 786            opcode == SHADER_OPCODE_TXF_CMS ||
 787            opcode == SHADER_OPCODE_TXF_CMS_W ||
 788            opcode == SHADER_OPCODE_TXF_UMS ||
 789            opcode == SHADER_OPCODE_TXF_MCS ||
 790            opcode == SHADER_OPCODE_TXL ||
 791            opcode == SHADER_OPCODE_TXL_LZ ||
 792            opcode == SHADER_OPCODE_TXS ||
 793            opcode == SHADER_OPCODE_LOD ||
 794            opcode == SHADER_OPCODE_TG4 ||
 795            opcode == SHADER_OPCODE_TG4_OFFSET ||
 796            opcode == SHADER_OPCODE_SAMPLEINFO);
 797 }
 798
 799 bool
 800 backend_instruction::is_math() const
 801 {
 802    return (opcode == SHADER_OPCODE_RCP ||
 803            opcode == SHADER_OPCODE_RSQ ||
 804            opcode == SHADER_OPCODE_SQRT ||
 805            opcode == SHADER_OPCODE_EXP2 ||
 806            opcode == SHADER_OPCODE_LOG2 ||
 807            opcode == SHADER_OPCODE_SIN ||
 808            opcode == SHADER_OPCODE_COS ||
 809            opcode == SHADER_OPCODE_INT_QUOTIENT ||
 810            opcode == SHADER_OPCODE_INT_REMAINDER ||
 811            opcode == SHADER_OPCODE_POW);
 812 }
 813
 814 bool
 815 backend_instruction::is_control_flow() const
 816 {
 817    switch (opcode) {
 818    case BRW_OPCODE_DO:
 819    case BRW_OPCODE_WHILE:
 820    case BRW_OPCODE_IF:
 821    case BRW_OPCODE_ELSE:
 822    case BRW_OPCODE_ENDIF:
 823    case BRW_OPCODE_BREAK:
 824    case BRW_OPCODE_CONTINUE:
 825       return true;
 826    default:
 827       return false;
 828    }
 829 }
 830
 831 bool
 832 backend_instruction::can_do_source_mods() const
 833 {
 834    switch (opcode) {
 835    case BRW_OPCODE_ADDC:
 836    case BRW_OPCODE_BFE:
 837    case BRW_OPCODE_BFI1:
 838    case BRW_OPCODE_BFI2:
 839    case BRW_OPCODE_BFREV:
 840    case BRW_OPCODE_CBIT:
 841    case BRW_OPCODE_FBH:
 842    case BRW_OPCODE_FBL:
 843    case BRW_OPCODE_SUBB:
 844       return false;
 845    default:
 846       return true;
 847    }
 848 }
 849
 850 bool
 851 backend_instruction::can_do_saturate() const
 852 {
 853    switch (opcode) {
 854    case BRW_OPCODE_ADD:
 855    case BRW_OPCODE_ASR:
 856    case BRW_OPCODE_AVG:
 857    case BRW_OPCODE_DP2:
 858    case BRW_OPCODE_DP3:
 859    case BRW_OPCODE_DP4:
 860    case BRW_OPCODE_DPH:
 861    case BRW_OPCODE_F16TO32:
 862    case BRW_OPCODE_F32TO16:
 863    case BRW_OPCODE_LINE:
 864    case BRW_OPCODE_LRP:
 865    case BRW_OPCODE_MAC:
 866    case BRW_OPCODE_MAD:
 867    case BRW_OPCODE_MATH:
 868    case BRW_OPCODE_MOV:
 869    case BRW_OPCODE_MUL:
 870    case SHADER_OPCODE_MULH:
 871    case BRW_OPCODE_PLN:
 872    case BRW_OPCODE_RNDD:
 873    case BRW_OPCODE_RNDE:
 874    case BRW_OPCODE_RNDU:
 875    case BRW_OPCODE_RNDZ:
 876    case BRW_OPCODE_SEL:
 877    case BRW_OPCODE_SHL:
 878    case BRW_OPCODE_SHR:
 879    case FS_OPCODE_LINTERP:
 880    case SHADER_OPCODE_COS:
 881    case SHADER_OPCODE_EXP2:
 882    case SHADER_OPCODE_LOG2:
 883    case SHADER_OPCODE_POW:
 884    case SHADER_OPCODE_RCP:
 885    case SHADER_OPCODE_RSQ:
 886    case SHADER_OPCODE_SIN:
 887    case SHADER_OPCODE_SQRT:
 888       return true;
 889    default:
 890       return false;
 891    }
 892 }
 893
 894 bool
 895 backend_instruction::can_do_cmod() const
 896 {
 897    switch (opcode) {
 898    case BRW_OPCODE_ADD:
 899    case BRW_OPCODE_ADDC:
 900    case BRW_OPCODE_AND:
 901    case BRW_OPCODE_ASR:
 902    case BRW_OPCODE_AVG:
 903    case BRW_OPCODE_CMP:
 904    case BRW_OPCODE_CMPN:
 905    case BRW_OPCODE_DP2:
 906    case BRW_OPCODE_DP3:
 907    case BRW_OPCODE_DP4:
 908    case BRW_OPCODE_DPH:
 909    case BRW_OPCODE_F16TO32:
 910    case BRW_OPCODE_F32TO16:
 911    case BRW_OPCODE_FRC:
 912    case BRW_OPCODE_LINE:
 913    case BRW_OPCODE_LRP:
 914    case BRW_OPCODE_LZD:
 915    case BRW_OPCODE_MAC:
 916    case BRW_OPCODE_MACH:
 917    case BRW_OPCODE_MAD:
 918    case BRW_OPCODE_MOV:
 919    case BRW_OPCODE_MUL:
 920    case BRW_OPCODE_NOT:
 921    case BRW_OPCODE_OR:
 922    case BRW_OPCODE_PLN:
 923    case BRW_OPCODE_RNDD:
 924    case BRW_OPCODE_RNDE:
 925    case BRW_OPCODE_RNDU:
 926    case BRW_OPCODE_RNDZ:
 927    case BRW_OPCODE_SAD2:
 928    case BRW_OPCODE_SADA2:
 929    case BRW_OPCODE_SHL:
 930    case BRW_OPCODE_SHR:
 931    case BRW_OPCODE_SUBB:
 932    case BRW_OPCODE_XOR:
 933    case FS_OPCODE_CINTERP:
 934    case FS_OPCODE_LINTERP:
 935       return true;
 936    default:
 937       return false;
 938    }
 939 }
 940
 941 bool
 942 backend_instruction::reads_accumulator_implicitly() const
 943 {
 944    switch (opcode) {
 945    case BRW_OPCODE_MAC:
 946    case BRW_OPCODE_MACH:
 947    case BRW_OPCODE_SADA2:
 948       return true;
 949    default:
 950       return false;
 951    }
 952 }
 953
 954 bool
 955 backend_instruction::writes_accumulator_implicitly(const struct gen_device_info *devinfo) const
 956 {
 957    return writes_accumulator ||
 958           (devinfo->gen < 6 &&
 959            ((opcode >= BRW_OPCODE_ADD && opcode < BRW_OPCODE_NOP) ||
 960             (opcode >= FS_OPCODE_DDX_COARSE && opcode <= FS_OPCODE_LINTERP &&
 961              opcode != FS_OPCODE_CINTERP)));
 962 }
 963
 964 bool
 965 backend_instruction::has_side_effects() const
 966 {
 967    switch (opcode) {
 968    case SHADER_OPCODE_UNTYPED_ATOMIC:
 969    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
 970    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 971    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
 972    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
 973    case SHADER_OPCODE_TYPED_ATOMIC:
 974    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
 975    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
 976    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
 977    case SHADER_OPCODE_MEMORY_FENCE:
 978    case SHADER_OPCODE_URB_WRITE_SIMD8:
 979    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
 980    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
 981    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
 982    case FS_OPCODE_FB_WRITE:
 983    case FS_OPCODE_FB_WRITE_LOGICAL:
 984    case SHADER_OPCODE_BARRIER:
 985    case TCS_OPCODE_URB_WRITE:
 986    case TCS_OPCODE_RELEASE_INPUT:
 987       return true;
 988    default:
 989       return false;
 990    }
 991 }
 992
 993 bool
 994 backend_instruction::is_volatile() const
 995 {
 996    switch (opcode) {
 997    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
 998    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
 999    case SHADER_OPCODE_TYPED_SURFACE_READ:
1000    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
1001    case SHADER_OPCODE_URB_READ_SIMD8:
1002    case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
1003    case VEC4_OPCODE_URB_READ:
1004       return true;
1005    default:
1006       return false;
1007    }
1008 }
1009
1010 #ifndef NDEBUG
1011 static bool
1012 inst_is_in_block(const bblock_t *block, const backend_instruction *inst)
1013 {
1014    bool found = false;
1015    foreach_inst_in_block (backend_instruction, i, block) {
1016       if (inst == i) {
1017          found = true;
1018       }
1019    }
1020    return found;
1021 }
1022 #endif
1023
1024 static void
1025 adjust_later_block_ips(bblock_t *start_block, int ip_adjustment)
1026 {
1027    for (bblock_t *block_iter = start_block->next();
1028         block_iter;
1029         block_iter = block_iter->next()) {
1030       block_iter->start_ip += ip_adjustment;
1031       block_iter->end_ip += ip_adjustment;
1032    }
1033 }
1034
1035 void
1036 backend_instruction::insert_after(bblock_t *block, backend_instruction *inst)
1037 {
1038    assert(this != inst);
1039
1040    if (!this->is_head_sentinel())
1041       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1042
1043    block->end_ip++;
1044
1045    adjust_later_block_ips(block, 1);
1046
1047    exec_node::insert_after(inst);
1048 }
1049
1050 void
1051 backend_instruction::insert_before(bblock_t *block, backend_instruction *inst)
1052 {
1053    assert(this != inst);
1054
1055    if (!this->is_tail_sentinel())
1056       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1057
1058    block->end_ip++;
1059
1060    adjust_later_block_ips(block, 1);
1061
1062    exec_node::insert_before(inst);
1063 }
1064
1065 void
1066 backend_instruction::insert_before(bblock_t *block, exec_list *list)
1067 {
1068    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1069
1070    unsigned num_inst = list->length();
1071
1072    block->end_ip += num_inst;
1073
1074    adjust_later_block_ips(block, num_inst);
1075
1076    exec_node::insert_before(list);
1077 }
1078
1079 void
1080 backend_instruction::remove(bblock_t *block)
1081 {
1082    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1083
1084    adjust_later_block_ips(block, -1);
1085
1086    if (block->start_ip == block->end_ip) {
1087       block->cfg->remove_block(block);
1088    } else {
1089       block->end_ip--;
1090    }
1091
1092    exec_node::remove();
1093 }
1094
1095 void
1096 backend_shader::dump_instructions()
1097 {
1098    dump_instructions(NULL);
1099 }
1100
1101 void
1102 backend_shader::dump_instructions(const char *name)
1103 {
1104    FILE *file = stderr;
1105    if (name && geteuid() != 0) {
1106       file = fopen(name, "w");
1107       if (!file)
1108          file = stderr;
1109    }
1110
1111    if (cfg) {
1112       int ip = 0;
1113       foreach_block_and_inst(block, backend_instruction, inst, cfg) {
1114          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1115             fprintf(file, "%4d: ", ip++);
1116          dump_instruction(inst, file);
1117       }
1118    } else {
1119       int ip = 0;
1120       foreach_in_list(backend_instruction, inst, &instructions) {
1121          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1122             fprintf(file, "%4d: ", ip++);
1123          dump_instruction(inst, file);
1124       }
1125    }
1126
1127    if (file != stderr) {
1128       fclose(file);
1129    }
1130 }
1131
1132 void
1133 backend_shader::calculate_cfg()
1134 {
1135    if (this->cfg)
1136       return;
1137    cfg = new(mem_ctx) cfg_t(&this->instructions);
1138 }
1139
1140 extern "C" const unsigned *
1141 brw_compile_tes(const struct brw_compiler *compiler,
1142                 void *log_data,
1143                 void *mem_ctx,
1144                 const struct brw_tes_prog_key *key,
1145                 const struct brw_vue_map *input_vue_map,
1146                 struct brw_tes_prog_data *prog_data,
1147                 const nir_shader *src_shader,
1148                 struct gl_program *prog,
1149                 int shader_time_index,
1150                 unsigned *final_assembly_size,
1151                 char **error_str)
1152 {
1153    const struct gen_device_info *devinfo = compiler->devinfo;
1154    const bool is_scalar = compiler->scalar_stage[MESA_SHADER_TESS_EVAL];
1155
1156    nir_shader *nir = nir_shader_clone(mem_ctx, src_shader);
1157    nir->info->inputs_read = key->inputs_read;
1158    nir->info->patch_inputs_read = key->patch_inputs_read;
1159
1160    nir = brw_nir_apply_sampler_key(nir, compiler, &key->tex, is_scalar);
1161    brw_nir_lower_tes_inputs(nir, input_vue_map);
1162    brw_nir_lower_vue_outputs(nir, is_scalar);
1163    nir = brw_postprocess_nir(nir, compiler, is_scalar);
1164
1165    brw_compute_vue_map(devinfo, &prog_data->base.vue_map,
1166                        nir->info->outputs_written,
1167                        nir->info->separate_shader);
1168
1169    unsigned output_size_bytes = prog_data->base.vue_map.num_slots * 4 * 4;
1170
1171    assert(output_size_bytes >= 1);
1172    if (output_size_bytes > GEN7_MAX_DS_URB_ENTRY_SIZE_BYTES) {
1173       if (error_str)
1174          *error_str = ralloc_strdup(mem_ctx, "DS outputs exceed maximum size");
1175       return NULL;
1176    }
1177
1178    prog_data->base.clip_distance_mask =
1179       ((1 << nir->info->clip_distance_array_size) - 1);
1180    prog_data->base.cull_distance_mask =
1181       ((1 << nir->info->cull_distance_array_size) - 1) <<
1182       nir->info->clip_distance_array_size;
1183
1184    /* URB entry sizes are stored as a multiple of 64 bytes. */
1185    prog_data->base.urb_entry_size = ALIGN(output_size_bytes, 64) / 64;
1186    prog_data->base.urb_read_length = 0;
1187
1188    STATIC_ASSERT(BRW_TESS_PARTITIONING_INTEGER == TESS_SPACING_EQUAL - 1);
1189    STATIC_ASSERT(BRW_TESS_PARTITIONING_ODD_FRACTIONAL ==
1190                  TESS_SPACING_FRACTIONAL_ODD - 1);
1191    STATIC_ASSERT(BRW_TESS_PARTITIONING_EVEN_FRACTIONAL ==
1192                  TESS_SPACING_FRACTIONAL_EVEN - 1);
1193
1194    prog_data->partitioning =
1195       (enum brw_tess_partitioning) (nir->info->tess.spacing - 1);
1196
1197    switch (nir->info->tess.primitive_mode) {
1198    case GL_QUADS:
1199       prog_data->domain = BRW_TESS_DOMAIN_QUAD;
1200       break;
1201    case GL_TRIANGLES:
1202       prog_data->domain = BRW_TESS_DOMAIN_TRI;
1203       break;
1204    case GL_ISOLINES:
1205       prog_data->domain = BRW_TESS_DOMAIN_ISOLINE;
1206       break;
1207    default:
1208       unreachable("invalid domain shader primitive mode");
1209    }
1210
1211    if (nir->info->tess.point_mode) {
1212       prog_data->output_topology = BRW_TESS_OUTPUT_TOPOLOGY_POINT;
1213    } else if (nir->info->tess.primitive_mode == GL_ISOLINES) {
1214       prog_data->output_topology = BRW_TESS_OUTPUT_TOPOLOGY_LINE;
1215    } else {
1216       /* Hardware winding order is backwards from OpenGL */
1217       prog_data->output_topology =
1218          nir->info->tess.ccw ? BRW_TESS_OUTPUT_TOPOLOGY_TRI_CW
1219                              : BRW_TESS_OUTPUT_TOPOLOGY_TRI_CCW;
1220    }
1221
1222    if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
1223       fprintf(stderr, "TES Input ");
1224       brw_print_vue_map(stderr, input_vue_map);
1225       fprintf(stderr, "TES Output ");
1226       brw_print_vue_map(stderr, &prog_data->base.vue_map);
1227    }
1228
1229    if (is_scalar) {
1230       fs_visitor v(compiler, log_data, mem_ctx, (void *) key,
1231                    &prog_data->base.base, NULL, nir, 8,
1232                    shader_time_index, input_vue_map);
1233       if (!v.run_tes()) {
1234          if (error_str)
1235             *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
1236          return NULL;
1237       }
1238
1239       prog_data->base.base.dispatch_grf_start_reg = v.payload.num_regs;
1240       prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8;
1241
1242       fs_generator g(compiler, log_data, mem_ctx, (void *) key,
1243                      &prog_data->base.base, v.promoted_constants, false,
1244                      MESA_SHADER_TESS_EVAL);
1245       if (unlikely(INTEL_DEBUG & DEBUG_TES)) {
1246          g.enable_debug(ralloc_asprintf(mem_ctx,
1247                                         "%s tessellation evaluation shader %s",
1248                                         nir->info->label ? nir->info->label
1249                                                         : "unnamed",
1250                                         nir->info->name));
1251       }
1252
1253       g.generate_code(v.cfg, 8);
1254
1255       return g.get_assembly(final_assembly_size);
1256    } else {
1257       brw::vec4_tes_visitor v(compiler, log_data, key, prog_data,
1258                               nir, mem_ctx, shader_time_index);
1259       if (!v.run()) {
1260          if (error_str)
1261             *error_str = ralloc_strdup(mem_ctx, v.fail_msg);
1262          return NULL;
1263       }
1264
1265       if (unlikely(INTEL_DEBUG & DEBUG_TES))
1266          v.dump_instructions();
1267
1268       return brw_vec4_generate_assembly(compiler, log_data, mem_ctx, nir,
1269                                         &prog_data->base, v.cfg,
1270                                         final_assembly_size);
1271    }
1272 }