src/mesa/drivers/dri/i965/brw_shader.cpp

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "main/macros.h"
  25 #include "brw_context.h"
  26 #include "brw_vs.h"
  27 #include "brw_gs.h"
  28 #include "brw_fs.h"
  29 #include "brw_cfg.h"
  30 #include "brw_nir.h"
  31 #include "glsl/ir_optimization.h"
  32 #include "glsl/glsl_parser_extras.h"
  33 #include "main/shaderapi.h"
  34
  35 static void
  36 shader_debug_log_mesa(void *data, const char *fmt, ...)
  37 {
  38    struct brw_context *brw = (struct brw_context *)data;
  39    va_list args;
  40
  41    va_start(args, fmt);
  42    GLuint msg_id = 0;
  43    _mesa_gl_vdebug(&brw->ctx, &msg_id,
  44                    MESA_DEBUG_SOURCE_SHADER_COMPILER,
  45                    MESA_DEBUG_TYPE_OTHER,
  46                    MESA_DEBUG_SEVERITY_NOTIFICATION, fmt, args);
  47    va_end(args);
  48 }
  49
  50 static void
  51 shader_perf_log_mesa(void *data, const char *fmt, ...)
  52 {
  53    struct brw_context *brw = (struct brw_context *)data;
  54
  55    va_list args;
  56    va_start(args, fmt);
  57
  58    if (unlikely(INTEL_DEBUG & DEBUG_PERF)) {
  59       va_list args_copy;
  60       va_copy(args_copy, args);
  61       vfprintf(stderr, fmt, args_copy);
  62       va_end(args_copy);
  63    }
  64
  65    if (brw->perf_debug) {
  66       GLuint msg_id = 0;
  67       _mesa_gl_vdebug(&brw->ctx, &msg_id,
  68                       MESA_DEBUG_SOURCE_SHADER_COMPILER,
  69                       MESA_DEBUG_TYPE_PERFORMANCE,
  70                       MESA_DEBUG_SEVERITY_MEDIUM, fmt, args);
  71    }
  72    va_end(args);
  73 }
  74
  75 bool
  76 is_scalar_shader_stage(const struct brw_compiler *compiler, int stage)
  77 {
  78    switch (stage) {
  79    case MESA_SHADER_FRAGMENT:
  80    case MESA_SHADER_COMPUTE:
  81       return true;
  82    case MESA_SHADER_GEOMETRY:
  83       return compiler->scalar_gs;
  84    case MESA_SHADER_VERTEX:
  85       return compiler->scalar_vs;
  86    default:
  87       return false;
  88    }
  89 }
  90
  91 struct brw_compiler *
  92 brw_compiler_create(void *mem_ctx, const struct brw_device_info *devinfo)
  93 {
  94    struct brw_compiler *compiler = rzalloc(mem_ctx, struct brw_compiler);
  95
  96    compiler->devinfo = devinfo;
  97    compiler->shader_debug_log = shader_debug_log_mesa;
  98    compiler->shader_perf_log = shader_perf_log_mesa;
  99
 100    brw_fs_alloc_reg_sets(compiler);
 101    brw_vec4_alloc_reg_set(compiler);
 102
 103    if (devinfo->gen >= 8 && !(INTEL_DEBUG & DEBUG_VEC4VS))
 104       compiler->scalar_vs = true;
 105
 106    if (devinfo->gen >= 8 && brw_env_var_as_boolean("INTEL_SCALAR_GS", false))
 107       compiler->scalar_gs = true;
 108
 109    nir_shader_compiler_options *nir_options =
 110       rzalloc(compiler, nir_shader_compiler_options);
 111    nir_options->native_integers = true;
 112    /* In order to help allow for better CSE at the NIR level we tell NIR
 113     * to split all ffma instructions during opt_algebraic and we then
 114     * re-combine them as a later step.
 115     */
 116    nir_options->lower_ffma = true;
 117    nir_options->lower_sub = true;
 118    /* In the vec4 backend, our dpN instruction replicates its result to all
 119     * the components of a vec4.  We would like NIR to give us replicated fdot
 120     * instructions because it can optimize better for us.
 121     *
 122     * For the FS backend, it should be lowered away by the scalarizing pass so
 123     * we should never see fdot anyway.
 124     */
 125    nir_options->fdot_replicates = true;
 126
 127    /* We want the GLSL compiler to emit code that uses condition codes */
 128    for (int i = 0; i < MESA_SHADER_STAGES; i++) {
 129       compiler->glsl_compiler_options[i].MaxUnrollIterations = 32;
 130       compiler->glsl_compiler_options[i].MaxIfDepth =
 131          devinfo->gen < 6 ? 16 : UINT_MAX;
 132
 133       compiler->glsl_compiler_options[i].EmitCondCodes = true;
 134       compiler->glsl_compiler_options[i].EmitNoNoise = true;
 135       compiler->glsl_compiler_options[i].EmitNoMainReturn = true;
 136       compiler->glsl_compiler_options[i].EmitNoIndirectInput = true;
 137       compiler->glsl_compiler_options[i].EmitNoIndirectUniform = false;
 138       compiler->glsl_compiler_options[i].LowerClipDistance = true;
 139
 140       bool is_scalar = is_scalar_shader_stage(compiler, i);
 141
 142       compiler->glsl_compiler_options[i].EmitNoIndirectOutput = is_scalar;
 143       compiler->glsl_compiler_options[i].EmitNoIndirectTemp = is_scalar;
 144       compiler->glsl_compiler_options[i].OptimizeForAOS = !is_scalar;
 145
 146       /* !ARB_gpu_shader5 */
 147       if (devinfo->gen < 7)
 148          compiler->glsl_compiler_options[i].EmitNoIndirectSampler = true;
 149
 150       compiler->glsl_compiler_options[i].NirOptions = nir_options;
 151    }
 152
 153    return compiler;
 154 }
 155
 156 struct gl_shader *
 157 brw_new_shader(struct gl_context *ctx, GLuint name, GLuint type)
 158 {
 159    struct brw_shader *shader;
 160
 161    shader = rzalloc(NULL, struct brw_shader);
 162    if (shader) {
 163       shader->base.Type = type;
 164       shader->base.Stage = _mesa_shader_enum_to_shader_stage(type);
 165       shader->base.Name = name;
 166       _mesa_init_shader(ctx, &shader->base);
 167    }
 168
 169    return &shader->base;
 170 }
 171
 172 void
 173 brw_mark_surface_used(struct brw_stage_prog_data *prog_data,
 174                       unsigned surf_index)
 175 {
 176    assert(surf_index < BRW_MAX_SURFACES);
 177
 178    prog_data->binding_table.size_bytes =
 179       MAX2(prog_data->binding_table.size_bytes, (surf_index + 1) * 4);
 180 }
 181
 182 enum brw_reg_type
 183 brw_type_for_base_type(const struct glsl_type *type)
 184 {
 185    switch (type->base_type) {
 186    case GLSL_TYPE_FLOAT:
 187       return BRW_REGISTER_TYPE_F;
 188    case GLSL_TYPE_INT:
 189    case GLSL_TYPE_BOOL:
 190    case GLSL_TYPE_SUBROUTINE:
 191       return BRW_REGISTER_TYPE_D;
 192    case GLSL_TYPE_UINT:
 193       return BRW_REGISTER_TYPE_UD;
 194    case GLSL_TYPE_ARRAY:
 195       return brw_type_for_base_type(type->fields.array);
 196    case GLSL_TYPE_STRUCT:
 197    case GLSL_TYPE_SAMPLER:
 198    case GLSL_TYPE_ATOMIC_UINT:
 199       /* These should be overridden with the type of the member when
 200        * dereferenced into.  BRW_REGISTER_TYPE_UD seems like a likely
 201        * way to trip up if we don't.
 202        */
 203       return BRW_REGISTER_TYPE_UD;
 204    case GLSL_TYPE_IMAGE:
 205       return BRW_REGISTER_TYPE_UD;
 206    case GLSL_TYPE_VOID:
 207    case GLSL_TYPE_ERROR:
 208    case GLSL_TYPE_INTERFACE:
 209    case GLSL_TYPE_DOUBLE:
 210       unreachable("not reached");
 211    }
 212
 213    return BRW_REGISTER_TYPE_F;
 214 }
 215
 216 enum brw_conditional_mod
 217 brw_conditional_for_comparison(unsigned int op)
 218 {
 219    switch (op) {
 220    case ir_binop_less:
 221       return BRW_CONDITIONAL_L;
 222    case ir_binop_greater:
 223       return BRW_CONDITIONAL_G;
 224    case ir_binop_lequal:
 225       return BRW_CONDITIONAL_LE;
 226    case ir_binop_gequal:
 227       return BRW_CONDITIONAL_GE;
 228    case ir_binop_equal:
 229    case ir_binop_all_equal: /* same as equal for scalars */
 230       return BRW_CONDITIONAL_Z;
 231    case ir_binop_nequal:
 232    case ir_binop_any_nequal: /* same as nequal for scalars */
 233       return BRW_CONDITIONAL_NZ;
 234    default:
 235       unreachable("not reached: bad operation for comparison");
 236    }
 237 }
 238
 239 uint32_t
 240 brw_math_function(enum opcode op)
 241 {
 242    switch (op) {
 243    case SHADER_OPCODE_RCP:
 244       return BRW_MATH_FUNCTION_INV;
 245    case SHADER_OPCODE_RSQ:
 246       return BRW_MATH_FUNCTION_RSQ;
 247    case SHADER_OPCODE_SQRT:
 248       return BRW_MATH_FUNCTION_SQRT;
 249    case SHADER_OPCODE_EXP2:
 250       return BRW_MATH_FUNCTION_EXP;
 251    case SHADER_OPCODE_LOG2:
 252       return BRW_MATH_FUNCTION_LOG;
 253    case SHADER_OPCODE_POW:
 254       return BRW_MATH_FUNCTION_POW;
 255    case SHADER_OPCODE_SIN:
 256       return BRW_MATH_FUNCTION_SIN;
 257    case SHADER_OPCODE_COS:
 258       return BRW_MATH_FUNCTION_COS;
 259    case SHADER_OPCODE_INT_QUOTIENT:
 260       return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT;
 261    case SHADER_OPCODE_INT_REMAINDER:
 262       return BRW_MATH_FUNCTION_INT_DIV_REMAINDER;
 263    default:
 264       unreachable("not reached: unknown math function");
 265    }
 266 }
 267
 268 uint32_t
 269 brw_texture_offset(int *offsets, unsigned num_components)
 270 {
 271    if (!offsets) return 0;  /* nonconstant offset; caller will handle it. */
 272
 273    /* Combine all three offsets into a single unsigned dword:
 274     *
 275     *    bits 11:8 - U Offset (X component)
 276     *    bits  7:4 - V Offset (Y component)
 277     *    bits  3:0 - R Offset (Z component)
 278     */
 279    unsigned offset_bits = 0;
 280    for (unsigned i = 0; i < num_components; i++) {
 281       const unsigned shift = 4 * (2 - i);
 282       offset_bits |= (offsets[i] << shift) & (0xF << shift);
 283    }
 284    return offset_bits;
 285 }
 286
 287 const char *
 288 brw_instruction_name(enum opcode op)
 289 {
 290    switch (op) {
 291    case BRW_OPCODE_MOV ... BRW_OPCODE_NOP:
 292       assert(opcode_descs[op].name);
 293       return opcode_descs[op].name;
 294    case FS_OPCODE_FB_WRITE:
 295       return "fb_write";
 296    case FS_OPCODE_FB_WRITE_LOGICAL:
 297       return "fb_write_logical";
 298    case FS_OPCODE_PACK_STENCIL_REF:
 299       return "pack_stencil_ref";
 300    case FS_OPCODE_BLORP_FB_WRITE:
 301       return "blorp_fb_write";
 302    case FS_OPCODE_REP_FB_WRITE:
 303       return "rep_fb_write";
 304
 305    case SHADER_OPCODE_RCP:
 306       return "rcp";
 307    case SHADER_OPCODE_RSQ:
 308       return "rsq";
 309    case SHADER_OPCODE_SQRT:
 310       return "sqrt";
 311    case SHADER_OPCODE_EXP2:
 312       return "exp2";
 313    case SHADER_OPCODE_LOG2:
 314       return "log2";
 315    case SHADER_OPCODE_POW:
 316       return "pow";
 317    case SHADER_OPCODE_INT_QUOTIENT:
 318       return "int_quot";
 319    case SHADER_OPCODE_INT_REMAINDER:
 320       return "int_rem";
 321    case SHADER_OPCODE_SIN:
 322       return "sin";
 323    case SHADER_OPCODE_COS:
 324       return "cos";
 325
 326    case SHADER_OPCODE_TEX:
 327       return "tex";
 328    case SHADER_OPCODE_TEX_LOGICAL:
 329       return "tex_logical";
 330    case SHADER_OPCODE_TXD:
 331       return "txd";
 332    case SHADER_OPCODE_TXD_LOGICAL:
 333       return "txd_logical";
 334    case SHADER_OPCODE_TXF:
 335       return "txf";
 336    case SHADER_OPCODE_TXF_LOGICAL:
 337       return "txf_logical";
 338    case SHADER_OPCODE_TXL:
 339       return "txl";
 340    case SHADER_OPCODE_TXL_LOGICAL:
 341       return "txl_logical";
 342    case SHADER_OPCODE_TXS:
 343       return "txs";
 344    case SHADER_OPCODE_TXS_LOGICAL:
 345       return "txs_logical";
 346    case FS_OPCODE_TXB:
 347       return "txb";
 348    case FS_OPCODE_TXB_LOGICAL:
 349       return "txb_logical";
 350    case SHADER_OPCODE_TXF_CMS:
 351       return "txf_cms";
 352    case SHADER_OPCODE_TXF_CMS_LOGICAL:
 353       return "txf_cms_logical";
 354    case SHADER_OPCODE_TXF_UMS:
 355       return "txf_ums";
 356    case SHADER_OPCODE_TXF_UMS_LOGICAL:
 357       return "txf_ums_logical";
 358    case SHADER_OPCODE_TXF_MCS:
 359       return "txf_mcs";
 360    case SHADER_OPCODE_TXF_MCS_LOGICAL:
 361       return "txf_mcs_logical";
 362    case SHADER_OPCODE_LOD:
 363       return "lod";
 364    case SHADER_OPCODE_LOD_LOGICAL:
 365       return "lod_logical";
 366    case SHADER_OPCODE_TG4:
 367       return "tg4";
 368    case SHADER_OPCODE_TG4_LOGICAL:
 369       return "tg4_logical";
 370    case SHADER_OPCODE_TG4_OFFSET:
 371       return "tg4_offset";
 372    case SHADER_OPCODE_TG4_OFFSET_LOGICAL:
 373       return "tg4_offset_logical";
 374    case SHADER_OPCODE_SAMPLEINFO:
 375       return "sampleinfo";
 376
 377    case SHADER_OPCODE_SHADER_TIME_ADD:
 378       return "shader_time_add";
 379
 380    case SHADER_OPCODE_UNTYPED_ATOMIC:
 381       return "untyped_atomic";
 382    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
 383       return "untyped_atomic_logical";
 384    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
 385       return "untyped_surface_read";
 386    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
 387       return "untyped_surface_read_logical";
 388    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
 389       return "untyped_surface_write";
 390    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
 391       return "untyped_surface_write_logical";
 392    case SHADER_OPCODE_TYPED_ATOMIC:
 393       return "typed_atomic";
 394    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
 395       return "typed_atomic_logical";
 396    case SHADER_OPCODE_TYPED_SURFACE_READ:
 397       return "typed_surface_read";
 398    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
 399       return "typed_surface_read_logical";
 400    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
 401       return "typed_surface_write";
 402    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
 403       return "typed_surface_write_logical";
 404    case SHADER_OPCODE_MEMORY_FENCE:
 405       return "memory_fence";
 406
 407    case SHADER_OPCODE_LOAD_PAYLOAD:
 408       return "load_payload";
 409
 410    case SHADER_OPCODE_GEN4_SCRATCH_READ:
 411       return "gen4_scratch_read";
 412    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 413       return "gen4_scratch_write";
 414    case SHADER_OPCODE_GEN7_SCRATCH_READ:
 415       return "gen7_scratch_read";
 416    case SHADER_OPCODE_URB_WRITE_SIMD8:
 417       return "gen8_urb_write_simd8";
 418    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
 419       return "gen8_urb_write_simd8_per_slot";
 420    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
 421       return "gen8_urb_write_simd8_masked";
 422    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
 423       return "gen8_urb_write_simd8_masked_per_slot";
 424    case SHADER_OPCODE_URB_READ_SIMD8:
 425       return "urb_read_simd8";
 426
 427    case SHADER_OPCODE_FIND_LIVE_CHANNEL:
 428       return "find_live_channel";
 429    case SHADER_OPCODE_BROADCAST:
 430       return "broadcast";
 431
 432    case VEC4_OPCODE_MOV_BYTES:
 433       return "mov_bytes";
 434    case VEC4_OPCODE_PACK_BYTES:
 435       return "pack_bytes";
 436    case VEC4_OPCODE_UNPACK_UNIFORM:
 437       return "unpack_uniform";
 438
 439    case FS_OPCODE_DDX_COARSE:
 440       return "ddx_coarse";
 441    case FS_OPCODE_DDX_FINE:
 442       return "ddx_fine";
 443    case FS_OPCODE_DDY_COARSE:
 444       return "ddy_coarse";
 445    case FS_OPCODE_DDY_FINE:
 446       return "ddy_fine";
 447
 448    case FS_OPCODE_CINTERP:
 449       return "cinterp";
 450    case FS_OPCODE_LINTERP:
 451       return "linterp";
 452
 453    case FS_OPCODE_PIXEL_X:
 454       return "pixel_x";
 455    case FS_OPCODE_PIXEL_Y:
 456       return "pixel_y";
 457
 458    case FS_OPCODE_GET_BUFFER_SIZE:
 459       return "fs_get_buffer_size";
 460
 461    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
 462       return "uniform_pull_const";
 463    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
 464       return "uniform_pull_const_gen7";
 465    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
 466       return "varying_pull_const";
 467    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
 468       return "varying_pull_const_gen7";
 469
 470    case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
 471       return "mov_dispatch_to_flags";
 472    case FS_OPCODE_DISCARD_JUMP:
 473       return "discard_jump";
 474
 475    case FS_OPCODE_SET_SAMPLE_ID:
 476       return "set_sample_id";
 477    case FS_OPCODE_SET_SIMD4X2_OFFSET:
 478       return "set_simd4x2_offset";
 479
 480    case FS_OPCODE_PACK_HALF_2x16_SPLIT:
 481       return "pack_half_2x16_split";
 482    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
 483       return "unpack_half_2x16_split_x";
 484    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
 485       return "unpack_half_2x16_split_y";
 486
 487    case FS_OPCODE_PLACEHOLDER_HALT:
 488       return "placeholder_halt";
 489
 490    case FS_OPCODE_INTERPOLATE_AT_CENTROID:
 491       return "interp_centroid";
 492    case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
 493       return "interp_sample";
 494    case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
 495       return "interp_shared_offset";
 496    case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
 497       return "interp_per_slot_offset";
 498
 499    case VS_OPCODE_URB_WRITE:
 500       return "vs_urb_write";
 501    case VS_OPCODE_PULL_CONSTANT_LOAD:
 502       return "pull_constant_load";
 503    case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
 504       return "pull_constant_load_gen7";
 505
 506    case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
 507       return "set_simd4x2_header_gen9";
 508
 509    case VS_OPCODE_GET_BUFFER_SIZE:
 510       return "vs_get_buffer_size";
 511
 512    case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
 513       return "unpack_flags_simd4x2";
 514
 515    case GS_OPCODE_URB_WRITE:
 516       return "gs_urb_write";
 517    case GS_OPCODE_URB_WRITE_ALLOCATE:
 518       return "gs_urb_write_allocate";
 519    case GS_OPCODE_THREAD_END:
 520       return "gs_thread_end";
 521    case GS_OPCODE_SET_WRITE_OFFSET:
 522       return "set_write_offset";
 523    case GS_OPCODE_SET_VERTEX_COUNT:
 524       return "set_vertex_count";
 525    case GS_OPCODE_SET_DWORD_2:
 526       return "set_dword_2";
 527    case GS_OPCODE_PREPARE_CHANNEL_MASKS:
 528       return "prepare_channel_masks";
 529    case GS_OPCODE_SET_CHANNEL_MASKS:
 530       return "set_channel_masks";
 531    case GS_OPCODE_GET_INSTANCE_ID:
 532       return "get_instance_id";
 533    case GS_OPCODE_FF_SYNC:
 534       return "ff_sync";
 535    case GS_OPCODE_SET_PRIMITIVE_ID:
 536       return "set_primitive_id";
 537    case GS_OPCODE_SVB_WRITE:
 538       return "gs_svb_write";
 539    case GS_OPCODE_SVB_SET_DST_INDEX:
 540       return "gs_svb_set_dst_index";
 541    case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
 542       return "gs_ff_sync_set_primitives";
 543    case CS_OPCODE_CS_TERMINATE:
 544       return "cs_terminate";
 545    case SHADER_OPCODE_BARRIER:
 546       return "barrier";
 547    case SHADER_OPCODE_MULH:
 548       return "mulh";
 549    }
 550
 551    unreachable("not reached");
 552 }
 553
 554 bool
 555 brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 556 {
 557    union {
 558       unsigned ud;
 559       int d;
 560       float f;
 561    } imm = { reg->dw1.ud }, sat_imm = { 0 };
 562
 563    switch (type) {
 564    case BRW_REGISTER_TYPE_UD:
 565    case BRW_REGISTER_TYPE_D:
 566    case BRW_REGISTER_TYPE_UQ:
 567    case BRW_REGISTER_TYPE_Q:
 568       /* Nothing to do. */
 569       return false;
 570    case BRW_REGISTER_TYPE_UW:
 571       sat_imm.ud = CLAMP(imm.ud, 0, USHRT_MAX);
 572       break;
 573    case BRW_REGISTER_TYPE_W:
 574       sat_imm.d = CLAMP(imm.d, SHRT_MIN, SHRT_MAX);
 575       break;
 576    case BRW_REGISTER_TYPE_F:
 577       sat_imm.f = CLAMP(imm.f, 0.0f, 1.0f);
 578       break;
 579    case BRW_REGISTER_TYPE_UB:
 580    case BRW_REGISTER_TYPE_B:
 581       unreachable("no UB/B immediates");
 582    case BRW_REGISTER_TYPE_V:
 583    case BRW_REGISTER_TYPE_UV:
 584    case BRW_REGISTER_TYPE_VF:
 585       unreachable("unimplemented: saturate vector immediate");
 586    case BRW_REGISTER_TYPE_DF:
 587    case BRW_REGISTER_TYPE_HF:
 588       unreachable("unimplemented: saturate DF/HF immediate");
 589    }
 590
 591    if (imm.ud != sat_imm.ud) {
 592       reg->dw1.ud = sat_imm.ud;
 593       return true;
 594    }
 595    return false;
 596 }
 597
 598 bool
 599 brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 600 {
 601    switch (type) {
 602    case BRW_REGISTER_TYPE_D:
 603    case BRW_REGISTER_TYPE_UD:
 604       reg->dw1.d = -reg->dw1.d;
 605       return true;
 606    case BRW_REGISTER_TYPE_W:
 607    case BRW_REGISTER_TYPE_UW:
 608       reg->dw1.d = -(int16_t)reg->dw1.ud;
 609       return true;
 610    case BRW_REGISTER_TYPE_F:
 611       reg->dw1.f = -reg->dw1.f;
 612       return true;
 613    case BRW_REGISTER_TYPE_VF:
 614       reg->dw1.ud ^= 0x80808080;
 615       return true;
 616    case BRW_REGISTER_TYPE_UB:
 617    case BRW_REGISTER_TYPE_B:
 618       unreachable("no UB/B immediates");
 619    case BRW_REGISTER_TYPE_UV:
 620    case BRW_REGISTER_TYPE_V:
 621       assert(!"unimplemented: negate UV/V immediate");
 622    case BRW_REGISTER_TYPE_UQ:
 623    case BRW_REGISTER_TYPE_Q:
 624       assert(!"unimplemented: negate UQ/Q immediate");
 625    case BRW_REGISTER_TYPE_DF:
 626    case BRW_REGISTER_TYPE_HF:
 627       assert(!"unimplemented: negate DF/HF immediate");
 628    }
 629
 630    return false;
 631 }
 632
 633 bool
 634 brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg)
 635 {
 636    switch (type) {
 637    case BRW_REGISTER_TYPE_D:
 638       reg->dw1.d = abs(reg->dw1.d);
 639       return true;
 640    case BRW_REGISTER_TYPE_W:
 641       reg->dw1.d = abs((int16_t)reg->dw1.ud);
 642       return true;
 643    case BRW_REGISTER_TYPE_F:
 644       reg->dw1.f = fabsf(reg->dw1.f);
 645       return true;
 646    case BRW_REGISTER_TYPE_VF:
 647       reg->dw1.ud &= ~0x80808080;
 648       return true;
 649    case BRW_REGISTER_TYPE_UB:
 650    case BRW_REGISTER_TYPE_B:
 651       unreachable("no UB/B immediates");
 652    case BRW_REGISTER_TYPE_UQ:
 653    case BRW_REGISTER_TYPE_UD:
 654    case BRW_REGISTER_TYPE_UW:
 655    case BRW_REGISTER_TYPE_UV:
 656       /* Presumably the absolute value modifier on an unsigned source is a
 657        * nop, but it would be nice to confirm.
 658        */
 659       assert(!"unimplemented: abs unsigned immediate");
 660    case BRW_REGISTER_TYPE_V:
 661       assert(!"unimplemented: abs V immediate");
 662    case BRW_REGISTER_TYPE_Q:
 663       assert(!"unimplemented: abs Q immediate");
 664    case BRW_REGISTER_TYPE_DF:
 665    case BRW_REGISTER_TYPE_HF:
 666       assert(!"unimplemented: abs DF/HF immediate");
 667    }
 668
 669    return false;
 670 }
 671
 672 backend_shader::backend_shader(const struct brw_compiler *compiler,
 673                                void *log_data,
 674                                void *mem_ctx,
 675                                const nir_shader *shader,
 676                                struct brw_stage_prog_data *stage_prog_data)
 677    : compiler(compiler),
 678      log_data(log_data),
 679      devinfo(compiler->devinfo),
 680      nir(shader),
 681      stage_prog_data(stage_prog_data),
 682      mem_ctx(mem_ctx),
 683      cfg(NULL),
 684      stage(shader->stage)
 685 {
 686    debug_enabled = INTEL_DEBUG & intel_debug_flag_for_shader_stage(stage);
 687    stage_name = _mesa_shader_stage_to_string(stage);
 688    stage_abbrev = _mesa_shader_stage_to_abbrev(stage);
 689 }
 690
 691 bool
 692 backend_reg::is_zero() const
 693 {
 694    if (file != IMM)
 695       return false;
 696
 697    return fixed_hw_reg.dw1.d == 0;
 698 }
 699
 700 bool
 701 backend_reg::is_one() const
 702 {
 703    if (file != IMM)
 704       return false;
 705
 706    return type == BRW_REGISTER_TYPE_F
 707           ? fixed_hw_reg.dw1.f == 1.0
 708           : fixed_hw_reg.dw1.d == 1;
 709 }
 710
 711 bool
 712 backend_reg::is_negative_one() const
 713 {
 714    if (file != IMM)
 715       return false;
 716
 717    switch (type) {
 718    case BRW_REGISTER_TYPE_F:
 719       return fixed_hw_reg.dw1.f == -1.0;
 720    case BRW_REGISTER_TYPE_D:
 721       return fixed_hw_reg.dw1.d == -1;
 722    default:
 723       return false;
 724    }
 725 }
 726
 727 bool
 728 backend_reg::is_null() const
 729 {
 730    return file == HW_REG &&
 731           fixed_hw_reg.file == BRW_ARCHITECTURE_REGISTER_FILE &&
 732           fixed_hw_reg.nr == BRW_ARF_NULL;
 733 }
 734
 735
 736 bool
 737 backend_reg::is_accumulator() const
 738 {
 739    return file == HW_REG &&
 740           fixed_hw_reg.file == BRW_ARCHITECTURE_REGISTER_FILE &&
 741           fixed_hw_reg.nr == BRW_ARF_ACCUMULATOR;
 742 }
 743
 744 bool
 745 backend_reg::in_range(const backend_reg &r, unsigned n) const
 746 {
 747    return (file == r.file &&
 748            reg == r.reg &&
 749            reg_offset >= r.reg_offset &&
 750            reg_offset < r.reg_offset + n);
 751 }
 752
 753 bool
 754 backend_instruction::is_commutative() const
 755 {
 756    switch (opcode) {
 757    case BRW_OPCODE_AND:
 758    case BRW_OPCODE_OR:
 759    case BRW_OPCODE_XOR:
 760    case BRW_OPCODE_ADD:
 761    case BRW_OPCODE_MUL:
 762    case SHADER_OPCODE_MULH:
 763       return true;
 764    case BRW_OPCODE_SEL:
 765       /* MIN and MAX are commutative. */
 766       if (conditional_mod == BRW_CONDITIONAL_GE ||
 767           conditional_mod == BRW_CONDITIONAL_L) {
 768          return true;
 769       }
 770       /* fallthrough */
 771    default:
 772       return false;
 773    }
 774 }
 775
 776 bool
 777 backend_instruction::is_3src() const
 778 {
 779    return opcode < ARRAY_SIZE(opcode_descs) && opcode_descs[opcode].nsrc == 3;
 780 }
 781
 782 bool
 783 backend_instruction::is_tex() const
 784 {
 785    return (opcode == SHADER_OPCODE_TEX ||
 786            opcode == FS_OPCODE_TXB ||
 787            opcode == SHADER_OPCODE_TXD ||
 788            opcode == SHADER_OPCODE_TXF ||
 789            opcode == SHADER_OPCODE_TXF_CMS ||
 790            opcode == SHADER_OPCODE_TXF_UMS ||
 791            opcode == SHADER_OPCODE_TXF_MCS ||
 792            opcode == SHADER_OPCODE_TXL ||
 793            opcode == SHADER_OPCODE_TXS ||
 794            opcode == SHADER_OPCODE_LOD ||
 795            opcode == SHADER_OPCODE_TG4 ||
 796            opcode == SHADER_OPCODE_TG4_OFFSET);
 797 }
 798
 799 bool
 800 backend_instruction::is_math() const
 801 {
 802    return (opcode == SHADER_OPCODE_RCP ||
 803            opcode == SHADER_OPCODE_RSQ ||
 804            opcode == SHADER_OPCODE_SQRT ||
 805            opcode == SHADER_OPCODE_EXP2 ||
 806            opcode == SHADER_OPCODE_LOG2 ||
 807            opcode == SHADER_OPCODE_SIN ||
 808            opcode == SHADER_OPCODE_COS ||
 809            opcode == SHADER_OPCODE_INT_QUOTIENT ||
 810            opcode == SHADER_OPCODE_INT_REMAINDER ||
 811            opcode == SHADER_OPCODE_POW);
 812 }
 813
 814 bool
 815 backend_instruction::is_control_flow() const
 816 {
 817    switch (opcode) {
 818    case BRW_OPCODE_DO:
 819    case BRW_OPCODE_WHILE:
 820    case BRW_OPCODE_IF:
 821    case BRW_OPCODE_ELSE:
 822    case BRW_OPCODE_ENDIF:
 823    case BRW_OPCODE_BREAK:
 824    case BRW_OPCODE_CONTINUE:
 825       return true;
 826    default:
 827       return false;
 828    }
 829 }
 830
 831 bool
 832 backend_instruction::can_do_source_mods() const
 833 {
 834    switch (opcode) {
 835    case BRW_OPCODE_ADDC:
 836    case BRW_OPCODE_BFE:
 837    case BRW_OPCODE_BFI1:
 838    case BRW_OPCODE_BFI2:
 839    case BRW_OPCODE_BFREV:
 840    case BRW_OPCODE_CBIT:
 841    case BRW_OPCODE_FBH:
 842    case BRW_OPCODE_FBL:
 843    case BRW_OPCODE_SUBB:
 844       return false;
 845    default:
 846       return true;
 847    }
 848 }
 849
 850 bool
 851 backend_instruction::can_do_saturate() const
 852 {
 853    switch (opcode) {
 854    case BRW_OPCODE_ADD:
 855    case BRW_OPCODE_ASR:
 856    case BRW_OPCODE_AVG:
 857    case BRW_OPCODE_DP2:
 858    case BRW_OPCODE_DP3:
 859    case BRW_OPCODE_DP4:
 860    case BRW_OPCODE_DPH:
 861    case BRW_OPCODE_F16TO32:
 862    case BRW_OPCODE_F32TO16:
 863    case BRW_OPCODE_LINE:
 864    case BRW_OPCODE_LRP:
 865    case BRW_OPCODE_MAC:
 866    case BRW_OPCODE_MAD:
 867    case BRW_OPCODE_MATH:
 868    case BRW_OPCODE_MOV:
 869    case BRW_OPCODE_MUL:
 870    case SHADER_OPCODE_MULH:
 871    case BRW_OPCODE_PLN:
 872    case BRW_OPCODE_RNDD:
 873    case BRW_OPCODE_RNDE:
 874    case BRW_OPCODE_RNDU:
 875    case BRW_OPCODE_RNDZ:
 876    case BRW_OPCODE_SEL:
 877    case BRW_OPCODE_SHL:
 878    case BRW_OPCODE_SHR:
 879    case FS_OPCODE_LINTERP:
 880    case SHADER_OPCODE_COS:
 881    case SHADER_OPCODE_EXP2:
 882    case SHADER_OPCODE_LOG2:
 883    case SHADER_OPCODE_POW:
 884    case SHADER_OPCODE_RCP:
 885    case SHADER_OPCODE_RSQ:
 886    case SHADER_OPCODE_SIN:
 887    case SHADER_OPCODE_SQRT:
 888       return true;
 889    default:
 890       return false;
 891    }
 892 }
 893
 894 bool
 895 backend_instruction::can_do_cmod() const
 896 {
 897    switch (opcode) {
 898    case BRW_OPCODE_ADD:
 899    case BRW_OPCODE_ADDC:
 900    case BRW_OPCODE_AND:
 901    case BRW_OPCODE_ASR:
 902    case BRW_OPCODE_AVG:
 903    case BRW_OPCODE_CMP:
 904    case BRW_OPCODE_CMPN:
 905    case BRW_OPCODE_DP2:
 906    case BRW_OPCODE_DP3:
 907    case BRW_OPCODE_DP4:
 908    case BRW_OPCODE_DPH:
 909    case BRW_OPCODE_F16TO32:
 910    case BRW_OPCODE_F32TO16:
 911    case BRW_OPCODE_FRC:
 912    case BRW_OPCODE_LINE:
 913    case BRW_OPCODE_LRP:
 914    case BRW_OPCODE_LZD:
 915    case BRW_OPCODE_MAC:
 916    case BRW_OPCODE_MACH:
 917    case BRW_OPCODE_MAD:
 918    case BRW_OPCODE_MOV:
 919    case BRW_OPCODE_MUL:
 920    case BRW_OPCODE_NOT:
 921    case BRW_OPCODE_OR:
 922    case BRW_OPCODE_PLN:
 923    case BRW_OPCODE_RNDD:
 924    case BRW_OPCODE_RNDE:
 925    case BRW_OPCODE_RNDU:
 926    case BRW_OPCODE_RNDZ:
 927    case BRW_OPCODE_SAD2:
 928    case BRW_OPCODE_SADA2:
 929    case BRW_OPCODE_SHL:
 930    case BRW_OPCODE_SHR:
 931    case BRW_OPCODE_SUBB:
 932    case BRW_OPCODE_XOR:
 933    case FS_OPCODE_CINTERP:
 934    case FS_OPCODE_LINTERP:
 935       return true;
 936    default:
 937       return false;
 938    }
 939 }
 940
 941 bool
 942 backend_instruction::reads_accumulator_implicitly() const
 943 {
 944    switch (opcode) {
 945    case BRW_OPCODE_MAC:
 946    case BRW_OPCODE_MACH:
 947    case BRW_OPCODE_SADA2:
 948       return true;
 949    default:
 950       return false;
 951    }
 952 }
 953
 954 bool
 955 backend_instruction::writes_accumulator_implicitly(const struct brw_device_info *devinfo) const
 956 {
 957    return writes_accumulator ||
 958           (devinfo->gen < 6 &&
 959            ((opcode >= BRW_OPCODE_ADD && opcode < BRW_OPCODE_NOP) ||
 960             (opcode >= FS_OPCODE_DDX_COARSE && opcode <= FS_OPCODE_LINTERP &&
 961              opcode != FS_OPCODE_CINTERP)));
 962 }
 963
 964 bool
 965 backend_instruction::has_side_effects() const
 966 {
 967    switch (opcode) {
 968    case SHADER_OPCODE_UNTYPED_ATOMIC:
 969    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
 970    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 971    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
 972    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
 973    case SHADER_OPCODE_TYPED_ATOMIC:
 974    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
 975    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
 976    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
 977    case SHADER_OPCODE_MEMORY_FENCE:
 978    case SHADER_OPCODE_URB_WRITE_SIMD8:
 979    case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
 980    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
 981    case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
 982    case FS_OPCODE_FB_WRITE:
 983    case SHADER_OPCODE_BARRIER:
 984       return true;
 985    default:
 986       return false;
 987    }
 988 }
 989
 990 #ifndef NDEBUG
 991 static bool
 992 inst_is_in_block(const bblock_t *block, const backend_instruction *inst)
 993 {
 994    bool found = false;
 995    foreach_inst_in_block (backend_instruction, i, block) {
 996       if (inst == i) {
 997          found = true;
 998       }
 999    }
1000    return found;
1001 }
1002 #endif
1003
1004 static void
1005 adjust_later_block_ips(bblock_t *start_block, int ip_adjustment)
1006 {
1007    for (bblock_t *block_iter = start_block->next();
1008         !block_iter->link.is_tail_sentinel();
1009         block_iter = block_iter->next()) {
1010       block_iter->start_ip += ip_adjustment;
1011       block_iter->end_ip += ip_adjustment;
1012    }
1013 }
1014
1015 void
1016 backend_instruction::insert_after(bblock_t *block, backend_instruction *inst)
1017 {
1018    if (!this->is_head_sentinel())
1019       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1020
1021    block->end_ip++;
1022
1023    adjust_later_block_ips(block, 1);
1024
1025    exec_node::insert_after(inst);
1026 }
1027
1028 void
1029 backend_instruction::insert_before(bblock_t *block, backend_instruction *inst)
1030 {
1031    if (!this->is_tail_sentinel())
1032       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1033
1034    block->end_ip++;
1035
1036    adjust_later_block_ips(block, 1);
1037
1038    exec_node::insert_before(inst);
1039 }
1040
1041 void
1042 backend_instruction::insert_before(bblock_t *block, exec_list *list)
1043 {
1044    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1045
1046    unsigned num_inst = list->length();
1047
1048    block->end_ip += num_inst;
1049
1050    adjust_later_block_ips(block, num_inst);
1051
1052    exec_node::insert_before(list);
1053 }
1054
1055 void
1056 backend_instruction::remove(bblock_t *block)
1057 {
1058    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1059
1060    adjust_later_block_ips(block, -1);
1061
1062    if (block->start_ip == block->end_ip) {
1063       block->cfg->remove_block(block);
1064    } else {
1065       block->end_ip--;
1066    }
1067
1068    exec_node::remove();
1069 }
1070
1071 void
1072 backend_shader::dump_instructions()
1073 {
1074    dump_instructions(NULL);
1075 }
1076
1077 void
1078 backend_shader::dump_instructions(const char *name)
1079 {
1080    FILE *file = stderr;
1081    if (name && geteuid() != 0) {
1082       file = fopen(name, "w");
1083       if (!file)
1084          file = stderr;
1085    }
1086
1087    if (cfg) {
1088       int ip = 0;
1089       foreach_block_and_inst(block, backend_instruction, inst, cfg) {
1090          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1091             fprintf(file, "%4d: ", ip++);
1092          dump_instruction(inst, file);
1093       }
1094    } else {
1095       int ip = 0;
1096       foreach_in_list(backend_instruction, inst, &instructions) {
1097          if (!unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER))
1098             fprintf(file, "%4d: ", ip++);
1099          dump_instruction(inst, file);
1100       }
1101    }
1102
1103    if (file != stderr) {
1104       fclose(file);
1105    }
1106 }
1107
1108 void
1109 backend_shader::calculate_cfg()
1110 {
1111    if (this->cfg)
1112       return;
1113    cfg = new(mem_ctx) cfg_t(&this->instructions);
1114 }
1115
1116 void
1117 backend_shader::invalidate_cfg()
1118 {
1119    ralloc_free(this->cfg);
1120    this->cfg = NULL;
1121 }
1122
1123 /**
1124  * Sets up the starting offsets for the groups of binding table entries
1125  * commong to all pipeline stages.
1126  *
1127  * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
1128  * unused but also make sure that addition of small offsets to them will
1129  * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
1130  */
1131 void
1132 brw_assign_common_binding_table_offsets(gl_shader_stage stage,
1133                                         const struct brw_device_info *devinfo,
1134                                         const struct gl_shader_program *shader_prog,
1135                                         const struct gl_program *prog,
1136                                         struct brw_stage_prog_data *stage_prog_data,
1137                                         uint32_t next_binding_table_offset)
1138 {
1139    const struct gl_shader *shader = NULL;
1140    int num_textures = _mesa_fls(prog->SamplersUsed);
1141
1142    if (shader_prog)
1143       shader = shader_prog->_LinkedShaders[stage];
1144
1145    stage_prog_data->binding_table.texture_start = next_binding_table_offset;
1146    next_binding_table_offset += num_textures;
1147
1148    if (shader) {
1149       assert(shader->NumUniformBlocks <= BRW_MAX_UBO);
1150       stage_prog_data->binding_table.ubo_start = next_binding_table_offset;
1151       next_binding_table_offset += shader->NumUniformBlocks;
1152
1153       assert(shader->NumShaderStorageBlocks <= BRW_MAX_SSBO);
1154       stage_prog_data->binding_table.ssbo_start = next_binding_table_offset;
1155       next_binding_table_offset += shader->NumShaderStorageBlocks;
1156    } else {
1157       stage_prog_data->binding_table.ubo_start = 0xd0d0d0d0;
1158       stage_prog_data->binding_table.ssbo_start = 0xd0d0d0d0;
1159    }
1160
1161    if (INTEL_DEBUG & DEBUG_SHADER_TIME) {
1162       stage_prog_data->binding_table.shader_time_start = next_binding_table_offset;
1163       next_binding_table_offset++;
1164    } else {
1165       stage_prog_data->binding_table.shader_time_start = 0xd0d0d0d0;
1166    }
1167
1168    if (prog->UsesGather) {
1169       if (devinfo->gen >= 8) {
1170          stage_prog_data->binding_table.gather_texture_start =
1171             stage_prog_data->binding_table.texture_start;
1172       } else {
1173          stage_prog_data->binding_table.gather_texture_start = next_binding_table_offset;
1174          next_binding_table_offset += num_textures;
1175       }
1176    } else {
1177       stage_prog_data->binding_table.gather_texture_start = 0xd0d0d0d0;
1178    }
1179
1180    if (shader_prog && shader_prog->NumAtomicBuffers) {
1181       stage_prog_data->binding_table.abo_start = next_binding_table_offset;
1182       next_binding_table_offset += shader_prog->NumAtomicBuffers;
1183    } else {
1184       stage_prog_data->binding_table.abo_start = 0xd0d0d0d0;
1185    }
1186
1187    if (shader && shader->NumImages) {
1188       stage_prog_data->binding_table.image_start = next_binding_table_offset;
1189       next_binding_table_offset += shader->NumImages;
1190    } else {
1191       stage_prog_data->binding_table.image_start = 0xd0d0d0d0;
1192    }
1193
1194    /* This may or may not be used depending on how the compile goes. */
1195    stage_prog_data->binding_table.pull_constants_start = next_binding_table_offset;
1196    next_binding_table_offset++;
1197
1198    assert(next_binding_table_offset <= BRW_MAX_SURFACES);
1199
1200    /* prog_data->base.binding_table.size will be set by brw_mark_surface_used. */
1201 }
1202
1203 static void
1204 setup_vec4_uniform_value(const gl_constant_value **params,
1205                          const gl_constant_value *values,
1206                          unsigned n)
1207 {
1208    static const gl_constant_value zero = { 0 };
1209
1210    for (unsigned i = 0; i < n; ++i)
1211       params[i] = &values[i];
1212
1213    for (unsigned i = n; i < 4; ++i)
1214       params[i] = &zero;
1215 }
1216
1217 void
1218 brw_setup_image_uniform_values(gl_shader_stage stage,
1219                                struct brw_stage_prog_data *stage_prog_data,
1220                                unsigned param_start_index,
1221                                const gl_uniform_storage *storage)
1222 {
1223    const gl_constant_value **param =
1224       &stage_prog_data->param[param_start_index];
1225
1226    for (unsigned i = 0; i < MAX2(storage->array_elements, 1); i++) {
1227       const unsigned image_idx = storage->opaque[stage].index + i;
1228       const brw_image_param *image_param =
1229          &stage_prog_data->image_param[image_idx];
1230
1231       /* Upload the brw_image_param structure.  The order is expected to match
1232        * the BRW_IMAGE_PARAM_*_OFFSET defines.
1233        */
1234       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SURFACE_IDX_OFFSET,
1235          (const gl_constant_value *)&image_param->surface_idx, 1);
1236       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_OFFSET_OFFSET,
1237          (const gl_constant_value *)image_param->offset, 2);
1238       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SIZE_OFFSET,
1239          (const gl_constant_value *)image_param->size, 3);
1240       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_STRIDE_OFFSET,
1241          (const gl_constant_value *)image_param->stride, 4);
1242       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_TILING_OFFSET,
1243          (const gl_constant_value *)image_param->tiling, 3);
1244       setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SWIZZLING_OFFSET,
1245          (const gl_constant_value *)image_param->swizzling, 2);
1246       param += BRW_IMAGE_PARAM_SIZE;
1247
1248       brw_mark_surface_used(
1249          stage_prog_data,
1250          stage_prog_data->binding_table.image_start + image_idx);
1251    }
1252 }
1253
1254 /**
1255  * Decide which set of clip planes should be used when clipping via
1256  * gl_Position or gl_ClipVertex.
1257  */
1258 gl_clip_plane *brw_select_clip_planes(struct gl_context *ctx)
1259 {
1260    if (ctx->_Shader->CurrentProgram[MESA_SHADER_VERTEX]) {
1261       /* There is currently a GLSL vertex shader, so clip according to GLSL
1262        * rules, which means compare gl_ClipVertex (or gl_Position, if
1263        * gl_ClipVertex wasn't assigned) against the eye-coordinate clip planes
1264        * that were stored in EyeUserPlane at the time the clip planes were
1265        * specified.
1266        */
1267       return ctx->Transform.EyeUserPlane;
1268    } else {
1269       /* Either we are using fixed function or an ARB vertex program.  In
1270        * either case the clip planes are going to be compared against
1271        * gl_Position (which is in clip coordinates) so we have to clip using
1272        * _ClipUserPlane, which was transformed into clip coordinates by Mesa
1273        * core.
1274        */
1275       return ctx->Transform._ClipUserPlane;
1276    }
1277 }
1278