src/mesa/drivers/dri/i965/brw_shader.cpp

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "main/macros.h"
  25 #include "brw_context.h"
  26 #include "brw_vs.h"
  27 #include "brw_gs.h"
  28 #include "brw_fs.h"
  29 #include "brw_cfg.h"
  30 #include "brw_nir.h"
  31 #include "glsl/ir_optimization.h"
  32 #include "glsl/glsl_parser_extras.h"
  33 #include "main/shaderapi.h"
  34
  35 static void
  36 shader_debug_log_mesa(void *data, const char *fmt, ...)
  37 {
  38    struct brw_context *brw = (struct brw_context *)data;
  39    va_list args;
  40
  41    va_start(args, fmt);
  42    GLuint msg_id = 0;
  43    _mesa_gl_vdebug(&brw->ctx, &msg_id,
  44                    MESA_DEBUG_SOURCE_SHADER_COMPILER,
  45                    MESA_DEBUG_TYPE_OTHER,
  46                    MESA_DEBUG_SEVERITY_NOTIFICATION, fmt, args);
  47    va_end(args);
  48 }
  49
  50 static void
  51 shader_perf_log_mesa(void *data, const char *fmt, ...)
  52 {
  53    struct brw_context *brw = (struct brw_context *)data;
  54
  55    va_list args;
  56    va_start(args, fmt);
  57
  58    if (unlikely(INTEL_DEBUG & DEBUG_PERF)) {
  59       va_list args_copy;
  60       va_copy(args_copy, args);
  61       vfprintf(stderr, fmt, args_copy);
  62       va_end(args_copy);
  63    }
  64
  65    if (brw->perf_debug) {
  66       GLuint msg_id = 0;
  67       _mesa_gl_vdebug(&brw->ctx, &msg_id,
  68                       MESA_DEBUG_SOURCE_SHADER_COMPILER,
  69                       MESA_DEBUG_TYPE_PERFORMANCE,
  70                       MESA_DEBUG_SEVERITY_MEDIUM, fmt, args);
  71    }
  72    va_end(args);
  73 }
  74
  75 struct brw_compiler *
  76 brw_compiler_create(void *mem_ctx, const struct brw_device_info *devinfo)
  77 {
  78    struct brw_compiler *compiler = rzalloc(mem_ctx, struct brw_compiler);
  79
  80    compiler->devinfo = devinfo;
  81    compiler->shader_debug_log = shader_debug_log_mesa;
  82    compiler->shader_perf_log = shader_perf_log_mesa;
  83
  84    brw_fs_alloc_reg_sets(compiler);
  85    brw_vec4_alloc_reg_set(compiler);
  86
  87    if (devinfo->gen >= 8 && !(INTEL_DEBUG & DEBUG_VEC4VS))
  88       compiler->scalar_vs = true;
  89
  90    nir_shader_compiler_options *nir_options =
  91       rzalloc(compiler, nir_shader_compiler_options);
  92    nir_options->native_integers = true;
  93    /* In order to help allow for better CSE at the NIR level we tell NIR
  94     * to split all ffma instructions during opt_algebraic and we then
  95     * re-combine them as a later step.
  96     */
  97    nir_options->lower_ffma = true;
  98    nir_options->lower_sub = true;
  99
 100    /* We want the GLSL compiler to emit code that uses condition codes */
 101    for (int i = 0; i < MESA_SHADER_STAGES; i++) {
 102       compiler->glsl_compiler_options[i].MaxUnrollIterations = 32;
 103       compiler->glsl_compiler_options[i].MaxIfDepth =
 104          devinfo->gen < 6 ? 16 : UINT_MAX;
 105
 106       compiler->glsl_compiler_options[i].EmitCondCodes = true;
 107       compiler->glsl_compiler_options[i].EmitNoNoise = true;
 108       compiler->glsl_compiler_options[i].EmitNoMainReturn = true;
 109       compiler->glsl_compiler_options[i].EmitNoIndirectInput = true;
 110       compiler->glsl_compiler_options[i].EmitNoIndirectOutput =
 111          (i == MESA_SHADER_FRAGMENT);
 112       compiler->glsl_compiler_options[i].EmitNoIndirectTemp =
 113          (i == MESA_SHADER_FRAGMENT);
 114       compiler->glsl_compiler_options[i].EmitNoIndirectUniform = false;
 115       compiler->glsl_compiler_options[i].LowerClipDistance = true;
 116
 117       /* !ARB_gpu_shader5 */
 118       if (devinfo->gen < 7)
 119          compiler->glsl_compiler_options[i].EmitNoIndirectSampler = true;
 120    }
 121
 122    compiler->glsl_compiler_options[MESA_SHADER_VERTEX].OptimizeForAOS = true;
 123    compiler->glsl_compiler_options[MESA_SHADER_GEOMETRY].OptimizeForAOS = true;
 124
 125    if (compiler->scalar_vs) {
 126       /* If we're using the scalar backend for vertex shaders, we need to
 127        * configure these accordingly.
 128        */
 129       compiler->glsl_compiler_options[MESA_SHADER_VERTEX].EmitNoIndirectOutput = true;
 130       compiler->glsl_compiler_options[MESA_SHADER_VERTEX].EmitNoIndirectTemp = true;
 131       compiler->glsl_compiler_options[MESA_SHADER_VERTEX].OptimizeForAOS = false;
 132
 133       compiler->glsl_compiler_options[MESA_SHADER_VERTEX].NirOptions = nir_options;
 134    }
 135
 136    compiler->glsl_compiler_options[MESA_SHADER_FRAGMENT].NirOptions = nir_options;
 137    compiler->glsl_compiler_options[MESA_SHADER_COMPUTE].NirOptions = nir_options;
 138
 139    return compiler;
 140 }
 141
 142 struct gl_shader *
 143 brw_new_shader(struct gl_context *ctx, GLuint name, GLuint type)
 144 {
 145    struct brw_shader *shader;
 146
 147    shader = rzalloc(NULL, struct brw_shader);
 148    if (shader) {
 149       shader->base.Type = type;
 150       shader->base.Stage = _mesa_shader_enum_to_shader_stage(type);
 151       shader->base.Name = name;
 152       _mesa_init_shader(ctx, &shader->base);
 153    }
 154
 155    return &shader->base;
 156 }
 157
 158 /**
 159  * Performs a compile of the shader stages even when we don't know
 160  * what non-orthogonal state will be set, in the hope that it reflects
 161  * the eventual NOS used, and thus allows us to produce link failures.
 162  */
 163 static bool
 164 brw_shader_precompile(struct gl_context *ctx,
 165                       struct gl_shader_program *sh_prog)
 166 {
 167    struct gl_shader *vs = sh_prog->_LinkedShaders[MESA_SHADER_VERTEX];
 168    struct gl_shader *gs = sh_prog->_LinkedShaders[MESA_SHADER_GEOMETRY];
 169    struct gl_shader *fs = sh_prog->_LinkedShaders[MESA_SHADER_FRAGMENT];
 170    struct gl_shader *cs = sh_prog->_LinkedShaders[MESA_SHADER_COMPUTE];
 171
 172    if (fs && !brw_fs_precompile(ctx, sh_prog, fs->Program))
 173       return false;
 174
 175    if (gs && !brw_gs_precompile(ctx, sh_prog, gs->Program))
 176       return false;
 177
 178    if (vs && !brw_vs_precompile(ctx, sh_prog, vs->Program))
 179       return false;
 180
 181    if (cs && !brw_cs_precompile(ctx, sh_prog, cs->Program))
 182       return false;
 183
 184    return true;
 185 }
 186
 187 static inline bool
 188 is_scalar_shader_stage(struct brw_context *brw, int stage)
 189 {
 190    switch (stage) {
 191    case MESA_SHADER_FRAGMENT:
 192       return true;
 193    case MESA_SHADER_VERTEX:
 194       return brw->intelScreen->compiler->scalar_vs;
 195    default:
 196       return false;
 197    }
 198 }
 199
 200 static void
 201 brw_lower_packing_builtins(struct brw_context *brw,
 202                            gl_shader_stage shader_type,
 203                            exec_list *ir)
 204 {
 205    int ops = LOWER_PACK_SNORM_2x16
 206            | LOWER_UNPACK_SNORM_2x16
 207            | LOWER_PACK_UNORM_2x16
 208            | LOWER_UNPACK_UNORM_2x16;
 209
 210    if (is_scalar_shader_stage(brw, shader_type)) {
 211       ops |= LOWER_UNPACK_UNORM_4x8
 212            | LOWER_UNPACK_SNORM_4x8
 213            | LOWER_PACK_UNORM_4x8
 214            | LOWER_PACK_SNORM_4x8;
 215    }
 216
 217    if (brw->gen >= 7) {
 218       /* Gen7 introduced the f32to16 and f16to32 instructions, which can be
 219        * used to execute packHalf2x16 and unpackHalf2x16. For AOS code, no
 220        * lowering is needed. For SOA code, the Half2x16 ops must be
 221        * scalarized.
 222        */
 223       if (is_scalar_shader_stage(brw, shader_type)) {
 224          ops |= LOWER_PACK_HALF_2x16_TO_SPLIT
 225              |  LOWER_UNPACK_HALF_2x16_TO_SPLIT;
 226       }
 227    } else {
 228       ops |= LOWER_PACK_HALF_2x16
 229           |  LOWER_UNPACK_HALF_2x16;
 230    }
 231
 232    lower_packing_builtins(ir, ops);
 233 }
 234
 235 static void
 236 process_glsl_ir(gl_shader_stage stage,
 237                 struct brw_context *brw,
 238                 struct gl_shader_program *shader_prog,
 239                 struct gl_shader *shader)
 240 {
 241    struct gl_context *ctx = &brw->ctx;
 242    const struct gl_shader_compiler_options *options =
 243       &ctx->Const.ShaderCompilerOptions[shader->Stage];
 244
 245    /* Temporary memory context for any new IR. */
 246    void *mem_ctx = ralloc_context(NULL);
 247
 248    ralloc_adopt(mem_ctx, shader->ir);
 249
 250    /* lower_packing_builtins() inserts arithmetic instructions, so it
 251     * must precede lower_instructions().
 252     */
 253    brw_lower_packing_builtins(brw, shader->Stage, shader->ir);
 254    do_mat_op_to_vec(shader->ir);
 255    const int bitfield_insert = brw->gen >= 7 ? BITFIELD_INSERT_TO_BFM_BFI : 0;
 256    lower_instructions(shader->ir,
 257                       MOD_TO_FLOOR |
 258                       DIV_TO_MUL_RCP |
 259                       SUB_TO_ADD_NEG |
 260                       EXP_TO_EXP2 |
 261                       LOG_TO_LOG2 |
 262                       bitfield_insert |
 263                       LDEXP_TO_ARITH |
 264                       CARRY_TO_ARITH |
 265                       BORROW_TO_ARITH);
 266
 267    /* Pre-gen6 HW can only nest if-statements 16 deep.  Beyond this,
 268     * if-statements need to be flattened.
 269     */
 270    if (brw->gen < 6)
 271       lower_if_to_cond_assign(shader->ir, 16);
 272
 273    do_lower_texture_projection(shader->ir);
 274    brw_lower_texture_gradients(brw, shader->ir);
 275    do_vec_index_to_cond_assign(shader->ir);
 276    lower_vector_insert(shader->ir, true);
 277    if (options->NirOptions == NULL)
 278       brw_do_cubemap_normalize(shader->ir);
 279    lower_offset_arrays(shader->ir);
 280    brw_do_lower_unnormalized_offset(shader->ir);
 281    lower_noise(shader->ir);
 282    lower_quadop_vector(shader->ir, false);
 283
 284    bool lowered_variable_indexing =
 285       lower_variable_index_to_cond_assign((gl_shader_stage)stage,
 286                                           shader->ir,
 287                                           options->EmitNoIndirectInput,
 288                                           options->EmitNoIndirectOutput,
 289                                           options->EmitNoIndirectTemp,
 290                                           options->EmitNoIndirectUniform);
 291
 292    if (unlikely(brw->perf_debug && lowered_variable_indexing)) {
 293       perf_debug("Unsupported form of variable indexing in FS; falling "
 294                  "back to very inefficient code generation\n");
 295    }
 296
 297    lower_ubo_reference(shader, shader->ir);
 298
 299    bool progress;
 300    do {
 301       progress = false;
 302
 303       if (is_scalar_shader_stage(brw, shader->Stage)) {
 304          brw_do_channel_expressions(shader->ir);
 305          brw_do_vector_splitting(shader->ir);
 306       }
 307
 308       progress = do_lower_jumps(shader->ir, true, true,
 309                                 true, /* main return */
 310                                 false, /* continue */
 311                                 false /* loops */
 312                                 ) || progress;
 313
 314       progress = do_common_optimization(shader->ir, true, true,
 315                                         options, ctx->Const.NativeIntegers) || progress;
 316    } while (progress);
 317
 318    if (options->NirOptions != NULL)
 319       lower_output_reads(stage, shader->ir);
 320
 321    validate_ir_tree(shader->ir);
 322
 323    /* Now that we've finished altering the linked IR, reparent any live IR back
 324     * to the permanent memory context, and free the temporary one (discarding any
 325     * junk we optimized away).
 326     */
 327    reparent_ir(shader->ir, shader->ir);
 328    ralloc_free(mem_ctx);
 329
 330    if (ctx->_Shader->Flags & GLSL_DUMP) {
 331       fprintf(stderr, "\n");
 332       fprintf(stderr, "GLSL IR for linked %s program %d:\n",
 333               _mesa_shader_stage_to_string(shader->Stage),
 334               shader_prog->Name);
 335       _mesa_print_ir(stderr, shader->ir, NULL);
 336       fprintf(stderr, "\n");
 337    }
 338 }
 339
 340 GLboolean
 341 brw_link_shader(struct gl_context *ctx, struct gl_shader_program *shProg)
 342 {
 343    struct brw_context *brw = brw_context(ctx);
 344    unsigned int stage;
 345
 346    for (stage = 0; stage < ARRAY_SIZE(shProg->_LinkedShaders); stage++) {
 347       struct gl_shader *shader = shProg->_LinkedShaders[stage];
 348       const struct gl_shader_compiler_options *options =
 349          &ctx->Const.ShaderCompilerOptions[stage];
 350
 351       if (!shader)
 352          continue;
 353
 354       struct gl_program *prog =
 355          ctx->Driver.NewProgram(ctx, _mesa_shader_stage_to_program(stage),
 356                                 shader->Name);
 357       if (!prog)
 358         return false;
 359       prog->Parameters = _mesa_new_parameter_list();
 360
 361       _mesa_copy_linked_program_data((gl_shader_stage) stage, shProg, prog);
 362
 363       process_glsl_ir((gl_shader_stage) stage, brw, shProg, shader);
 364
 365       /* Make a pass over the IR to add state references for any built-in
 366        * uniforms that are used.  This has to be done now (during linking).
 367        * Code generation doesn't happen until the first time this shader is
 368        * used for rendering.  Waiting until then to generate the parameters is
 369        * too late.  At that point, the values for the built-in uniforms won't
 370        * get sent to the shader.
 371        */
 372       foreach_in_list(ir_instruction, node, shader->ir) {
 373          ir_variable *var = node->as_variable();
 374
 375          if ((var == NULL) || (var->data.mode != ir_var_uniform)
 376              || (strncmp(var->name, "gl_", 3) != 0))
 377             continue;
 378
 379          const ir_state_slot *const slots = var->get_state_slots();
 380          assert(slots != NULL);
 381
 382          for (unsigned int i = 0; i < var->get_num_state_slots(); i++) {
 383             _mesa_add_state_reference(prog->Parameters,
 384                                       (gl_state_index *) slots[i].tokens);
 385          }
 386       }
 387
 388       do_set_program_inouts(shader->ir, prog, shader->Stage);
 389
 390       prog->SamplersUsed = shader->active_samplers;
 391       prog->ShadowSamplers = shader->shadow_samplers;
 392       _mesa_update_shader_textures_used(shProg, prog);
 393
 394       _mesa_reference_program(ctx, &shader->Program, prog);
 395
 396       brw_add_texrect_params(prog);
 397
 398       if (options->NirOptions)
 399          prog->nir = brw_create_nir(brw, shProg, prog, (gl_shader_stage) stage);
 400
 401       _mesa_reference_program(ctx, &prog, NULL);
 402    }
 403
 404    if ((ctx->_Shader->Flags & GLSL_DUMP) && shProg->Name != 0) {
 405       for (unsigned i = 0; i < shProg->NumShaders; i++) {
 406          const struct gl_shader *sh = shProg->Shaders[i];
 407          if (!sh)
 408             continue;
 409
 410          fprintf(stderr, "GLSL %s shader %d source for linked program %d:\n",
 411                  _mesa_shader_stage_to_string(sh->Stage),
 412                  i, shProg->Name);
 413          fprintf(stderr, "%s", sh->Source);
 414          fprintf(stderr, "\n");
 415       }
 416    }
 417
 418    if (brw->precompile && !brw_shader_precompile(ctx, shProg))
 419       return false;
 420
 421    return true;
 422 }
 423
 424
 425 enum brw_reg_type
 426 brw_type_for_base_type(const struct glsl_type *type)
 427 {
 428    switch (type->base_type) {
 429    case GLSL_TYPE_FLOAT:
 430       return BRW_REGISTER_TYPE_F;
 431    case GLSL_TYPE_INT:
 432    case GLSL_TYPE_BOOL:
 433       return BRW_REGISTER_TYPE_D;
 434    case GLSL_TYPE_UINT:
 435       return BRW_REGISTER_TYPE_UD;
 436    case GLSL_TYPE_ARRAY:
 437       return brw_type_for_base_type(type->fields.array);
 438    case GLSL_TYPE_STRUCT:
 439    case GLSL_TYPE_SAMPLER:
 440    case GLSL_TYPE_ATOMIC_UINT:
 441       /* These should be overridden with the type of the member when
 442        * dereferenced into.  BRW_REGISTER_TYPE_UD seems like a likely
 443        * way to trip up if we don't.
 444        */
 445       return BRW_REGISTER_TYPE_UD;
 446    case GLSL_TYPE_IMAGE:
 447       return BRW_REGISTER_TYPE_UD;
 448    case GLSL_TYPE_VOID:
 449    case GLSL_TYPE_ERROR:
 450    case GLSL_TYPE_INTERFACE:
 451    case GLSL_TYPE_DOUBLE:
 452       unreachable("not reached");
 453    }
 454
 455    return BRW_REGISTER_TYPE_F;
 456 }
 457
 458 enum brw_conditional_mod
 459 brw_conditional_for_comparison(unsigned int op)
 460 {
 461    switch (op) {
 462    case ir_binop_less:
 463       return BRW_CONDITIONAL_L;
 464    case ir_binop_greater:
 465       return BRW_CONDITIONAL_G;
 466    case ir_binop_lequal:
 467       return BRW_CONDITIONAL_LE;
 468    case ir_binop_gequal:
 469       return BRW_CONDITIONAL_GE;
 470    case ir_binop_equal:
 471    case ir_binop_all_equal: /* same as equal for scalars */
 472       return BRW_CONDITIONAL_Z;
 473    case ir_binop_nequal:
 474    case ir_binop_any_nequal: /* same as nequal for scalars */
 475       return BRW_CONDITIONAL_NZ;
 476    default:
 477       unreachable("not reached: bad operation for comparison");
 478    }
 479 }
 480
 481 uint32_t
 482 brw_math_function(enum opcode op)
 483 {
 484    switch (op) {
 485    case SHADER_OPCODE_RCP:
 486       return BRW_MATH_FUNCTION_INV;
 487    case SHADER_OPCODE_RSQ:
 488       return BRW_MATH_FUNCTION_RSQ;
 489    case SHADER_OPCODE_SQRT:
 490       return BRW_MATH_FUNCTION_SQRT;
 491    case SHADER_OPCODE_EXP2:
 492       return BRW_MATH_FUNCTION_EXP;
 493    case SHADER_OPCODE_LOG2:
 494       return BRW_MATH_FUNCTION_LOG;
 495    case SHADER_OPCODE_POW:
 496       return BRW_MATH_FUNCTION_POW;
 497    case SHADER_OPCODE_SIN:
 498       return BRW_MATH_FUNCTION_SIN;
 499    case SHADER_OPCODE_COS:
 500       return BRW_MATH_FUNCTION_COS;
 501    case SHADER_OPCODE_INT_QUOTIENT:
 502       return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT;
 503    case SHADER_OPCODE_INT_REMAINDER:
 504       return BRW_MATH_FUNCTION_INT_DIV_REMAINDER;
 505    default:
 506       unreachable("not reached: unknown math function");
 507    }
 508 }
 509
 510 uint32_t
 511 brw_texture_offset(int *offsets, unsigned num_components)
 512 {
 513    if (!offsets) return 0;  /* nonconstant offset; caller will handle it. */
 514
 515    /* Combine all three offsets into a single unsigned dword:
 516     *
 517     *    bits 11:8 - U Offset (X component)
 518     *    bits  7:4 - V Offset (Y component)
 519     *    bits  3:0 - R Offset (Z component)
 520     */
 521    unsigned offset_bits = 0;
 522    for (unsigned i = 0; i < num_components; i++) {
 523       const unsigned shift = 4 * (2 - i);
 524       offset_bits |= (offsets[i] << shift) & (0xF << shift);
 525    }
 526    return offset_bits;
 527 }
 528
 529 const char *
 530 brw_instruction_name(enum opcode op)
 531 {
 532    switch (op) {
 533    case BRW_OPCODE_MOV ... BRW_OPCODE_NOP:
 534       assert(opcode_descs[op].name);
 535       return opcode_descs[op].name;
 536    case FS_OPCODE_FB_WRITE:
 537       return "fb_write";
 538    case FS_OPCODE_BLORP_FB_WRITE:
 539       return "blorp_fb_write";
 540    case FS_OPCODE_REP_FB_WRITE:
 541       return "rep_fb_write";
 542
 543    case SHADER_OPCODE_RCP:
 544       return "rcp";
 545    case SHADER_OPCODE_RSQ:
 546       return "rsq";
 547    case SHADER_OPCODE_SQRT:
 548       return "sqrt";
 549    case SHADER_OPCODE_EXP2:
 550       return "exp2";
 551    case SHADER_OPCODE_LOG2:
 552       return "log2";
 553    case SHADER_OPCODE_POW:
 554       return "pow";
 555    case SHADER_OPCODE_INT_QUOTIENT:
 556       return "int_quot";
 557    case SHADER_OPCODE_INT_REMAINDER:
 558       return "int_rem";
 559    case SHADER_OPCODE_SIN:
 560       return "sin";
 561    case SHADER_OPCODE_COS:
 562       return "cos";
 563
 564    case SHADER_OPCODE_TEX:
 565       return "tex";
 566    case SHADER_OPCODE_TXD:
 567       return "txd";
 568    case SHADER_OPCODE_TXF:
 569       return "txf";
 570    case SHADER_OPCODE_TXL:
 571       return "txl";
 572    case SHADER_OPCODE_TXS:
 573       return "txs";
 574    case FS_OPCODE_TXB:
 575       return "txb";
 576    case SHADER_OPCODE_TXF_CMS:
 577       return "txf_cms";
 578    case SHADER_OPCODE_TXF_UMS:
 579       return "txf_ums";
 580    case SHADER_OPCODE_TXF_MCS:
 581       return "txf_mcs";
 582    case SHADER_OPCODE_LOD:
 583       return "lod";
 584    case SHADER_OPCODE_TG4:
 585       return "tg4";
 586    case SHADER_OPCODE_TG4_OFFSET:
 587       return "tg4_offset";
 588    case SHADER_OPCODE_SHADER_TIME_ADD:
 589       return "shader_time_add";
 590
 591    case SHADER_OPCODE_UNTYPED_ATOMIC:
 592       return "untyped_atomic";
 593    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
 594       return "untyped_surface_read";
 595    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
 596       return "untyped_surface_write";
 597    case SHADER_OPCODE_TYPED_ATOMIC:
 598       return "typed_atomic";
 599    case SHADER_OPCODE_TYPED_SURFACE_READ:
 600       return "typed_surface_read";
 601    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
 602       return "typed_surface_write";
 603    case SHADER_OPCODE_MEMORY_FENCE:
 604       return "memory_fence";
 605
 606    case SHADER_OPCODE_LOAD_PAYLOAD:
 607       return "load_payload";
 608
 609    case SHADER_OPCODE_GEN4_SCRATCH_READ:
 610       return "gen4_scratch_read";
 611    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 612       return "gen4_scratch_write";
 613    case SHADER_OPCODE_GEN7_SCRATCH_READ:
 614       return "gen7_scratch_read";
 615    case SHADER_OPCODE_URB_WRITE_SIMD8:
 616       return "gen8_urb_write_simd8";
 617
 618    case SHADER_OPCODE_FIND_LIVE_CHANNEL:
 619       return "find_live_channel";
 620    case SHADER_OPCODE_BROADCAST:
 621       return "broadcast";
 622
 623    case VEC4_OPCODE_MOV_BYTES:
 624       return "mov_bytes";
 625    case VEC4_OPCODE_PACK_BYTES:
 626       return "pack_bytes";
 627    case VEC4_OPCODE_UNPACK_UNIFORM:
 628       return "unpack_uniform";
 629
 630    case FS_OPCODE_DDX_COARSE:
 631       return "ddx_coarse";
 632    case FS_OPCODE_DDX_FINE:
 633       return "ddx_fine";
 634    case FS_OPCODE_DDY_COARSE:
 635       return "ddy_coarse";
 636    case FS_OPCODE_DDY_FINE:
 637       return "ddy_fine";
 638
 639    case FS_OPCODE_CINTERP:
 640       return "cinterp";
 641    case FS_OPCODE_LINTERP:
 642       return "linterp";
 643
 644    case FS_OPCODE_PIXEL_X:
 645       return "pixel_x";
 646    case FS_OPCODE_PIXEL_Y:
 647       return "pixel_y";
 648
 649    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
 650       return "uniform_pull_const";
 651    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
 652       return "uniform_pull_const_gen7";
 653    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
 654       return "varying_pull_const";
 655    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
 656       return "varying_pull_const_gen7";
 657
 658    case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
 659       return "mov_dispatch_to_flags";
 660    case FS_OPCODE_DISCARD_JUMP:
 661       return "discard_jump";
 662
 663    case FS_OPCODE_SET_OMASK:
 664       return "set_omask";
 665    case FS_OPCODE_SET_SAMPLE_ID:
 666       return "set_sample_id";
 667    case FS_OPCODE_SET_SIMD4X2_OFFSET:
 668       return "set_simd4x2_offset";
 669
 670    case FS_OPCODE_PACK_HALF_2x16_SPLIT:
 671       return "pack_half_2x16_split";
 672    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
 673       return "unpack_half_2x16_split_x";
 674    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
 675       return "unpack_half_2x16_split_y";
 676
 677    case FS_OPCODE_PLACEHOLDER_HALT:
 678       return "placeholder_halt";
 679
 680    case FS_OPCODE_INTERPOLATE_AT_CENTROID:
 681       return "interp_centroid";
 682    case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
 683       return "interp_sample";
 684    case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
 685       return "interp_shared_offset";
 686    case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
 687       return "interp_per_slot_offset";
 688
 689    case VS_OPCODE_URB_WRITE:
 690       return "vs_urb_write";
 691    case VS_OPCODE_PULL_CONSTANT_LOAD:
 692       return "pull_constant_load";
 693    case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
 694       return "pull_constant_load_gen7";
 695
 696    case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
 697       return "set_simd4x2_header_gen9";
 698
 699    case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
 700       return "unpack_flags_simd4x2";
 701
 702    case GS_OPCODE_URB_WRITE:
 703       return "gs_urb_write";
 704    case GS_OPCODE_URB_WRITE_ALLOCATE:
 705       return "gs_urb_write_allocate";
 706    case GS_OPCODE_THREAD_END:
 707       return "gs_thread_end";
 708    case GS_OPCODE_SET_WRITE_OFFSET:
 709       return "set_write_offset";
 710    case GS_OPCODE_SET_VERTEX_COUNT:
 711       return "set_vertex_count";
 712    case GS_OPCODE_SET_DWORD_2:
 713       return "set_dword_2";
 714    case GS_OPCODE_PREPARE_CHANNEL_MASKS:
 715       return "prepare_channel_masks";
 716    case GS_OPCODE_SET_CHANNEL_MASKS:
 717       return "set_channel_masks";
 718    case GS_OPCODE_GET_INSTANCE_ID:
 719       return "get_instance_id";
 720    case GS_OPCODE_FF_SYNC:
 721       return "ff_sync";
 722    case GS_OPCODE_SET_PRIMITIVE_ID:
 723       return "set_primitive_id";
 724    case GS_OPCODE_SVB_WRITE:
 725       return "gs_svb_write";
 726    case GS_OPCODE_SVB_SET_DST_INDEX:
 727       return "gs_svb_set_dst_index";
 728    case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
 729       return "gs_ff_sync_set_primitives";
 730    case CS_OPCODE_CS_TERMINATE:
 731       return "cs_terminate";
 732    case SHADER_OPCODE_BARRIER:
 733       return "barrier";
 734    }
 735
 736    unreachable("not reached");
 737 }
 738
 739 bool
 740 brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 741 {
 742    union {
 743       unsigned ud;
 744       int d;
 745       float f;
 746    } imm = { reg->dw1.ud }, sat_imm = { 0 };
 747
 748    switch (type) {
 749    case BRW_REGISTER_TYPE_UD:
 750    case BRW_REGISTER_TYPE_D:
 751    case BRW_REGISTER_TYPE_UQ:
 752    case BRW_REGISTER_TYPE_Q:
 753       /* Nothing to do. */
 754       return false;
 755    case BRW_REGISTER_TYPE_UW:
 756       sat_imm.ud = CLAMP(imm.ud, 0, USHRT_MAX);
 757       break;
 758    case BRW_REGISTER_TYPE_W:
 759       sat_imm.d = CLAMP(imm.d, SHRT_MIN, SHRT_MAX);
 760       break;
 761    case BRW_REGISTER_TYPE_F:
 762       sat_imm.f = CLAMP(imm.f, 0.0f, 1.0f);
 763       break;
 764    case BRW_REGISTER_TYPE_UB:
 765    case BRW_REGISTER_TYPE_B:
 766       unreachable("no UB/B immediates");
 767    case BRW_REGISTER_TYPE_V:
 768    case BRW_REGISTER_TYPE_UV:
 769    case BRW_REGISTER_TYPE_VF:
 770       unreachable("unimplemented: saturate vector immediate");
 771    case BRW_REGISTER_TYPE_DF:
 772    case BRW_REGISTER_TYPE_HF:
 773       unreachable("unimplemented: saturate DF/HF immediate");
 774    }
 775
 776    if (imm.ud != sat_imm.ud) {
 777       reg->dw1.ud = sat_imm.ud;
 778       return true;
 779    }
 780    return false;
 781 }
 782
 783 bool
 784 brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 785 {
 786    switch (type) {
 787    case BRW_REGISTER_TYPE_D:
 788    case BRW_REGISTER_TYPE_UD:
 789       reg->dw1.d = -reg->dw1.d;
 790       return true;
 791    case BRW_REGISTER_TYPE_W:
 792    case BRW_REGISTER_TYPE_UW:
 793       reg->dw1.d = -(int16_t)reg->dw1.ud;
 794       return true;
 795    case BRW_REGISTER_TYPE_F:
 796       reg->dw1.f = -reg->dw1.f;
 797       return true;
 798    case BRW_REGISTER_TYPE_VF:
 799       reg->dw1.ud ^= 0x80808080;
 800       return true;
 801    case BRW_REGISTER_TYPE_UB:
 802    case BRW_REGISTER_TYPE_B:
 803       unreachable("no UB/B immediates");
 804    case BRW_REGISTER_TYPE_UV:
 805    case BRW_REGISTER_TYPE_V:
 806       assert(!"unimplemented: negate UV/V immediate");
 807    case BRW_REGISTER_TYPE_UQ:
 808    case BRW_REGISTER_TYPE_Q:
 809       assert(!"unimplemented: negate UQ/Q immediate");
 810    case BRW_REGISTER_TYPE_DF:
 811    case BRW_REGISTER_TYPE_HF:
 812       assert(!"unimplemented: negate DF/HF immediate");
 813    }
 814
 815    return false;
 816 }
 817
 818 bool
 819 brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg)
 820 {
 821    switch (type) {
 822    case BRW_REGISTER_TYPE_D:
 823       reg->dw1.d = abs(reg->dw1.d);
 824       return true;
 825    case BRW_REGISTER_TYPE_W:
 826       reg->dw1.d = abs((int16_t)reg->dw1.ud);
 827       return true;
 828    case BRW_REGISTER_TYPE_F:
 829       reg->dw1.f = fabsf(reg->dw1.f);
 830       return true;
 831    case BRW_REGISTER_TYPE_VF:
 832       reg->dw1.ud &= ~0x80808080;
 833       return true;
 834    case BRW_REGISTER_TYPE_UB:
 835    case BRW_REGISTER_TYPE_B:
 836       unreachable("no UB/B immediates");
 837    case BRW_REGISTER_TYPE_UQ:
 838    case BRW_REGISTER_TYPE_UD:
 839    case BRW_REGISTER_TYPE_UW:
 840    case BRW_REGISTER_TYPE_UV:
 841       /* Presumably the absolute value modifier on an unsigned source is a
 842        * nop, but it would be nice to confirm.
 843        */
 844       assert(!"unimplemented: abs unsigned immediate");
 845    case BRW_REGISTER_TYPE_V:
 846       assert(!"unimplemented: abs V immediate");
 847    case BRW_REGISTER_TYPE_Q:
 848       assert(!"unimplemented: abs Q immediate");
 849    case BRW_REGISTER_TYPE_DF:
 850    case BRW_REGISTER_TYPE_HF:
 851       assert(!"unimplemented: abs DF/HF immediate");
 852    }
 853
 854    return false;
 855 }
 856
 857 backend_shader::backend_shader(const struct brw_compiler *compiler,
 858                                void *log_data,
 859                                void *mem_ctx,
 860                                struct gl_shader_program *shader_prog,
 861                                struct gl_program *prog,
 862                                struct brw_stage_prog_data *stage_prog_data,
 863                                gl_shader_stage stage)
 864    : compiler(compiler),
 865      log_data(log_data),
 866      devinfo(compiler->devinfo),
 867      shader(shader_prog ?
 868         (struct brw_shader *)shader_prog->_LinkedShaders[stage] : NULL),
 869      shader_prog(shader_prog),
 870      prog(prog),
 871      stage_prog_data(stage_prog_data),
 872      mem_ctx(mem_ctx),
 873      cfg(NULL),
 874      stage(stage)
 875 {
 876    debug_enabled = INTEL_DEBUG & intel_debug_flag_for_shader_stage(stage);
 877    stage_name = _mesa_shader_stage_to_string(stage);
 878    stage_abbrev = _mesa_shader_stage_to_abbrev(stage);
 879 }
 880
 881 bool
 882 backend_reg::is_zero() const
 883 {
 884    if (file != IMM)
 885       return false;
 886
 887    return fixed_hw_reg.dw1.d == 0;
 888 }
 889
 890 bool
 891 backend_reg::is_one() const
 892 {
 893    if (file != IMM)
 894       return false;
 895
 896    return type == BRW_REGISTER_TYPE_F
 897           ? fixed_hw_reg.dw1.f == 1.0
 898           : fixed_hw_reg.dw1.d == 1;
 899 }
 900
 901 bool
 902 backend_reg::is_negative_one() const
 903 {
 904    if (file != IMM)
 905       return false;
 906
 907    switch (type) {
 908    case BRW_REGISTER_TYPE_F:
 909       return fixed_hw_reg.dw1.f == -1.0;
 910    case BRW_REGISTER_TYPE_D:
 911       return fixed_hw_reg.dw1.d == -1;
 912    default:
 913       return false;
 914    }
 915 }
 916
 917 bool
 918 backend_reg::is_null() const
 919 {
 920    return file == HW_REG &&
 921           fixed_hw_reg.file == BRW_ARCHITECTURE_REGISTER_FILE &&
 922           fixed_hw_reg.nr == BRW_ARF_NULL;
 923 }
 924
 925
 926 bool
 927 backend_reg::is_accumulator() const
 928 {
 929    return file == HW_REG &&
 930           fixed_hw_reg.file == BRW_ARCHITECTURE_REGISTER_FILE &&
 931           fixed_hw_reg.nr == BRW_ARF_ACCUMULATOR;
 932 }
 933
 934 bool
 935 backend_reg::in_range(const backend_reg &r, unsigned n) const
 936 {
 937    return (file == r.file &&
 938            reg == r.reg &&
 939            reg_offset >= r.reg_offset &&
 940            reg_offset < r.reg_offset + n);
 941 }
 942
 943 bool
 944 backend_instruction::is_commutative() const
 945 {
 946    switch (opcode) {
 947    case BRW_OPCODE_AND:
 948    case BRW_OPCODE_OR:
 949    case BRW_OPCODE_XOR:
 950    case BRW_OPCODE_ADD:
 951    case BRW_OPCODE_MUL:
 952       return true;
 953    case BRW_OPCODE_SEL:
 954       /* MIN and MAX are commutative. */
 955       if (conditional_mod == BRW_CONDITIONAL_GE ||
 956           conditional_mod == BRW_CONDITIONAL_L) {
 957          return true;
 958       }
 959       /* fallthrough */
 960    default:
 961       return false;
 962    }
 963 }
 964
 965 bool
 966 backend_instruction::is_3src() const
 967 {
 968    return opcode < ARRAY_SIZE(opcode_descs) && opcode_descs[opcode].nsrc == 3;
 969 }
 970
 971 bool
 972 backend_instruction::is_tex() const
 973 {
 974    return (opcode == SHADER_OPCODE_TEX ||
 975            opcode == FS_OPCODE_TXB ||
 976            opcode == SHADER_OPCODE_TXD ||
 977            opcode == SHADER_OPCODE_TXF ||
 978            opcode == SHADER_OPCODE_TXF_CMS ||
 979            opcode == SHADER_OPCODE_TXF_UMS ||
 980            opcode == SHADER_OPCODE_TXF_MCS ||
 981            opcode == SHADER_OPCODE_TXL ||
 982            opcode == SHADER_OPCODE_TXS ||
 983            opcode == SHADER_OPCODE_LOD ||
 984            opcode == SHADER_OPCODE_TG4 ||
 985            opcode == SHADER_OPCODE_TG4_OFFSET);
 986 }
 987
 988 bool
 989 backend_instruction::is_math() const
 990 {
 991    return (opcode == SHADER_OPCODE_RCP ||
 992            opcode == SHADER_OPCODE_RSQ ||
 993            opcode == SHADER_OPCODE_SQRT ||
 994            opcode == SHADER_OPCODE_EXP2 ||
 995            opcode == SHADER_OPCODE_LOG2 ||
 996            opcode == SHADER_OPCODE_SIN ||
 997            opcode == SHADER_OPCODE_COS ||
 998            opcode == SHADER_OPCODE_INT_QUOTIENT ||
 999            opcode == SHADER_OPCODE_INT_REMAINDER ||
1000            opcode == SHADER_OPCODE_POW);
1001 }
1002
1003 bool
1004 backend_instruction::is_control_flow() const
1005 {
1006    switch (opcode) {
1007    case BRW_OPCODE_DO:
1008    case BRW_OPCODE_WHILE:
1009    case BRW_OPCODE_IF:
1010    case BRW_OPCODE_ELSE:
1011    case BRW_OPCODE_ENDIF:
1012    case BRW_OPCODE_BREAK:
1013    case BRW_OPCODE_CONTINUE:
1014       return true;
1015    default:
1016       return false;
1017    }
1018 }
1019
1020 bool
1021 backend_instruction::can_do_source_mods() const
1022 {
1023    switch (opcode) {
1024    case BRW_OPCODE_ADDC:
1025    case BRW_OPCODE_BFE:
1026    case BRW_OPCODE_BFI1:
1027    case BRW_OPCODE_BFI2:
1028    case BRW_OPCODE_BFREV:
1029    case BRW_OPCODE_CBIT:
1030    case BRW_OPCODE_FBH:
1031    case BRW_OPCODE_FBL:
1032    case BRW_OPCODE_SUBB:
1033       return false;
1034    default:
1035       return true;
1036    }
1037 }
1038
1039 bool
1040 backend_instruction::can_do_saturate() const
1041 {
1042    switch (opcode) {
1043    case BRW_OPCODE_ADD:
1044    case BRW_OPCODE_ASR:
1045    case BRW_OPCODE_AVG:
1046    case BRW_OPCODE_DP2:
1047    case BRW_OPCODE_DP3:
1048    case BRW_OPCODE_DP4:
1049    case BRW_OPCODE_DPH:
1050    case BRW_OPCODE_F16TO32:
1051    case BRW_OPCODE_F32TO16:
1052    case BRW_OPCODE_LINE:
1053    case BRW_OPCODE_LRP:
1054    case BRW_OPCODE_MAC:
1055    case BRW_OPCODE_MAD:
1056    case BRW_OPCODE_MATH:
1057    case BRW_OPCODE_MOV:
1058    case BRW_OPCODE_MUL:
1059    case BRW_OPCODE_PLN:
1060    case BRW_OPCODE_RNDD:
1061    case BRW_OPCODE_RNDE:
1062    case BRW_OPCODE_RNDU:
1063    case BRW_OPCODE_RNDZ:
1064    case BRW_OPCODE_SEL:
1065    case BRW_OPCODE_SHL:
1066    case BRW_OPCODE_SHR:
1067    case FS_OPCODE_LINTERP:
1068    case SHADER_OPCODE_COS:
1069    case SHADER_OPCODE_EXP2:
1070    case SHADER_OPCODE_LOG2:
1071    case SHADER_OPCODE_POW:
1072    case SHADER_OPCODE_RCP:
1073    case SHADER_OPCODE_RSQ:
1074    case SHADER_OPCODE_SIN:
1075    case SHADER_OPCODE_SQRT:
1076       return true;
1077    default:
1078       return false;
1079    }
1080 }
1081
1082 bool
1083 backend_instruction::can_do_cmod() const
1084 {
1085    switch (opcode) {
1086    case BRW_OPCODE_ADD:
1087    case BRW_OPCODE_ADDC:
1088    case BRW_OPCODE_AND:
1089    case BRW_OPCODE_ASR:
1090    case BRW_OPCODE_AVG:
1091    case BRW_OPCODE_CMP:
1092    case BRW_OPCODE_CMPN:
1093    case BRW_OPCODE_DP2:
1094    case BRW_OPCODE_DP3:
1095    case BRW_OPCODE_DP4:
1096    case BRW_OPCODE_DPH:
1097    case BRW_OPCODE_F16TO32:
1098    case BRW_OPCODE_F32TO16:
1099    case BRW_OPCODE_FRC:
1100    case BRW_OPCODE_LINE:
1101    case BRW_OPCODE_LRP:
1102    case BRW_OPCODE_LZD:
1103    case BRW_OPCODE_MAC:
1104    case BRW_OPCODE_MACH:
1105    case BRW_OPCODE_MAD:
1106    case BRW_OPCODE_MOV:
1107    case BRW_OPCODE_MUL:
1108    case BRW_OPCODE_NOT:
1109    case BRW_OPCODE_OR:
1110    case BRW_OPCODE_PLN:
1111    case BRW_OPCODE_RNDD:
1112    case BRW_OPCODE_RNDE:
1113    case BRW_OPCODE_RNDU:
1114    case BRW_OPCODE_RNDZ:
1115    case BRW_OPCODE_SAD2:
1116    case BRW_OPCODE_SADA2:
1117    case BRW_OPCODE_SHL:
1118    case BRW_OPCODE_SHR:
1119    case BRW_OPCODE_SUBB:
1120    case BRW_OPCODE_XOR:
1121    case FS_OPCODE_CINTERP:
1122    case FS_OPCODE_LINTERP:
1123       return true;
1124    default:
1125       return false;
1126    }
1127 }
1128
1129 bool
1130 backend_instruction::reads_accumulator_implicitly() const
1131 {
1132    switch (opcode) {
1133    case BRW_OPCODE_MAC:
1134    case BRW_OPCODE_MACH:
1135    case BRW_OPCODE_SADA2:
1136       return true;
1137    default:
1138       return false;
1139    }
1140 }
1141
1142 bool
1143 backend_instruction::writes_accumulator_implicitly(const struct brw_device_info *devinfo) const
1144 {
1145    return writes_accumulator ||
1146           (devinfo->gen < 6 &&
1147            ((opcode >= BRW_OPCODE_ADD && opcode < BRW_OPCODE_NOP) ||
1148             (opcode >= FS_OPCODE_DDX_COARSE && opcode <= FS_OPCODE_LINTERP &&
1149              opcode != FS_OPCODE_CINTERP)));
1150 }
1151
1152 bool
1153 backend_instruction::has_side_effects() const
1154 {
1155    switch (opcode) {
1156    case SHADER_OPCODE_UNTYPED_ATOMIC:
1157    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1158    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
1159    case SHADER_OPCODE_TYPED_ATOMIC:
1160    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
1161    case SHADER_OPCODE_MEMORY_FENCE:
1162    case SHADER_OPCODE_URB_WRITE_SIMD8:
1163    case FS_OPCODE_FB_WRITE:
1164    case SHADER_OPCODE_BARRIER:
1165       return true;
1166    default:
1167       return false;
1168    }
1169 }
1170
1171 #ifndef NDEBUG
1172 static bool
1173 inst_is_in_block(const bblock_t *block, const backend_instruction *inst)
1174 {
1175    bool found = false;
1176    foreach_inst_in_block (backend_instruction, i, block) {
1177       if (inst == i) {
1178          found = true;
1179       }
1180    }
1181    return found;
1182 }
1183 #endif
1184
1185 static void
1186 adjust_later_block_ips(bblock_t *start_block, int ip_adjustment)
1187 {
1188    for (bblock_t *block_iter = start_block->next();
1189         !block_iter->link.is_tail_sentinel();
1190         block_iter = block_iter->next()) {
1191       block_iter->start_ip += ip_adjustment;
1192       block_iter->end_ip += ip_adjustment;
1193    }
1194 }
1195
1196 void
1197 backend_instruction::insert_after(bblock_t *block, backend_instruction *inst)
1198 {
1199    if (!this->is_head_sentinel())
1200       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1201
1202    block->end_ip++;
1203
1204    adjust_later_block_ips(block, 1);
1205
1206    exec_node::insert_after(inst);
1207 }
1208
1209 void
1210 backend_instruction::insert_before(bblock_t *block, backend_instruction *inst)
1211 {
1212    if (!this->is_tail_sentinel())
1213       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1214
1215    block->end_ip++;
1216
1217    adjust_later_block_ips(block, 1);
1218
1219    exec_node::insert_before(inst);
1220 }
1221
1222 void
1223 backend_instruction::insert_before(bblock_t *block, exec_list *list)
1224 {
1225    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1226
1227    unsigned num_inst = list->length();
1228
1229    block->end_ip += num_inst;
1230
1231    adjust_later_block_ips(block, num_inst);
1232
1233    exec_node::insert_before(list);
1234 }
1235
1236 void
1237 backend_instruction::remove(bblock_t *block)
1238 {
1239    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1240
1241    adjust_later_block_ips(block, -1);
1242
1243    if (block->start_ip == block->end_ip) {
1244       block->cfg->remove_block(block);
1245    } else {
1246       block->end_ip--;
1247    }
1248
1249    exec_node::remove();
1250 }
1251
1252 void
1253 backend_shader::dump_instructions()
1254 {
1255    dump_instructions(NULL);
1256 }
1257
1258 void
1259 backend_shader::dump_instructions(const char *name)
1260 {
1261    FILE *file = stderr;
1262    if (name && geteuid() != 0) {
1263       file = fopen(name, "w");
1264       if (!file)
1265          file = stderr;
1266    }
1267
1268    if (cfg) {
1269       int ip = 0;
1270       foreach_block_and_inst(block, backend_instruction, inst, cfg) {
1271          fprintf(file, "%4d: ", ip++);
1272          dump_instruction(inst, file);
1273       }
1274    } else {
1275       int ip = 0;
1276       foreach_in_list(backend_instruction, inst, &instructions) {
1277          fprintf(file, "%4d: ", ip++);
1278          dump_instruction(inst, file);
1279       }
1280    }
1281
1282    if (file != stderr) {
1283       fclose(file);
1284    }
1285 }
1286
1287 void
1288 backend_shader::calculate_cfg()
1289 {
1290    if (this->cfg)
1291       return;
1292    cfg = new(mem_ctx) cfg_t(&this->instructions);
1293 }
1294
1295 void
1296 backend_shader::invalidate_cfg()
1297 {
1298    ralloc_free(this->cfg);
1299    this->cfg = NULL;
1300 }
1301
1302 /**
1303  * Sets up the starting offsets for the groups of binding table entries
1304  * commong to all pipeline stages.
1305  *
1306  * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
1307  * unused but also make sure that addition of small offsets to them will
1308  * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
1309  */
1310 void
1311 backend_shader::assign_common_binding_table_offsets(uint32_t next_binding_table_offset)
1312 {
1313    int num_textures = _mesa_fls(prog->SamplersUsed);
1314
1315    stage_prog_data->binding_table.texture_start = next_binding_table_offset;
1316    next_binding_table_offset += num_textures;
1317
1318    if (shader) {
1319       stage_prog_data->binding_table.ubo_start = next_binding_table_offset;
1320       next_binding_table_offset += shader->base.NumUniformBlocks;
1321    } else {
1322       stage_prog_data->binding_table.ubo_start = 0xd0d0d0d0;
1323    }
1324
1325    if (INTEL_DEBUG & DEBUG_SHADER_TIME) {
1326       stage_prog_data->binding_table.shader_time_start = next_binding_table_offset;
1327       next_binding_table_offset++;
1328    } else {
1329       stage_prog_data->binding_table.shader_time_start = 0xd0d0d0d0;
1330    }
1331
1332    if (prog->UsesGather) {
1333       if (devinfo->gen >= 8) {
1334          stage_prog_data->binding_table.gather_texture_start =
1335             stage_prog_data->binding_table.texture_start;
1336       } else {
1337          stage_prog_data->binding_table.gather_texture_start = next_binding_table_offset;
1338          next_binding_table_offset += num_textures;
1339       }
1340    } else {
1341       stage_prog_data->binding_table.gather_texture_start = 0xd0d0d0d0;
1342    }
1343
1344    if (shader_prog && shader_prog->NumAtomicBuffers) {
1345       stage_prog_data->binding_table.abo_start = next_binding_table_offset;
1346       next_binding_table_offset += shader_prog->NumAtomicBuffers;
1347    } else {
1348       stage_prog_data->binding_table.abo_start = 0xd0d0d0d0;
1349    }
1350
1351    if (shader && shader->base.NumImages) {
1352       stage_prog_data->binding_table.image_start = next_binding_table_offset;
1353       next_binding_table_offset += shader->base.NumImages;
1354    } else {
1355       stage_prog_data->binding_table.image_start = 0xd0d0d0d0;
1356    }
1357
1358    /* This may or may not be used depending on how the compile goes. */
1359    stage_prog_data->binding_table.pull_constants_start = next_binding_table_offset;
1360    next_binding_table_offset++;
1361
1362    assert(next_binding_table_offset <= BRW_MAX_SURFACES);
1363
1364    /* prog_data->base.binding_table.size will be set by brw_mark_surface_used. */
1365 }