src/mesa/drivers/dri/i965/brw_shader.cpp

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "main/macros.h"
  25 #include "brw_context.h"
  26 #include "brw_vs.h"
  27 #include "brw_gs.h"
  28 #include "brw_fs.h"
  29 #include "brw_cfg.h"
  30 #include "brw_nir.h"
  31 #include "glsl/ir_optimization.h"
  32 #include "glsl/glsl_parser_extras.h"
  33 #include "main/shaderapi.h"
  34
  35 static void
  36 shader_debug_log_mesa(void *data, const char *fmt, ...)
  37 {
  38    struct brw_context *brw = (struct brw_context *)data;
  39    va_list args;
  40
  41    va_start(args, fmt);
  42    GLuint msg_id = 0;
  43    _mesa_gl_vdebug(&brw->ctx, &msg_id,
  44                    MESA_DEBUG_SOURCE_SHADER_COMPILER,
  45                    MESA_DEBUG_TYPE_OTHER,
  46                    MESA_DEBUG_SEVERITY_NOTIFICATION, fmt, args);
  47    va_end(args);
  48 }
  49
  50 static void
  51 shader_perf_log_mesa(void *data, const char *fmt, ...)
  52 {
  53    struct brw_context *brw = (struct brw_context *)data;
  54
  55    va_list args;
  56    va_start(args, fmt);
  57
  58    if (unlikely(INTEL_DEBUG & DEBUG_PERF)) {
  59       va_list args_copy;
  60       va_copy(args_copy, args);
  61       vfprintf(stderr, fmt, args_copy);
  62       va_end(args_copy);
  63    }
  64
  65    if (brw->perf_debug) {
  66       GLuint msg_id = 0;
  67       _mesa_gl_vdebug(&brw->ctx, &msg_id,
  68                       MESA_DEBUG_SOURCE_SHADER_COMPILER,
  69                       MESA_DEBUG_TYPE_PERFORMANCE,
  70                       MESA_DEBUG_SEVERITY_MEDIUM, fmt, args);
  71    }
  72    va_end(args);
  73 }
  74
  75 struct brw_compiler *
  76 brw_compiler_create(void *mem_ctx, const struct brw_device_info *devinfo)
  77 {
  78    struct brw_compiler *compiler = rzalloc(mem_ctx, struct brw_compiler);
  79
  80    compiler->devinfo = devinfo;
  81    compiler->shader_debug_log = shader_debug_log_mesa;
  82    compiler->shader_perf_log = shader_perf_log_mesa;
  83
  84    brw_fs_alloc_reg_sets(compiler);
  85    brw_vec4_alloc_reg_set(compiler);
  86
  87    if (devinfo->gen >= 8 && !(INTEL_DEBUG & DEBUG_VEC4VS))
  88       compiler->scalar_vs = true;
  89
  90    nir_shader_compiler_options *nir_options =
  91       rzalloc(compiler, nir_shader_compiler_options);
  92    nir_options->native_integers = true;
  93    /* In order to help allow for better CSE at the NIR level we tell NIR
  94     * to split all ffma instructions during opt_algebraic and we then
  95     * re-combine them as a later step.
  96     */
  97    nir_options->lower_ffma = true;
  98    nir_options->lower_sub = true;
  99
 100    /* We want the GLSL compiler to emit code that uses condition codes */
 101    for (int i = 0; i < MESA_SHADER_STAGES; i++) {
 102       compiler->glsl_compiler_options[i].MaxUnrollIterations = 32;
 103       compiler->glsl_compiler_options[i].MaxIfDepth =
 104          devinfo->gen < 6 ? 16 : UINT_MAX;
 105
 106       compiler->glsl_compiler_options[i].EmitCondCodes = true;
 107       compiler->glsl_compiler_options[i].EmitNoNoise = true;
 108       compiler->glsl_compiler_options[i].EmitNoMainReturn = true;
 109       compiler->glsl_compiler_options[i].EmitNoIndirectInput = true;
 110       compiler->glsl_compiler_options[i].EmitNoIndirectOutput =
 111          (i == MESA_SHADER_FRAGMENT);
 112       compiler->glsl_compiler_options[i].EmitNoIndirectTemp =
 113          (i == MESA_SHADER_FRAGMENT);
 114       compiler->glsl_compiler_options[i].EmitNoIndirectUniform = false;
 115       compiler->glsl_compiler_options[i].LowerClipDistance = true;
 116
 117       /* !ARB_gpu_shader5 */
 118       if (devinfo->gen < 7)
 119          compiler->glsl_compiler_options[i].EmitNoIndirectSampler = true;
 120    }
 121
 122    compiler->glsl_compiler_options[MESA_SHADER_VERTEX].OptimizeForAOS = true;
 123    compiler->glsl_compiler_options[MESA_SHADER_GEOMETRY].OptimizeForAOS = true;
 124
 125    if (compiler->scalar_vs || brw_env_var_as_boolean("INTEL_USE_NIR", true)) {
 126       if (compiler->scalar_vs) {
 127          /* If we're using the scalar backend for vertex shaders, we need to
 128           * configure these accordingly.
 129           */
 130          compiler->glsl_compiler_options[MESA_SHADER_VERTEX].EmitNoIndirectOutput = true;
 131          compiler->glsl_compiler_options[MESA_SHADER_VERTEX].EmitNoIndirectTemp = true;
 132          compiler->glsl_compiler_options[MESA_SHADER_VERTEX].OptimizeForAOS = false;
 133       }
 134
 135       compiler->glsl_compiler_options[MESA_SHADER_VERTEX].NirOptions = nir_options;
 136    }
 137
 138    if (brw_env_var_as_boolean("INTEL_USE_NIR", true)) {
 139       compiler->glsl_compiler_options[MESA_SHADER_GEOMETRY].NirOptions = nir_options;
 140    }
 141
 142    compiler->glsl_compiler_options[MESA_SHADER_FRAGMENT].NirOptions = nir_options;
 143    compiler->glsl_compiler_options[MESA_SHADER_COMPUTE].NirOptions = nir_options;
 144
 145    return compiler;
 146 }
 147
 148 struct gl_shader *
 149 brw_new_shader(struct gl_context *ctx, GLuint name, GLuint type)
 150 {
 151    struct brw_shader *shader;
 152
 153    shader = rzalloc(NULL, struct brw_shader);
 154    if (shader) {
 155       shader->base.Type = type;
 156       shader->base.Stage = _mesa_shader_enum_to_shader_stage(type);
 157       shader->base.Name = name;
 158       _mesa_init_shader(ctx, &shader->base);
 159    }
 160
 161    return &shader->base;
 162 }
 163
 164 /**
 165  * Performs a compile of the shader stages even when we don't know
 166  * what non-orthogonal state will be set, in the hope that it reflects
 167  * the eventual NOS used, and thus allows us to produce link failures.
 168  */
 169 static bool
 170 brw_shader_precompile(struct gl_context *ctx,
 171                       struct gl_shader_program *sh_prog)
 172 {
 173    struct gl_shader *vs = sh_prog->_LinkedShaders[MESA_SHADER_VERTEX];
 174    struct gl_shader *gs = sh_prog->_LinkedShaders[MESA_SHADER_GEOMETRY];
 175    struct gl_shader *fs = sh_prog->_LinkedShaders[MESA_SHADER_FRAGMENT];
 176    struct gl_shader *cs = sh_prog->_LinkedShaders[MESA_SHADER_COMPUTE];
 177
 178    if (fs && !brw_fs_precompile(ctx, sh_prog, fs->Program))
 179       return false;
 180
 181    if (gs && !brw_gs_precompile(ctx, sh_prog, gs->Program))
 182       return false;
 183
 184    if (vs && !brw_vs_precompile(ctx, sh_prog, vs->Program))
 185       return false;
 186
 187    if (cs && !brw_cs_precompile(ctx, sh_prog, cs->Program))
 188       return false;
 189
 190    return true;
 191 }
 192
 193 static inline bool
 194 is_scalar_shader_stage(struct brw_context *brw, int stage)
 195 {
 196    switch (stage) {
 197    case MESA_SHADER_FRAGMENT:
 198    case MESA_SHADER_COMPUTE:
 199       return true;
 200    case MESA_SHADER_VERTEX:
 201       return brw->intelScreen->compiler->scalar_vs;
 202    default:
 203       return false;
 204    }
 205 }
 206
 207 static void
 208 brw_lower_packing_builtins(struct brw_context *brw,
 209                            gl_shader_stage shader_type,
 210                            exec_list *ir)
 211 {
 212    int ops = LOWER_PACK_SNORM_2x16
 213            | LOWER_UNPACK_SNORM_2x16
 214            | LOWER_PACK_UNORM_2x16
 215            | LOWER_UNPACK_UNORM_2x16;
 216
 217    if (is_scalar_shader_stage(brw, shader_type)) {
 218       ops |= LOWER_UNPACK_UNORM_4x8
 219            | LOWER_UNPACK_SNORM_4x8
 220            | LOWER_PACK_UNORM_4x8
 221            | LOWER_PACK_SNORM_4x8;
 222    }
 223
 224    if (brw->gen >= 7) {
 225       /* Gen7 introduced the f32to16 and f16to32 instructions, which can be
 226        * used to execute packHalf2x16 and unpackHalf2x16. For AOS code, no
 227        * lowering is needed. For SOA code, the Half2x16 ops must be
 228        * scalarized.
 229        */
 230       if (is_scalar_shader_stage(brw, shader_type)) {
 231          ops |= LOWER_PACK_HALF_2x16_TO_SPLIT
 232              |  LOWER_UNPACK_HALF_2x16_TO_SPLIT;
 233       }
 234    } else {
 235       ops |= LOWER_PACK_HALF_2x16
 236           |  LOWER_UNPACK_HALF_2x16;
 237    }
 238
 239    lower_packing_builtins(ir, ops);
 240 }
 241
 242 static void
 243 process_glsl_ir(gl_shader_stage stage,
 244                 struct brw_context *brw,
 245                 struct gl_shader_program *shader_prog,
 246                 struct gl_shader *shader)
 247 {
 248    struct gl_context *ctx = &brw->ctx;
 249    const struct gl_shader_compiler_options *options =
 250       &ctx->Const.ShaderCompilerOptions[shader->Stage];
 251
 252    /* Temporary memory context for any new IR. */
 253    void *mem_ctx = ralloc_context(NULL);
 254
 255    ralloc_adopt(mem_ctx, shader->ir);
 256
 257    /* lower_packing_builtins() inserts arithmetic instructions, so it
 258     * must precede lower_instructions().
 259     */
 260    brw_lower_packing_builtins(brw, shader->Stage, shader->ir);
 261    do_mat_op_to_vec(shader->ir);
 262    const int bitfield_insert = brw->gen >= 7 ? BITFIELD_INSERT_TO_BFM_BFI : 0;
 263    lower_instructions(shader->ir,
 264                       MOD_TO_FLOOR |
 265                       DIV_TO_MUL_RCP |
 266                       SUB_TO_ADD_NEG |
 267                       EXP_TO_EXP2 |
 268                       LOG_TO_LOG2 |
 269                       bitfield_insert |
 270                       LDEXP_TO_ARITH |
 271                       CARRY_TO_ARITH |
 272                       BORROW_TO_ARITH);
 273
 274    /* Pre-gen6 HW can only nest if-statements 16 deep.  Beyond this,
 275     * if-statements need to be flattened.
 276     */
 277    if (brw->gen < 6)
 278       lower_if_to_cond_assign(shader->ir, 16);
 279
 280    do_lower_texture_projection(shader->ir);
 281    brw_lower_texture_gradients(brw, shader->ir);
 282    do_vec_index_to_cond_assign(shader->ir);
 283    lower_vector_insert(shader->ir, true);
 284    if (options->NirOptions == NULL)
 285       brw_do_cubemap_normalize(shader->ir);
 286    lower_offset_arrays(shader->ir);
 287    brw_do_lower_unnormalized_offset(shader->ir);
 288    lower_noise(shader->ir);
 289    lower_quadop_vector(shader->ir, false);
 290
 291    bool lowered_variable_indexing =
 292       lower_variable_index_to_cond_assign((gl_shader_stage)stage,
 293                                           shader->ir,
 294                                           options->EmitNoIndirectInput,
 295                                           options->EmitNoIndirectOutput,
 296                                           options->EmitNoIndirectTemp,
 297                                           options->EmitNoIndirectUniform);
 298
 299    if (unlikely(brw->perf_debug && lowered_variable_indexing)) {
 300       perf_debug("Unsupported form of variable indexing in %s; falling "
 301                  "back to very inefficient code generation\n",
 302                  _mesa_shader_stage_to_abbrev(shader->Stage));
 303    }
 304
 305    lower_ubo_reference(shader, shader->ir);
 306
 307    bool progress;
 308    do {
 309       progress = false;
 310
 311       if (is_scalar_shader_stage(brw, shader->Stage)) {
 312          brw_do_channel_expressions(shader->ir);
 313          brw_do_vector_splitting(shader->ir);
 314       }
 315
 316       progress = do_lower_jumps(shader->ir, true, true,
 317                                 true, /* main return */
 318                                 false, /* continue */
 319                                 false /* loops */
 320                                 ) || progress;
 321
 322       progress = do_common_optimization(shader->ir, true, true,
 323                                         options, ctx->Const.NativeIntegers) || progress;
 324    } while (progress);
 325
 326    validate_ir_tree(shader->ir);
 327
 328    /* Now that we've finished altering the linked IR, reparent any live IR back
 329     * to the permanent memory context, and free the temporary one (discarding any
 330     * junk we optimized away).
 331     */
 332    reparent_ir(shader->ir, shader->ir);
 333    ralloc_free(mem_ctx);
 334
 335    if (ctx->_Shader->Flags & GLSL_DUMP) {
 336       fprintf(stderr, "\n");
 337       fprintf(stderr, "GLSL IR for linked %s program %d:\n",
 338               _mesa_shader_stage_to_string(shader->Stage),
 339               shader_prog->Name);
 340       _mesa_print_ir(stderr, shader->ir, NULL);
 341       fprintf(stderr, "\n");
 342    }
 343 }
 344
 345 GLboolean
 346 brw_link_shader(struct gl_context *ctx, struct gl_shader_program *shProg)
 347 {
 348    struct brw_context *brw = brw_context(ctx);
 349    unsigned int stage;
 350
 351    for (stage = 0; stage < ARRAY_SIZE(shProg->_LinkedShaders); stage++) {
 352       struct gl_shader *shader = shProg->_LinkedShaders[stage];
 353       const struct gl_shader_compiler_options *options =
 354          &ctx->Const.ShaderCompilerOptions[stage];
 355
 356       if (!shader)
 357          continue;
 358
 359       struct gl_program *prog =
 360          ctx->Driver.NewProgram(ctx, _mesa_shader_stage_to_program(stage),
 361                                 shader->Name);
 362       if (!prog)
 363         return false;
 364       prog->Parameters = _mesa_new_parameter_list();
 365
 366       _mesa_copy_linked_program_data((gl_shader_stage) stage, shProg, prog);
 367
 368       process_glsl_ir((gl_shader_stage) stage, brw, shProg, shader);
 369
 370       /* Make a pass over the IR to add state references for any built-in
 371        * uniforms that are used.  This has to be done now (during linking).
 372        * Code generation doesn't happen until the first time this shader is
 373        * used for rendering.  Waiting until then to generate the parameters is
 374        * too late.  At that point, the values for the built-in uniforms won't
 375        * get sent to the shader.
 376        */
 377       foreach_in_list(ir_instruction, node, shader->ir) {
 378          ir_variable *var = node->as_variable();
 379
 380          if ((var == NULL) || (var->data.mode != ir_var_uniform)
 381              || (strncmp(var->name, "gl_", 3) != 0))
 382             continue;
 383
 384          const ir_state_slot *const slots = var->get_state_slots();
 385          assert(slots != NULL);
 386
 387          for (unsigned int i = 0; i < var->get_num_state_slots(); i++) {
 388             _mesa_add_state_reference(prog->Parameters,
 389                                       (gl_state_index *) slots[i].tokens);
 390          }
 391       }
 392
 393       do_set_program_inouts(shader->ir, prog, shader->Stage);
 394
 395       prog->SamplersUsed = shader->active_samplers;
 396       prog->ShadowSamplers = shader->shadow_samplers;
 397       _mesa_update_shader_textures_used(shProg, prog);
 398
 399       _mesa_reference_program(ctx, &shader->Program, prog);
 400
 401       brw_add_texrect_params(prog);
 402
 403       if (options->NirOptions) {
 404          prog->nir = brw_create_nir(brw, shProg, prog, (gl_shader_stage) stage,
 405                                     is_scalar_shader_stage(brw, stage));
 406       }
 407
 408       _mesa_reference_program(ctx, &prog, NULL);
 409    }
 410
 411    if ((ctx->_Shader->Flags & GLSL_DUMP) && shProg->Name != 0) {
 412       for (unsigned i = 0; i < shProg->NumShaders; i++) {
 413          const struct gl_shader *sh = shProg->Shaders[i];
 414          if (!sh)
 415             continue;
 416
 417          fprintf(stderr, "GLSL %s shader %d source for linked program %d:\n",
 418                  _mesa_shader_stage_to_string(sh->Stage),
 419                  i, shProg->Name);
 420          fprintf(stderr, "%s", sh->Source);
 421          fprintf(stderr, "\n");
 422       }
 423    }
 424
 425    if (brw->precompile && !brw_shader_precompile(ctx, shProg))
 426       return false;
 427
 428    return true;
 429 }
 430
 431
 432 enum brw_reg_type
 433 brw_type_for_base_type(const struct glsl_type *type)
 434 {
 435    switch (type->base_type) {
 436    case GLSL_TYPE_FLOAT:
 437       return BRW_REGISTER_TYPE_F;
 438    case GLSL_TYPE_INT:
 439    case GLSL_TYPE_BOOL:
 440    case GLSL_TYPE_SUBROUTINE:
 441       return BRW_REGISTER_TYPE_D;
 442    case GLSL_TYPE_UINT:
 443       return BRW_REGISTER_TYPE_UD;
 444    case GLSL_TYPE_ARRAY:
 445       return brw_type_for_base_type(type->fields.array);
 446    case GLSL_TYPE_STRUCT:
 447    case GLSL_TYPE_SAMPLER:
 448    case GLSL_TYPE_ATOMIC_UINT:
 449       /* These should be overridden with the type of the member when
 450        * dereferenced into.  BRW_REGISTER_TYPE_UD seems like a likely
 451        * way to trip up if we don't.
 452        */
 453       return BRW_REGISTER_TYPE_UD;
 454    case GLSL_TYPE_IMAGE:
 455       return BRW_REGISTER_TYPE_UD;
 456    case GLSL_TYPE_VOID:
 457    case GLSL_TYPE_ERROR:
 458    case GLSL_TYPE_INTERFACE:
 459    case GLSL_TYPE_DOUBLE:
 460       unreachable("not reached");
 461    }
 462
 463    return BRW_REGISTER_TYPE_F;
 464 }
 465
 466 enum brw_conditional_mod
 467 brw_conditional_for_comparison(unsigned int op)
 468 {
 469    switch (op) {
 470    case ir_binop_less:
 471       return BRW_CONDITIONAL_L;
 472    case ir_binop_greater:
 473       return BRW_CONDITIONAL_G;
 474    case ir_binop_lequal:
 475       return BRW_CONDITIONAL_LE;
 476    case ir_binop_gequal:
 477       return BRW_CONDITIONAL_GE;
 478    case ir_binop_equal:
 479    case ir_binop_all_equal: /* same as equal for scalars */
 480       return BRW_CONDITIONAL_Z;
 481    case ir_binop_nequal:
 482    case ir_binop_any_nequal: /* same as nequal for scalars */
 483       return BRW_CONDITIONAL_NZ;
 484    default:
 485       unreachable("not reached: bad operation for comparison");
 486    }
 487 }
 488
 489 uint32_t
 490 brw_math_function(enum opcode op)
 491 {
 492    switch (op) {
 493    case SHADER_OPCODE_RCP:
 494       return BRW_MATH_FUNCTION_INV;
 495    case SHADER_OPCODE_RSQ:
 496       return BRW_MATH_FUNCTION_RSQ;
 497    case SHADER_OPCODE_SQRT:
 498       return BRW_MATH_FUNCTION_SQRT;
 499    case SHADER_OPCODE_EXP2:
 500       return BRW_MATH_FUNCTION_EXP;
 501    case SHADER_OPCODE_LOG2:
 502       return BRW_MATH_FUNCTION_LOG;
 503    case SHADER_OPCODE_POW:
 504       return BRW_MATH_FUNCTION_POW;
 505    case SHADER_OPCODE_SIN:
 506       return BRW_MATH_FUNCTION_SIN;
 507    case SHADER_OPCODE_COS:
 508       return BRW_MATH_FUNCTION_COS;
 509    case SHADER_OPCODE_INT_QUOTIENT:
 510       return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT;
 511    case SHADER_OPCODE_INT_REMAINDER:
 512       return BRW_MATH_FUNCTION_INT_DIV_REMAINDER;
 513    default:
 514       unreachable("not reached: unknown math function");
 515    }
 516 }
 517
 518 uint32_t
 519 brw_texture_offset(int *offsets, unsigned num_components)
 520 {
 521    if (!offsets) return 0;  /* nonconstant offset; caller will handle it. */
 522
 523    /* Combine all three offsets into a single unsigned dword:
 524     *
 525     *    bits 11:8 - U Offset (X component)
 526     *    bits  7:4 - V Offset (Y component)
 527     *    bits  3:0 - R Offset (Z component)
 528     */
 529    unsigned offset_bits = 0;
 530    for (unsigned i = 0; i < num_components; i++) {
 531       const unsigned shift = 4 * (2 - i);
 532       offset_bits |= (offsets[i] << shift) & (0xF << shift);
 533    }
 534    return offset_bits;
 535 }
 536
 537 const char *
 538 brw_instruction_name(enum opcode op)
 539 {
 540    switch (op) {
 541    case BRW_OPCODE_MOV ... BRW_OPCODE_NOP:
 542       assert(opcode_descs[op].name);
 543       return opcode_descs[op].name;
 544    case FS_OPCODE_FB_WRITE:
 545       return "fb_write";
 546    case FS_OPCODE_FB_WRITE_LOGICAL:
 547       return "fb_write_logical";
 548    case FS_OPCODE_BLORP_FB_WRITE:
 549       return "blorp_fb_write";
 550    case FS_OPCODE_REP_FB_WRITE:
 551       return "rep_fb_write";
 552
 553    case SHADER_OPCODE_RCP:
 554       return "rcp";
 555    case SHADER_OPCODE_RSQ:
 556       return "rsq";
 557    case SHADER_OPCODE_SQRT:
 558       return "sqrt";
 559    case SHADER_OPCODE_EXP2:
 560       return "exp2";
 561    case SHADER_OPCODE_LOG2:
 562       return "log2";
 563    case SHADER_OPCODE_POW:
 564       return "pow";
 565    case SHADER_OPCODE_INT_QUOTIENT:
 566       return "int_quot";
 567    case SHADER_OPCODE_INT_REMAINDER:
 568       return "int_rem";
 569    case SHADER_OPCODE_SIN:
 570       return "sin";
 571    case SHADER_OPCODE_COS:
 572       return "cos";
 573
 574    case SHADER_OPCODE_TEX:
 575       return "tex";
 576    case SHADER_OPCODE_TEX_LOGICAL:
 577       return "tex_logical";
 578    case SHADER_OPCODE_TXD:
 579       return "txd";
 580    case SHADER_OPCODE_TXD_LOGICAL:
 581       return "txd_logical";
 582    case SHADER_OPCODE_TXF:
 583       return "txf";
 584    case SHADER_OPCODE_TXF_LOGICAL:
 585       return "txf_logical";
 586    case SHADER_OPCODE_TXL:
 587       return "txl";
 588    case SHADER_OPCODE_TXL_LOGICAL:
 589       return "txl_logical";
 590    case SHADER_OPCODE_TXS:
 591       return "txs";
 592    case SHADER_OPCODE_TXS_LOGICAL:
 593       return "txs_logical";
 594    case FS_OPCODE_TXB:
 595       return "txb";
 596    case FS_OPCODE_TXB_LOGICAL:
 597       return "txb_logical";
 598    case SHADER_OPCODE_TXF_CMS:
 599       return "txf_cms";
 600    case SHADER_OPCODE_TXF_CMS_LOGICAL:
 601       return "txf_cms_logical";
 602    case SHADER_OPCODE_TXF_UMS:
 603       return "txf_ums";
 604    case SHADER_OPCODE_TXF_UMS_LOGICAL:
 605       return "txf_ums_logical";
 606    case SHADER_OPCODE_TXF_MCS:
 607       return "txf_mcs";
 608    case SHADER_OPCODE_TXF_MCS_LOGICAL:
 609       return "txf_mcs_logical";
 610    case SHADER_OPCODE_LOD:
 611       return "lod";
 612    case SHADER_OPCODE_LOD_LOGICAL:
 613       return "lod_logical";
 614    case SHADER_OPCODE_TG4:
 615       return "tg4";
 616    case SHADER_OPCODE_TG4_LOGICAL:
 617       return "tg4_logical";
 618    case SHADER_OPCODE_TG4_OFFSET:
 619       return "tg4_offset";
 620    case SHADER_OPCODE_TG4_OFFSET_LOGICAL:
 621       return "tg4_offset_logical";
 622    case SHADER_OPCODE_SAMPLEINFO:
 623       return "sampleinfo";
 624
 625    case SHADER_OPCODE_SHADER_TIME_ADD:
 626       return "shader_time_add";
 627
 628    case SHADER_OPCODE_UNTYPED_ATOMIC:
 629       return "untyped_atomic";
 630    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
 631       return "untyped_atomic_logical";
 632    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
 633       return "untyped_surface_read";
 634    case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
 635       return "untyped_surface_read_logical";
 636    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
 637       return "untyped_surface_write";
 638    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
 639       return "untyped_surface_write_logical";
 640    case SHADER_OPCODE_TYPED_ATOMIC:
 641       return "typed_atomic";
 642    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
 643       return "typed_atomic_logical";
 644    case SHADER_OPCODE_TYPED_SURFACE_READ:
 645       return "typed_surface_read";
 646    case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
 647       return "typed_surface_read_logical";
 648    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
 649       return "typed_surface_write";
 650    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
 651       return "typed_surface_write_logical";
 652    case SHADER_OPCODE_MEMORY_FENCE:
 653       return "memory_fence";
 654
 655    case SHADER_OPCODE_LOAD_PAYLOAD:
 656       return "load_payload";
 657
 658    case SHADER_OPCODE_GEN4_SCRATCH_READ:
 659       return "gen4_scratch_read";
 660    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 661       return "gen4_scratch_write";
 662    case SHADER_OPCODE_GEN7_SCRATCH_READ:
 663       return "gen7_scratch_read";
 664    case SHADER_OPCODE_URB_WRITE_SIMD8:
 665       return "gen8_urb_write_simd8";
 666
 667    case SHADER_OPCODE_FIND_LIVE_CHANNEL:
 668       return "find_live_channel";
 669    case SHADER_OPCODE_BROADCAST:
 670       return "broadcast";
 671
 672    case VEC4_OPCODE_MOV_BYTES:
 673       return "mov_bytes";
 674    case VEC4_OPCODE_PACK_BYTES:
 675       return "pack_bytes";
 676    case VEC4_OPCODE_UNPACK_UNIFORM:
 677       return "unpack_uniform";
 678
 679    case FS_OPCODE_DDX_COARSE:
 680       return "ddx_coarse";
 681    case FS_OPCODE_DDX_FINE:
 682       return "ddx_fine";
 683    case FS_OPCODE_DDY_COARSE:
 684       return "ddy_coarse";
 685    case FS_OPCODE_DDY_FINE:
 686       return "ddy_fine";
 687
 688    case FS_OPCODE_CINTERP:
 689       return "cinterp";
 690    case FS_OPCODE_LINTERP:
 691       return "linterp";
 692
 693    case FS_OPCODE_PIXEL_X:
 694       return "pixel_x";
 695    case FS_OPCODE_PIXEL_Y:
 696       return "pixel_y";
 697
 698    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
 699       return "uniform_pull_const";
 700    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
 701       return "uniform_pull_const_gen7";
 702    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
 703       return "varying_pull_const";
 704    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
 705       return "varying_pull_const_gen7";
 706
 707    case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
 708       return "mov_dispatch_to_flags";
 709    case FS_OPCODE_DISCARD_JUMP:
 710       return "discard_jump";
 711
 712    case FS_OPCODE_SET_SAMPLE_ID:
 713       return "set_sample_id";
 714    case FS_OPCODE_SET_SIMD4X2_OFFSET:
 715       return "set_simd4x2_offset";
 716
 717    case FS_OPCODE_PACK_HALF_2x16_SPLIT:
 718       return "pack_half_2x16_split";
 719    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
 720       return "unpack_half_2x16_split_x";
 721    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
 722       return "unpack_half_2x16_split_y";
 723
 724    case FS_OPCODE_PLACEHOLDER_HALT:
 725       return "placeholder_halt";
 726
 727    case FS_OPCODE_INTERPOLATE_AT_CENTROID:
 728       return "interp_centroid";
 729    case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
 730       return "interp_sample";
 731    case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
 732       return "interp_shared_offset";
 733    case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
 734       return "interp_per_slot_offset";
 735
 736    case VS_OPCODE_URB_WRITE:
 737       return "vs_urb_write";
 738    case VS_OPCODE_PULL_CONSTANT_LOAD:
 739       return "pull_constant_load";
 740    case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
 741       return "pull_constant_load_gen7";
 742
 743    case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
 744       return "set_simd4x2_header_gen9";
 745
 746    case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
 747       return "unpack_flags_simd4x2";
 748
 749    case GS_OPCODE_URB_WRITE:
 750       return "gs_urb_write";
 751    case GS_OPCODE_URB_WRITE_ALLOCATE:
 752       return "gs_urb_write_allocate";
 753    case GS_OPCODE_THREAD_END:
 754       return "gs_thread_end";
 755    case GS_OPCODE_SET_WRITE_OFFSET:
 756       return "set_write_offset";
 757    case GS_OPCODE_SET_VERTEX_COUNT:
 758       return "set_vertex_count";
 759    case GS_OPCODE_SET_DWORD_2:
 760       return "set_dword_2";
 761    case GS_OPCODE_PREPARE_CHANNEL_MASKS:
 762       return "prepare_channel_masks";
 763    case GS_OPCODE_SET_CHANNEL_MASKS:
 764       return "set_channel_masks";
 765    case GS_OPCODE_GET_INSTANCE_ID:
 766       return "get_instance_id";
 767    case GS_OPCODE_FF_SYNC:
 768       return "ff_sync";
 769    case GS_OPCODE_SET_PRIMITIVE_ID:
 770       return "set_primitive_id";
 771    case GS_OPCODE_SVB_WRITE:
 772       return "gs_svb_write";
 773    case GS_OPCODE_SVB_SET_DST_INDEX:
 774       return "gs_svb_set_dst_index";
 775    case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
 776       return "gs_ff_sync_set_primitives";
 777    case CS_OPCODE_CS_TERMINATE:
 778       return "cs_terminate";
 779    case SHADER_OPCODE_BARRIER:
 780       return "barrier";
 781    case SHADER_OPCODE_MULH:
 782       return "mulh";
 783    }
 784
 785    unreachable("not reached");
 786 }
 787
 788 bool
 789 brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 790 {
 791    union {
 792       unsigned ud;
 793       int d;
 794       float f;
 795    } imm = { reg->dw1.ud }, sat_imm = { 0 };
 796
 797    switch (type) {
 798    case BRW_REGISTER_TYPE_UD:
 799    case BRW_REGISTER_TYPE_D:
 800    case BRW_REGISTER_TYPE_UQ:
 801    case BRW_REGISTER_TYPE_Q:
 802       /* Nothing to do. */
 803       return false;
 804    case BRW_REGISTER_TYPE_UW:
 805       sat_imm.ud = CLAMP(imm.ud, 0, USHRT_MAX);
 806       break;
 807    case BRW_REGISTER_TYPE_W:
 808       sat_imm.d = CLAMP(imm.d, SHRT_MIN, SHRT_MAX);
 809       break;
 810    case BRW_REGISTER_TYPE_F:
 811       sat_imm.f = CLAMP(imm.f, 0.0f, 1.0f);
 812       break;
 813    case BRW_REGISTER_TYPE_UB:
 814    case BRW_REGISTER_TYPE_B:
 815       unreachable("no UB/B immediates");
 816    case BRW_REGISTER_TYPE_V:
 817    case BRW_REGISTER_TYPE_UV:
 818    case BRW_REGISTER_TYPE_VF:
 819       unreachable("unimplemented: saturate vector immediate");
 820    case BRW_REGISTER_TYPE_DF:
 821    case BRW_REGISTER_TYPE_HF:
 822       unreachable("unimplemented: saturate DF/HF immediate");
 823    }
 824
 825    if (imm.ud != sat_imm.ud) {
 826       reg->dw1.ud = sat_imm.ud;
 827       return true;
 828    }
 829    return false;
 830 }
 831
 832 bool
 833 brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 834 {
 835    switch (type) {
 836    case BRW_REGISTER_TYPE_D:
 837    case BRW_REGISTER_TYPE_UD:
 838       reg->dw1.d = -reg->dw1.d;
 839       return true;
 840    case BRW_REGISTER_TYPE_W:
 841    case BRW_REGISTER_TYPE_UW:
 842       reg->dw1.d = -(int16_t)reg->dw1.ud;
 843       return true;
 844    case BRW_REGISTER_TYPE_F:
 845       reg->dw1.f = -reg->dw1.f;
 846       return true;
 847    case BRW_REGISTER_TYPE_VF:
 848       reg->dw1.ud ^= 0x80808080;
 849       return true;
 850    case BRW_REGISTER_TYPE_UB:
 851    case BRW_REGISTER_TYPE_B:
 852       unreachable("no UB/B immediates");
 853    case BRW_REGISTER_TYPE_UV:
 854    case BRW_REGISTER_TYPE_V:
 855       assert(!"unimplemented: negate UV/V immediate");
 856    case BRW_REGISTER_TYPE_UQ:
 857    case BRW_REGISTER_TYPE_Q:
 858       assert(!"unimplemented: negate UQ/Q immediate");
 859    case BRW_REGISTER_TYPE_DF:
 860    case BRW_REGISTER_TYPE_HF:
 861       assert(!"unimplemented: negate DF/HF immediate");
 862    }
 863
 864    return false;
 865 }
 866
 867 bool
 868 brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg)
 869 {
 870    switch (type) {
 871    case BRW_REGISTER_TYPE_D:
 872       reg->dw1.d = abs(reg->dw1.d);
 873       return true;
 874    case BRW_REGISTER_TYPE_W:
 875       reg->dw1.d = abs((int16_t)reg->dw1.ud);
 876       return true;
 877    case BRW_REGISTER_TYPE_F:
 878       reg->dw1.f = fabsf(reg->dw1.f);
 879       return true;
 880    case BRW_REGISTER_TYPE_VF:
 881       reg->dw1.ud &= ~0x80808080;
 882       return true;
 883    case BRW_REGISTER_TYPE_UB:
 884    case BRW_REGISTER_TYPE_B:
 885       unreachable("no UB/B immediates");
 886    case BRW_REGISTER_TYPE_UQ:
 887    case BRW_REGISTER_TYPE_UD:
 888    case BRW_REGISTER_TYPE_UW:
 889    case BRW_REGISTER_TYPE_UV:
 890       /* Presumably the absolute value modifier on an unsigned source is a
 891        * nop, but it would be nice to confirm.
 892        */
 893       assert(!"unimplemented: abs unsigned immediate");
 894    case BRW_REGISTER_TYPE_V:
 895       assert(!"unimplemented: abs V immediate");
 896    case BRW_REGISTER_TYPE_Q:
 897       assert(!"unimplemented: abs Q immediate");
 898    case BRW_REGISTER_TYPE_DF:
 899    case BRW_REGISTER_TYPE_HF:
 900       assert(!"unimplemented: abs DF/HF immediate");
 901    }
 902
 903    return false;
 904 }
 905
 906 backend_shader::backend_shader(const struct brw_compiler *compiler,
 907                                void *log_data,
 908                                void *mem_ctx,
 909                                struct gl_shader_program *shader_prog,
 910                                struct gl_program *prog,
 911                                struct brw_stage_prog_data *stage_prog_data,
 912                                gl_shader_stage stage)
 913    : compiler(compiler),
 914      log_data(log_data),
 915      devinfo(compiler->devinfo),
 916      shader(shader_prog ?
 917         (struct brw_shader *)shader_prog->_LinkedShaders[stage] : NULL),
 918      shader_prog(shader_prog),
 919      prog(prog),
 920      stage_prog_data(stage_prog_data),
 921      mem_ctx(mem_ctx),
 922      cfg(NULL),
 923      stage(stage)
 924 {
 925    debug_enabled = INTEL_DEBUG & intel_debug_flag_for_shader_stage(stage);
 926    stage_name = _mesa_shader_stage_to_string(stage);
 927    stage_abbrev = _mesa_shader_stage_to_abbrev(stage);
 928 }
 929
 930 bool
 931 backend_reg::is_zero() const
 932 {
 933    if (file != IMM)
 934       return false;
 935
 936    return fixed_hw_reg.dw1.d == 0;
 937 }
 938
 939 bool
 940 backend_reg::is_one() const
 941 {
 942    if (file != IMM)
 943       return false;
 944
 945    return type == BRW_REGISTER_TYPE_F
 946           ? fixed_hw_reg.dw1.f == 1.0
 947           : fixed_hw_reg.dw1.d == 1;
 948 }
 949
 950 bool
 951 backend_reg::is_negative_one() const
 952 {
 953    if (file != IMM)
 954       return false;
 955
 956    switch (type) {
 957    case BRW_REGISTER_TYPE_F:
 958       return fixed_hw_reg.dw1.f == -1.0;
 959    case BRW_REGISTER_TYPE_D:
 960       return fixed_hw_reg.dw1.d == -1;
 961    default:
 962       return false;
 963    }
 964 }
 965
 966 bool
 967 backend_reg::is_null() const
 968 {
 969    return file == HW_REG &&
 970           fixed_hw_reg.file == BRW_ARCHITECTURE_REGISTER_FILE &&
 971           fixed_hw_reg.nr == BRW_ARF_NULL;
 972 }
 973
 974
 975 bool
 976 backend_reg::is_accumulator() const
 977 {
 978    return file == HW_REG &&
 979           fixed_hw_reg.file == BRW_ARCHITECTURE_REGISTER_FILE &&
 980           fixed_hw_reg.nr == BRW_ARF_ACCUMULATOR;
 981 }
 982
 983 bool
 984 backend_reg::in_range(const backend_reg &r, unsigned n) const
 985 {
 986    return (file == r.file &&
 987            reg == r.reg &&
 988            reg_offset >= r.reg_offset &&
 989            reg_offset < r.reg_offset + n);
 990 }
 991
 992 bool
 993 backend_instruction::is_commutative() const
 994 {
 995    switch (opcode) {
 996    case BRW_OPCODE_AND:
 997    case BRW_OPCODE_OR:
 998    case BRW_OPCODE_XOR:
 999    case BRW_OPCODE_ADD:
1000    case BRW_OPCODE_MUL:
1001    case SHADER_OPCODE_MULH:
1002       return true;
1003    case BRW_OPCODE_SEL:
1004       /* MIN and MAX are commutative. */
1005       if (conditional_mod == BRW_CONDITIONAL_GE ||
1006           conditional_mod == BRW_CONDITIONAL_L) {
1007          return true;
1008       }
1009       /* fallthrough */
1010    default:
1011       return false;
1012    }
1013 }
1014
1015 bool
1016 backend_instruction::is_3src() const
1017 {
1018    return opcode < ARRAY_SIZE(opcode_descs) && opcode_descs[opcode].nsrc == 3;
1019 }
1020
1021 bool
1022 backend_instruction::is_tex() const
1023 {
1024    return (opcode == SHADER_OPCODE_TEX ||
1025            opcode == FS_OPCODE_TXB ||
1026            opcode == SHADER_OPCODE_TXD ||
1027            opcode == SHADER_OPCODE_TXF ||
1028            opcode == SHADER_OPCODE_TXF_CMS ||
1029            opcode == SHADER_OPCODE_TXF_UMS ||
1030            opcode == SHADER_OPCODE_TXF_MCS ||
1031            opcode == SHADER_OPCODE_TXL ||
1032            opcode == SHADER_OPCODE_TXS ||
1033            opcode == SHADER_OPCODE_LOD ||
1034            opcode == SHADER_OPCODE_TG4 ||
1035            opcode == SHADER_OPCODE_TG4_OFFSET);
1036 }
1037
1038 bool
1039 backend_instruction::is_math() const
1040 {
1041    return (opcode == SHADER_OPCODE_RCP ||
1042            opcode == SHADER_OPCODE_RSQ ||
1043            opcode == SHADER_OPCODE_SQRT ||
1044            opcode == SHADER_OPCODE_EXP2 ||
1045            opcode == SHADER_OPCODE_LOG2 ||
1046            opcode == SHADER_OPCODE_SIN ||
1047            opcode == SHADER_OPCODE_COS ||
1048            opcode == SHADER_OPCODE_INT_QUOTIENT ||
1049            opcode == SHADER_OPCODE_INT_REMAINDER ||
1050            opcode == SHADER_OPCODE_POW);
1051 }
1052
1053 bool
1054 backend_instruction::is_control_flow() const
1055 {
1056    switch (opcode) {
1057    case BRW_OPCODE_DO:
1058    case BRW_OPCODE_WHILE:
1059    case BRW_OPCODE_IF:
1060    case BRW_OPCODE_ELSE:
1061    case BRW_OPCODE_ENDIF:
1062    case BRW_OPCODE_BREAK:
1063    case BRW_OPCODE_CONTINUE:
1064       return true;
1065    default:
1066       return false;
1067    }
1068 }
1069
1070 bool
1071 backend_instruction::can_do_source_mods() const
1072 {
1073    switch (opcode) {
1074    case BRW_OPCODE_ADDC:
1075    case BRW_OPCODE_BFE:
1076    case BRW_OPCODE_BFI1:
1077    case BRW_OPCODE_BFI2:
1078    case BRW_OPCODE_BFREV:
1079    case BRW_OPCODE_CBIT:
1080    case BRW_OPCODE_FBH:
1081    case BRW_OPCODE_FBL:
1082    case BRW_OPCODE_SUBB:
1083       return false;
1084    default:
1085       return true;
1086    }
1087 }
1088
1089 bool
1090 backend_instruction::can_do_saturate() const
1091 {
1092    switch (opcode) {
1093    case BRW_OPCODE_ADD:
1094    case BRW_OPCODE_ASR:
1095    case BRW_OPCODE_AVG:
1096    case BRW_OPCODE_DP2:
1097    case BRW_OPCODE_DP3:
1098    case BRW_OPCODE_DP4:
1099    case BRW_OPCODE_DPH:
1100    case BRW_OPCODE_F16TO32:
1101    case BRW_OPCODE_F32TO16:
1102    case BRW_OPCODE_LINE:
1103    case BRW_OPCODE_LRP:
1104    case BRW_OPCODE_MAC:
1105    case BRW_OPCODE_MAD:
1106    case BRW_OPCODE_MATH:
1107    case BRW_OPCODE_MOV:
1108    case BRW_OPCODE_MUL:
1109    case SHADER_OPCODE_MULH:
1110    case BRW_OPCODE_PLN:
1111    case BRW_OPCODE_RNDD:
1112    case BRW_OPCODE_RNDE:
1113    case BRW_OPCODE_RNDU:
1114    case BRW_OPCODE_RNDZ:
1115    case BRW_OPCODE_SEL:
1116    case BRW_OPCODE_SHL:
1117    case BRW_OPCODE_SHR:
1118    case FS_OPCODE_LINTERP:
1119    case SHADER_OPCODE_COS:
1120    case SHADER_OPCODE_EXP2:
1121    case SHADER_OPCODE_LOG2:
1122    case SHADER_OPCODE_POW:
1123    case SHADER_OPCODE_RCP:
1124    case SHADER_OPCODE_RSQ:
1125    case SHADER_OPCODE_SIN:
1126    case SHADER_OPCODE_SQRT:
1127       return true;
1128    default:
1129       return false;
1130    }
1131 }
1132
1133 bool
1134 backend_instruction::can_do_cmod() const
1135 {
1136    switch (opcode) {
1137    case BRW_OPCODE_ADD:
1138    case BRW_OPCODE_ADDC:
1139    case BRW_OPCODE_AND:
1140    case BRW_OPCODE_ASR:
1141    case BRW_OPCODE_AVG:
1142    case BRW_OPCODE_CMP:
1143    case BRW_OPCODE_CMPN:
1144    case BRW_OPCODE_DP2:
1145    case BRW_OPCODE_DP3:
1146    case BRW_OPCODE_DP4:
1147    case BRW_OPCODE_DPH:
1148    case BRW_OPCODE_F16TO32:
1149    case BRW_OPCODE_F32TO16:
1150    case BRW_OPCODE_FRC:
1151    case BRW_OPCODE_LINE:
1152    case BRW_OPCODE_LRP:
1153    case BRW_OPCODE_LZD:
1154    case BRW_OPCODE_MAC:
1155    case BRW_OPCODE_MACH:
1156    case BRW_OPCODE_MAD:
1157    case BRW_OPCODE_MOV:
1158    case BRW_OPCODE_MUL:
1159    case BRW_OPCODE_NOT:
1160    case BRW_OPCODE_OR:
1161    case BRW_OPCODE_PLN:
1162    case BRW_OPCODE_RNDD:
1163    case BRW_OPCODE_RNDE:
1164    case BRW_OPCODE_RNDU:
1165    case BRW_OPCODE_RNDZ:
1166    case BRW_OPCODE_SAD2:
1167    case BRW_OPCODE_SADA2:
1168    case BRW_OPCODE_SHL:
1169    case BRW_OPCODE_SHR:
1170    case BRW_OPCODE_SUBB:
1171    case BRW_OPCODE_XOR:
1172    case FS_OPCODE_CINTERP:
1173    case FS_OPCODE_LINTERP:
1174       return true;
1175    default:
1176       return false;
1177    }
1178 }
1179
1180 bool
1181 backend_instruction::reads_accumulator_implicitly() const
1182 {
1183    switch (opcode) {
1184    case BRW_OPCODE_MAC:
1185    case BRW_OPCODE_MACH:
1186    case BRW_OPCODE_SADA2:
1187       return true;
1188    default:
1189       return false;
1190    }
1191 }
1192
1193 bool
1194 backend_instruction::writes_accumulator_implicitly(const struct brw_device_info *devinfo) const
1195 {
1196    return writes_accumulator ||
1197           (devinfo->gen < 6 &&
1198            ((opcode >= BRW_OPCODE_ADD && opcode < BRW_OPCODE_NOP) ||
1199             (opcode >= FS_OPCODE_DDX_COARSE && opcode <= FS_OPCODE_LINTERP &&
1200              opcode != FS_OPCODE_CINTERP)));
1201 }
1202
1203 bool
1204 backend_instruction::has_side_effects() const
1205 {
1206    switch (opcode) {
1207    case SHADER_OPCODE_UNTYPED_ATOMIC:
1208    case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
1209    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1210    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
1211    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
1212    case SHADER_OPCODE_TYPED_ATOMIC:
1213    case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
1214    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
1215    case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
1216    case SHADER_OPCODE_MEMORY_FENCE:
1217    case SHADER_OPCODE_URB_WRITE_SIMD8:
1218    case FS_OPCODE_FB_WRITE:
1219    case SHADER_OPCODE_BARRIER:
1220       return true;
1221    default:
1222       return false;
1223    }
1224 }
1225
1226 #ifndef NDEBUG
1227 static bool
1228 inst_is_in_block(const bblock_t *block, const backend_instruction *inst)
1229 {
1230    bool found = false;
1231    foreach_inst_in_block (backend_instruction, i, block) {
1232       if (inst == i) {
1233          found = true;
1234       }
1235    }
1236    return found;
1237 }
1238 #endif
1239
1240 static void
1241 adjust_later_block_ips(bblock_t *start_block, int ip_adjustment)
1242 {
1243    for (bblock_t *block_iter = start_block->next();
1244         !block_iter->link.is_tail_sentinel();
1245         block_iter = block_iter->next()) {
1246       block_iter->start_ip += ip_adjustment;
1247       block_iter->end_ip += ip_adjustment;
1248    }
1249 }
1250
1251 void
1252 backend_instruction::insert_after(bblock_t *block, backend_instruction *inst)
1253 {
1254    if (!this->is_head_sentinel())
1255       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1256
1257    block->end_ip++;
1258
1259    adjust_later_block_ips(block, 1);
1260
1261    exec_node::insert_after(inst);
1262 }
1263
1264 void
1265 backend_instruction::insert_before(bblock_t *block, backend_instruction *inst)
1266 {
1267    if (!this->is_tail_sentinel())
1268       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1269
1270    block->end_ip++;
1271
1272    adjust_later_block_ips(block, 1);
1273
1274    exec_node::insert_before(inst);
1275 }
1276
1277 void
1278 backend_instruction::insert_before(bblock_t *block, exec_list *list)
1279 {
1280    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1281
1282    unsigned num_inst = list->length();
1283
1284    block->end_ip += num_inst;
1285
1286    adjust_later_block_ips(block, num_inst);
1287
1288    exec_node::insert_before(list);
1289 }
1290
1291 void
1292 backend_instruction::remove(bblock_t *block)
1293 {
1294    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1295
1296    adjust_later_block_ips(block, -1);
1297
1298    if (block->start_ip == block->end_ip) {
1299       block->cfg->remove_block(block);
1300    } else {
1301       block->end_ip--;
1302    }
1303
1304    exec_node::remove();
1305 }
1306
1307 void
1308 backend_shader::dump_instructions()
1309 {
1310    dump_instructions(NULL);
1311 }
1312
1313 void
1314 backend_shader::dump_instructions(const char *name)
1315 {
1316    FILE *file = stderr;
1317    if (name && geteuid() != 0) {
1318       file = fopen(name, "w");
1319       if (!file)
1320          file = stderr;
1321    }
1322
1323    if (cfg) {
1324       int ip = 0;
1325       foreach_block_and_inst(block, backend_instruction, inst, cfg) {
1326          fprintf(file, "%4d: ", ip++);
1327          dump_instruction(inst, file);
1328       }
1329    } else {
1330       int ip = 0;
1331       foreach_in_list(backend_instruction, inst, &instructions) {
1332          fprintf(file, "%4d: ", ip++);
1333          dump_instruction(inst, file);
1334       }
1335    }
1336
1337    if (file != stderr) {
1338       fclose(file);
1339    }
1340 }
1341
1342 void
1343 backend_shader::calculate_cfg()
1344 {
1345    if (this->cfg)
1346       return;
1347    cfg = new(mem_ctx) cfg_t(&this->instructions);
1348 }
1349
1350 void
1351 backend_shader::invalidate_cfg()
1352 {
1353    ralloc_free(this->cfg);
1354    this->cfg = NULL;
1355 }
1356
1357 /**
1358  * Sets up the starting offsets for the groups of binding table entries
1359  * commong to all pipeline stages.
1360  *
1361  * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
1362  * unused but also make sure that addition of small offsets to them will
1363  * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
1364  */
1365 void
1366 backend_shader::assign_common_binding_table_offsets(uint32_t next_binding_table_offset)
1367 {
1368    int num_textures = _mesa_fls(prog->SamplersUsed);
1369
1370    stage_prog_data->binding_table.texture_start = next_binding_table_offset;
1371    next_binding_table_offset += num_textures;
1372
1373    if (shader) {
1374       stage_prog_data->binding_table.ubo_start = next_binding_table_offset;
1375       next_binding_table_offset += shader->base.NumUniformBlocks;
1376    } else {
1377       stage_prog_data->binding_table.ubo_start = 0xd0d0d0d0;
1378    }
1379
1380    if (INTEL_DEBUG & DEBUG_SHADER_TIME) {
1381       stage_prog_data->binding_table.shader_time_start = next_binding_table_offset;
1382       next_binding_table_offset++;
1383    } else {
1384       stage_prog_data->binding_table.shader_time_start = 0xd0d0d0d0;
1385    }
1386
1387    if (prog->UsesGather) {
1388       if (devinfo->gen >= 8) {
1389          stage_prog_data->binding_table.gather_texture_start =
1390             stage_prog_data->binding_table.texture_start;
1391       } else {
1392          stage_prog_data->binding_table.gather_texture_start = next_binding_table_offset;
1393          next_binding_table_offset += num_textures;
1394       }
1395    } else {
1396       stage_prog_data->binding_table.gather_texture_start = 0xd0d0d0d0;
1397    }
1398
1399    if (shader_prog && shader_prog->NumAtomicBuffers) {
1400       stage_prog_data->binding_table.abo_start = next_binding_table_offset;
1401       next_binding_table_offset += shader_prog->NumAtomicBuffers;
1402    } else {
1403       stage_prog_data->binding_table.abo_start = 0xd0d0d0d0;
1404    }
1405
1406    if (shader && shader->base.NumImages) {
1407       stage_prog_data->binding_table.image_start = next_binding_table_offset;
1408       next_binding_table_offset += shader->base.NumImages;
1409    } else {
1410       stage_prog_data->binding_table.image_start = 0xd0d0d0d0;
1411    }
1412
1413    /* This may or may not be used depending on how the compile goes. */
1414    stage_prog_data->binding_table.pull_constants_start = next_binding_table_offset;
1415    next_binding_table_offset++;
1416
1417    assert(next_binding_table_offset <= BRW_MAX_SURFACES);
1418
1419    /* prog_data->base.binding_table.size will be set by brw_mark_surface_used. */
1420 }
1421
1422 void
1423 backend_shader::setup_image_uniform_values(unsigned param_offset,
1424                                            const gl_uniform_storage *storage)
1425 {
1426    const unsigned stage = _mesa_program_enum_to_shader_stage(prog->Target);
1427
1428    for (unsigned i = 0; i < MAX2(storage->array_elements, 1); i++) {
1429       const unsigned image_idx = storage->image[stage].index + i;
1430       const brw_image_param *param = &stage_prog_data->image_param[image_idx];
1431
1432       /* Upload the brw_image_param structure.  The order is expected to match
1433        * the BRW_IMAGE_PARAM_*_OFFSET defines.
1434        */
1435       setup_vec4_uniform_value(param_offset + BRW_IMAGE_PARAM_SURFACE_IDX_OFFSET,
1436          (const gl_constant_value *)&param->surface_idx, 1);
1437       setup_vec4_uniform_value(param_offset + BRW_IMAGE_PARAM_OFFSET_OFFSET,
1438          (const gl_constant_value *)param->offset, 2);
1439       setup_vec4_uniform_value(param_offset + BRW_IMAGE_PARAM_SIZE_OFFSET,
1440          (const gl_constant_value *)param->size, 3);
1441       setup_vec4_uniform_value(param_offset + BRW_IMAGE_PARAM_STRIDE_OFFSET,
1442          (const gl_constant_value *)param->stride, 4);
1443       setup_vec4_uniform_value(param_offset + BRW_IMAGE_PARAM_TILING_OFFSET,
1444          (const gl_constant_value *)param->tiling, 3);
1445       setup_vec4_uniform_value(param_offset + BRW_IMAGE_PARAM_SWIZZLING_OFFSET,
1446          (const gl_constant_value *)param->swizzling, 2);
1447       param_offset += BRW_IMAGE_PARAM_SIZE;
1448
1449       brw_mark_surface_used(
1450          stage_prog_data,
1451          stage_prog_data->binding_table.image_start + image_idx);
1452    }
1453 }