src/mesa/drivers/dri/i965/brw_shader.cpp

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "main/macros.h"
  25 #include "brw_context.h"
  26 #include "brw_vs.h"
  27 #include "brw_gs.h"
  28 #include "brw_fs.h"
  29 #include "brw_cfg.h"
  30 #include "brw_nir.h"
  31 #include "glsl/ir_optimization.h"
  32 #include "glsl/glsl_parser_extras.h"
  33 #include "main/shaderapi.h"
  34
  35 struct brw_compiler *
  36 brw_compiler_create(void *mem_ctx, const struct brw_device_info *devinfo)
  37 {
  38    struct brw_compiler *compiler = rzalloc(mem_ctx, struct brw_compiler);
  39
  40    compiler->devinfo = devinfo;
  41
  42    brw_fs_alloc_reg_sets(compiler);
  43    brw_vec4_alloc_reg_set(compiler);
  44
  45    return compiler;
  46 }
  47
  48 struct gl_shader *
  49 brw_new_shader(struct gl_context *ctx, GLuint name, GLuint type)
  50 {
  51    struct brw_shader *shader;
  52
  53    shader = rzalloc(NULL, struct brw_shader);
  54    if (shader) {
  55       shader->base.Type = type;
  56       shader->base.Stage = _mesa_shader_enum_to_shader_stage(type);
  57       shader->base.Name = name;
  58       _mesa_init_shader(ctx, &shader->base);
  59    }
  60
  61    return &shader->base;
  62 }
  63
  64 /**
  65  * Performs a compile of the shader stages even when we don't know
  66  * what non-orthogonal state will be set, in the hope that it reflects
  67  * the eventual NOS used, and thus allows us to produce link failures.
  68  */
  69 static bool
  70 brw_shader_precompile(struct gl_context *ctx,
  71                       struct gl_shader_program *sh_prog)
  72 {
  73    struct gl_shader *vs = sh_prog->_LinkedShaders[MESA_SHADER_VERTEX];
  74    struct gl_shader *gs = sh_prog->_LinkedShaders[MESA_SHADER_GEOMETRY];
  75    struct gl_shader *fs = sh_prog->_LinkedShaders[MESA_SHADER_FRAGMENT];
  76    struct gl_shader *cs = sh_prog->_LinkedShaders[MESA_SHADER_COMPUTE];
  77
  78    if (fs && !brw_fs_precompile(ctx, sh_prog, fs->Program))
  79       return false;
  80
  81    if (gs && !brw_gs_precompile(ctx, sh_prog, gs->Program))
  82       return false;
  83
  84    if (vs && !brw_vs_precompile(ctx, sh_prog, vs->Program))
  85       return false;
  86
  87    if (cs && !brw_cs_precompile(ctx, sh_prog, cs->Program))
  88       return false;
  89
  90    return true;
  91 }
  92
  93 static inline bool
  94 is_scalar_shader_stage(struct brw_context *brw, int stage)
  95 {
  96    switch (stage) {
  97    case MESA_SHADER_FRAGMENT:
  98       return true;
  99    case MESA_SHADER_VERTEX:
 100       return brw->scalar_vs;
 101    default:
 102       return false;
 103    }
 104 }
 105
 106 static void
 107 brw_lower_packing_builtins(struct brw_context *brw,
 108                            gl_shader_stage shader_type,
 109                            exec_list *ir)
 110 {
 111    int ops = LOWER_PACK_SNORM_2x16
 112            | LOWER_UNPACK_SNORM_2x16
 113            | LOWER_PACK_UNORM_2x16
 114            | LOWER_UNPACK_UNORM_2x16;
 115
 116    if (is_scalar_shader_stage(brw, shader_type)) {
 117       ops |= LOWER_UNPACK_UNORM_4x8
 118            | LOWER_UNPACK_SNORM_4x8
 119            | LOWER_PACK_UNORM_4x8
 120            | LOWER_PACK_SNORM_4x8;
 121    }
 122
 123    if (brw->gen >= 7) {
 124       /* Gen7 introduced the f32to16 and f16to32 instructions, which can be
 125        * used to execute packHalf2x16 and unpackHalf2x16. For AOS code, no
 126        * lowering is needed. For SOA code, the Half2x16 ops must be
 127        * scalarized.
 128        */
 129       if (is_scalar_shader_stage(brw, shader_type)) {
 130          ops |= LOWER_PACK_HALF_2x16_TO_SPLIT
 131              |  LOWER_UNPACK_HALF_2x16_TO_SPLIT;
 132       }
 133    } else {
 134       ops |= LOWER_PACK_HALF_2x16
 135           |  LOWER_UNPACK_HALF_2x16;
 136    }
 137
 138    lower_packing_builtins(ir, ops);
 139 }
 140
 141 static void
 142 process_glsl_ir(struct brw_context *brw,
 143                 struct gl_shader_program *shader_prog,
 144                 struct gl_shader *shader)
 145 {
 146    struct gl_context *ctx = &brw->ctx;
 147    const struct gl_shader_compiler_options *options =
 148       &ctx->Const.ShaderCompilerOptions[shader->Stage];
 149
 150    /* Temporary memory context for any new IR. */
 151    void *mem_ctx = ralloc_context(NULL);
 152
 153    ralloc_adopt(mem_ctx, shader->ir);
 154
 155    /* lower_packing_builtins() inserts arithmetic instructions, so it
 156     * must precede lower_instructions().
 157     */
 158    brw_lower_packing_builtins(brw, shader->Stage, shader->ir);
 159    do_mat_op_to_vec(shader->ir);
 160    const int bitfield_insert = brw->gen >= 7 ? BITFIELD_INSERT_TO_BFM_BFI : 0;
 161    lower_instructions(shader->ir,
 162                       MOD_TO_FLOOR |
 163                       DIV_TO_MUL_RCP |
 164                       SUB_TO_ADD_NEG |
 165                       EXP_TO_EXP2 |
 166                       LOG_TO_LOG2 |
 167                       bitfield_insert |
 168                       LDEXP_TO_ARITH);
 169
 170    /* Pre-gen6 HW can only nest if-statements 16 deep.  Beyond this,
 171     * if-statements need to be flattened.
 172     */
 173    if (brw->gen < 6)
 174       lower_if_to_cond_assign(shader->ir, 16);
 175
 176    do_lower_texture_projection(shader->ir);
 177    brw_lower_texture_gradients(brw, shader->ir);
 178    do_vec_index_to_cond_assign(shader->ir);
 179    lower_vector_insert(shader->ir, true);
 180    if (options->NirOptions == NULL)
 181       brw_do_cubemap_normalize(shader->ir);
 182    lower_offset_arrays(shader->ir);
 183    brw_do_lower_unnormalized_offset(shader->ir);
 184    lower_noise(shader->ir);
 185    lower_quadop_vector(shader->ir, false);
 186
 187    bool lowered_variable_indexing =
 188       lower_variable_index_to_cond_assign(shader->ir,
 189                                           options->EmitNoIndirectInput,
 190                                           options->EmitNoIndirectOutput,
 191                                           options->EmitNoIndirectTemp,
 192                                           options->EmitNoIndirectUniform);
 193
 194    if (unlikely(brw->perf_debug && lowered_variable_indexing)) {
 195       perf_debug("Unsupported form of variable indexing in FS; falling "
 196                  "back to very inefficient code generation\n");
 197    }
 198
 199    lower_ubo_reference(shader, shader->ir);
 200
 201    bool progress;
 202    do {
 203       progress = false;
 204
 205       if (is_scalar_shader_stage(brw, shader->Stage)) {
 206          brw_do_channel_expressions(shader->ir);
 207          brw_do_vector_splitting(shader->ir);
 208       }
 209
 210       progress = do_lower_jumps(shader->ir, true, true,
 211                                 true, /* main return */
 212                                 false, /* continue */
 213                                 false /* loops */
 214                                 ) || progress;
 215
 216       progress = do_common_optimization(shader->ir, true, true,
 217                                         options, ctx->Const.NativeIntegers) || progress;
 218    } while (progress);
 219
 220    if (options->NirOptions != NULL)
 221       lower_output_reads(shader->ir);
 222
 223    validate_ir_tree(shader->ir);
 224
 225    /* Now that we've finished altering the linked IR, reparent any live IR back
 226     * to the permanent memory context, and free the temporary one (discarding any
 227     * junk we optimized away).
 228     */
 229    reparent_ir(shader->ir, shader->ir);
 230    ralloc_free(mem_ctx);
 231
 232    if (ctx->_Shader->Flags & GLSL_DUMP) {
 233       fprintf(stderr, "\n");
 234       fprintf(stderr, "GLSL IR for linked %s program %d:\n",
 235               _mesa_shader_stage_to_string(shader->Stage),
 236               shader_prog->Name);
 237       _mesa_print_ir(stderr, shader->ir, NULL);
 238       fprintf(stderr, "\n");
 239    }
 240 }
 241
 242 GLboolean
 243 brw_link_shader(struct gl_context *ctx, struct gl_shader_program *shProg)
 244 {
 245    struct brw_context *brw = brw_context(ctx);
 246    unsigned int stage;
 247
 248    for (stage = 0; stage < ARRAY_SIZE(shProg->_LinkedShaders); stage++) {
 249       struct gl_shader *shader = shProg->_LinkedShaders[stage];
 250       const struct gl_shader_compiler_options *options =
 251          &ctx->Const.ShaderCompilerOptions[stage];
 252
 253       if (!shader)
 254          continue;
 255
 256       struct gl_program *prog =
 257          ctx->Driver.NewProgram(ctx, _mesa_shader_stage_to_program(stage),
 258                                 shader->Name);
 259       if (!prog)
 260         return false;
 261       prog->Parameters = _mesa_new_parameter_list();
 262
 263       _mesa_copy_linked_program_data((gl_shader_stage) stage, shProg, prog);
 264
 265       process_glsl_ir(brw, shProg, shader);
 266
 267       /* Make a pass over the IR to add state references for any built-in
 268        * uniforms that are used.  This has to be done now (during linking).
 269        * Code generation doesn't happen until the first time this shader is
 270        * used for rendering.  Waiting until then to generate the parameters is
 271        * too late.  At that point, the values for the built-in uniforms won't
 272        * get sent to the shader.
 273        */
 274       foreach_in_list(ir_instruction, node, shader->ir) {
 275          ir_variable *var = node->as_variable();
 276
 277          if ((var == NULL) || (var->data.mode != ir_var_uniform)
 278              || (strncmp(var->name, "gl_", 3) != 0))
 279             continue;
 280
 281          const ir_state_slot *const slots = var->get_state_slots();
 282          assert(slots != NULL);
 283
 284          for (unsigned int i = 0; i < var->get_num_state_slots(); i++) {
 285             _mesa_add_state_reference(prog->Parameters,
 286                                       (gl_state_index *) slots[i].tokens);
 287          }
 288       }
 289
 290       do_set_program_inouts(shader->ir, prog, shader->Stage);
 291
 292       prog->SamplersUsed = shader->active_samplers;
 293       prog->ShadowSamplers = shader->shadow_samplers;
 294       _mesa_update_shader_textures_used(shProg, prog);
 295
 296       _mesa_reference_program(ctx, &shader->Program, prog);
 297
 298       brw_add_texrect_params(prog);
 299
 300       if (options->NirOptions)
 301          prog->nir = brw_create_nir(brw, shProg, prog, (gl_shader_stage) stage);
 302
 303       _mesa_reference_program(ctx, &prog, NULL);
 304    }
 305
 306    if ((ctx->_Shader->Flags & GLSL_DUMP) && shProg->Name != 0) {
 307       for (unsigned i = 0; i < shProg->NumShaders; i++) {
 308          const struct gl_shader *sh = shProg->Shaders[i];
 309          if (!sh)
 310             continue;
 311
 312          fprintf(stderr, "GLSL %s shader %d source for linked program %d:\n",
 313                  _mesa_shader_stage_to_string(sh->Stage),
 314                  i, shProg->Name);
 315          fprintf(stderr, "%s", sh->Source);
 316          fprintf(stderr, "\n");
 317       }
 318    }
 319
 320    if (brw->precompile && !brw_shader_precompile(ctx, shProg))
 321       return false;
 322
 323    return true;
 324 }
 325
 326
 327 enum brw_reg_type
 328 brw_type_for_base_type(const struct glsl_type *type)
 329 {
 330    switch (type->base_type) {
 331    case GLSL_TYPE_FLOAT:
 332       return BRW_REGISTER_TYPE_F;
 333    case GLSL_TYPE_INT:
 334    case GLSL_TYPE_BOOL:
 335       return BRW_REGISTER_TYPE_D;
 336    case GLSL_TYPE_UINT:
 337       return BRW_REGISTER_TYPE_UD;
 338    case GLSL_TYPE_ARRAY:
 339       return brw_type_for_base_type(type->fields.array);
 340    case GLSL_TYPE_STRUCT:
 341    case GLSL_TYPE_SAMPLER:
 342    case GLSL_TYPE_ATOMIC_UINT:
 343       /* These should be overridden with the type of the member when
 344        * dereferenced into.  BRW_REGISTER_TYPE_UD seems like a likely
 345        * way to trip up if we don't.
 346        */
 347       return BRW_REGISTER_TYPE_UD;
 348    case GLSL_TYPE_IMAGE:
 349       return BRW_REGISTER_TYPE_UD;
 350    case GLSL_TYPE_VOID:
 351    case GLSL_TYPE_ERROR:
 352    case GLSL_TYPE_INTERFACE:
 353    case GLSL_TYPE_DOUBLE:
 354    case GLSL_TYPE_FUNCTION:
 355       unreachable("not reached");
 356    }
 357
 358    return BRW_REGISTER_TYPE_F;
 359 }
 360
 361 enum brw_conditional_mod
 362 brw_conditional_for_comparison(unsigned int op)
 363 {
 364    switch (op) {
 365    case ir_binop_less:
 366       return BRW_CONDITIONAL_L;
 367    case ir_binop_greater:
 368       return BRW_CONDITIONAL_G;
 369    case ir_binop_lequal:
 370       return BRW_CONDITIONAL_LE;
 371    case ir_binop_gequal:
 372       return BRW_CONDITIONAL_GE;
 373    case ir_binop_equal:
 374    case ir_binop_all_equal: /* same as equal for scalars */
 375       return BRW_CONDITIONAL_Z;
 376    case ir_binop_nequal:
 377    case ir_binop_any_nequal: /* same as nequal for scalars */
 378       return BRW_CONDITIONAL_NZ;
 379    default:
 380       unreachable("not reached: bad operation for comparison");
 381    }
 382 }
 383
 384 uint32_t
 385 brw_math_function(enum opcode op)
 386 {
 387    switch (op) {
 388    case SHADER_OPCODE_RCP:
 389       return BRW_MATH_FUNCTION_INV;
 390    case SHADER_OPCODE_RSQ:
 391       return BRW_MATH_FUNCTION_RSQ;
 392    case SHADER_OPCODE_SQRT:
 393       return BRW_MATH_FUNCTION_SQRT;
 394    case SHADER_OPCODE_EXP2:
 395       return BRW_MATH_FUNCTION_EXP;
 396    case SHADER_OPCODE_LOG2:
 397       return BRW_MATH_FUNCTION_LOG;
 398    case SHADER_OPCODE_POW:
 399       return BRW_MATH_FUNCTION_POW;
 400    case SHADER_OPCODE_SIN:
 401       return BRW_MATH_FUNCTION_SIN;
 402    case SHADER_OPCODE_COS:
 403       return BRW_MATH_FUNCTION_COS;
 404    case SHADER_OPCODE_INT_QUOTIENT:
 405       return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT;
 406    case SHADER_OPCODE_INT_REMAINDER:
 407       return BRW_MATH_FUNCTION_INT_DIV_REMAINDER;
 408    default:
 409       unreachable("not reached: unknown math function");
 410    }
 411 }
 412
 413 uint32_t
 414 brw_texture_offset(int *offsets, unsigned num_components)
 415 {
 416    if (!offsets) return 0;  /* nonconstant offset; caller will handle it. */
 417
 418    /* Combine all three offsets into a single unsigned dword:
 419     *
 420     *    bits 11:8 - U Offset (X component)
 421     *    bits  7:4 - V Offset (Y component)
 422     *    bits  3:0 - R Offset (Z component)
 423     */
 424    unsigned offset_bits = 0;
 425    for (unsigned i = 0; i < num_components; i++) {
 426       const unsigned shift = 4 * (2 - i);
 427       offset_bits |= (offsets[i] << shift) & (0xF << shift);
 428    }
 429    return offset_bits;
 430 }
 431
 432 const char *
 433 brw_instruction_name(enum opcode op)
 434 {
 435    switch (op) {
 436    case BRW_OPCODE_MOV ... BRW_OPCODE_NOP:
 437       assert(opcode_descs[op].name);
 438       return opcode_descs[op].name;
 439    case FS_OPCODE_FB_WRITE:
 440       return "fb_write";
 441    case FS_OPCODE_BLORP_FB_WRITE:
 442       return "blorp_fb_write";
 443    case FS_OPCODE_REP_FB_WRITE:
 444       return "rep_fb_write";
 445
 446    case SHADER_OPCODE_RCP:
 447       return "rcp";
 448    case SHADER_OPCODE_RSQ:
 449       return "rsq";
 450    case SHADER_OPCODE_SQRT:
 451       return "sqrt";
 452    case SHADER_OPCODE_EXP2:
 453       return "exp2";
 454    case SHADER_OPCODE_LOG2:
 455       return "log2";
 456    case SHADER_OPCODE_POW:
 457       return "pow";
 458    case SHADER_OPCODE_INT_QUOTIENT:
 459       return "int_quot";
 460    case SHADER_OPCODE_INT_REMAINDER:
 461       return "int_rem";
 462    case SHADER_OPCODE_SIN:
 463       return "sin";
 464    case SHADER_OPCODE_COS:
 465       return "cos";
 466
 467    case SHADER_OPCODE_TEX:
 468       return "tex";
 469    case SHADER_OPCODE_TXD:
 470       return "txd";
 471    case SHADER_OPCODE_TXF:
 472       return "txf";
 473    case SHADER_OPCODE_TXL:
 474       return "txl";
 475    case SHADER_OPCODE_TXS:
 476       return "txs";
 477    case FS_OPCODE_TXB:
 478       return "txb";
 479    case SHADER_OPCODE_TXF_CMS:
 480       return "txf_cms";
 481    case SHADER_OPCODE_TXF_UMS:
 482       return "txf_ums";
 483    case SHADER_OPCODE_TXF_MCS:
 484       return "txf_mcs";
 485    case SHADER_OPCODE_LOD:
 486       return "lod";
 487    case SHADER_OPCODE_TG4:
 488       return "tg4";
 489    case SHADER_OPCODE_TG4_OFFSET:
 490       return "tg4_offset";
 491    case SHADER_OPCODE_SHADER_TIME_ADD:
 492       return "shader_time_add";
 493
 494    case SHADER_OPCODE_UNTYPED_ATOMIC:
 495       return "untyped_atomic";
 496    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
 497       return "untyped_surface_read";
 498    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
 499       return "untyped_surface_write";
 500    case SHADER_OPCODE_TYPED_ATOMIC:
 501       return "typed_atomic";
 502    case SHADER_OPCODE_TYPED_SURFACE_READ:
 503       return "typed_surface_read";
 504    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
 505       return "typed_surface_write";
 506    case SHADER_OPCODE_MEMORY_FENCE:
 507       return "memory_fence";
 508
 509    case SHADER_OPCODE_LOAD_PAYLOAD:
 510       return "load_payload";
 511
 512    case SHADER_OPCODE_GEN4_SCRATCH_READ:
 513       return "gen4_scratch_read";
 514    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 515       return "gen4_scratch_write";
 516    case SHADER_OPCODE_GEN7_SCRATCH_READ:
 517       return "gen7_scratch_read";
 518    case SHADER_OPCODE_URB_WRITE_SIMD8:
 519       return "gen8_urb_write_simd8";
 520
 521    case SHADER_OPCODE_FIND_LIVE_CHANNEL:
 522       return "find_live_channel";
 523    case SHADER_OPCODE_BROADCAST:
 524       return "broadcast";
 525
 526    case VEC4_OPCODE_MOV_BYTES:
 527       return "mov_bytes";
 528    case VEC4_OPCODE_PACK_BYTES:
 529       return "pack_bytes";
 530    case VEC4_OPCODE_UNPACK_UNIFORM:
 531       return "unpack_uniform";
 532
 533    case FS_OPCODE_DDX_COARSE:
 534       return "ddx_coarse";
 535    case FS_OPCODE_DDX_FINE:
 536       return "ddx_fine";
 537    case FS_OPCODE_DDY_COARSE:
 538       return "ddy_coarse";
 539    case FS_OPCODE_DDY_FINE:
 540       return "ddy_fine";
 541
 542    case FS_OPCODE_CINTERP:
 543       return "cinterp";
 544    case FS_OPCODE_LINTERP:
 545       return "linterp";
 546
 547    case FS_OPCODE_PIXEL_X:
 548       return "pixel_x";
 549    case FS_OPCODE_PIXEL_Y:
 550       return "pixel_y";
 551
 552    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
 553       return "uniform_pull_const";
 554    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
 555       return "uniform_pull_const_gen7";
 556    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
 557       return "varying_pull_const";
 558    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
 559       return "varying_pull_const_gen7";
 560
 561    case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
 562       return "mov_dispatch_to_flags";
 563    case FS_OPCODE_DISCARD_JUMP:
 564       return "discard_jump";
 565
 566    case FS_OPCODE_SET_OMASK:
 567       return "set_omask";
 568    case FS_OPCODE_SET_SAMPLE_ID:
 569       return "set_sample_id";
 570    case FS_OPCODE_SET_SIMD4X2_OFFSET:
 571       return "set_simd4x2_offset";
 572
 573    case FS_OPCODE_PACK_HALF_2x16_SPLIT:
 574       return "pack_half_2x16_split";
 575    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
 576       return "unpack_half_2x16_split_x";
 577    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
 578       return "unpack_half_2x16_split_y";
 579
 580    case FS_OPCODE_PLACEHOLDER_HALT:
 581       return "placeholder_halt";
 582
 583    case FS_OPCODE_INTERPOLATE_AT_CENTROID:
 584       return "interp_centroid";
 585    case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
 586       return "interp_sample";
 587    case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
 588       return "interp_shared_offset";
 589    case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
 590       return "interp_per_slot_offset";
 591
 592    case VS_OPCODE_URB_WRITE:
 593       return "vs_urb_write";
 594    case VS_OPCODE_PULL_CONSTANT_LOAD:
 595       return "pull_constant_load";
 596    case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
 597       return "pull_constant_load_gen7";
 598
 599    case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
 600       return "set_simd4x2_header_gen9";
 601
 602    case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
 603       return "unpack_flags_simd4x2";
 604
 605    case GS_OPCODE_URB_WRITE:
 606       return "gs_urb_write";
 607    case GS_OPCODE_URB_WRITE_ALLOCATE:
 608       return "gs_urb_write_allocate";
 609    case GS_OPCODE_THREAD_END:
 610       return "gs_thread_end";
 611    case GS_OPCODE_SET_WRITE_OFFSET:
 612       return "set_write_offset";
 613    case GS_OPCODE_SET_VERTEX_COUNT:
 614       return "set_vertex_count";
 615    case GS_OPCODE_SET_DWORD_2:
 616       return "set_dword_2";
 617    case GS_OPCODE_PREPARE_CHANNEL_MASKS:
 618       return "prepare_channel_masks";
 619    case GS_OPCODE_SET_CHANNEL_MASKS:
 620       return "set_channel_masks";
 621    case GS_OPCODE_GET_INSTANCE_ID:
 622       return "get_instance_id";
 623    case GS_OPCODE_FF_SYNC:
 624       return "ff_sync";
 625    case GS_OPCODE_SET_PRIMITIVE_ID:
 626       return "set_primitive_id";
 627    case GS_OPCODE_SVB_WRITE:
 628       return "gs_svb_write";
 629    case GS_OPCODE_SVB_SET_DST_INDEX:
 630       return "gs_svb_set_dst_index";
 631    case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
 632       return "gs_ff_sync_set_primitives";
 633    case CS_OPCODE_CS_TERMINATE:
 634       return "cs_terminate";
 635    }
 636
 637    unreachable("not reached");
 638 }
 639
 640 bool
 641 brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 642 {
 643    union {
 644       unsigned ud;
 645       int d;
 646       float f;
 647    } imm = { reg->dw1.ud }, sat_imm = { 0 };
 648
 649    switch (type) {
 650    case BRW_REGISTER_TYPE_UD:
 651    case BRW_REGISTER_TYPE_D:
 652    case BRW_REGISTER_TYPE_UQ:
 653    case BRW_REGISTER_TYPE_Q:
 654       /* Nothing to do. */
 655       return false;
 656    case BRW_REGISTER_TYPE_UW:
 657       sat_imm.ud = CLAMP(imm.ud, 0, USHRT_MAX);
 658       break;
 659    case BRW_REGISTER_TYPE_W:
 660       sat_imm.d = CLAMP(imm.d, SHRT_MIN, SHRT_MAX);
 661       break;
 662    case BRW_REGISTER_TYPE_F:
 663       sat_imm.f = CLAMP(imm.f, 0.0f, 1.0f);
 664       break;
 665    case BRW_REGISTER_TYPE_UB:
 666    case BRW_REGISTER_TYPE_B:
 667       unreachable("no UB/B immediates");
 668    case BRW_REGISTER_TYPE_V:
 669    case BRW_REGISTER_TYPE_UV:
 670    case BRW_REGISTER_TYPE_VF:
 671       unreachable("unimplemented: saturate vector immediate");
 672    case BRW_REGISTER_TYPE_DF:
 673    case BRW_REGISTER_TYPE_HF:
 674       unreachable("unimplemented: saturate DF/HF immediate");
 675    }
 676
 677    if (imm.ud != sat_imm.ud) {
 678       reg->dw1.ud = sat_imm.ud;
 679       return true;
 680    }
 681    return false;
 682 }
 683
 684 bool
 685 brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 686 {
 687    switch (type) {
 688    case BRW_REGISTER_TYPE_D:
 689    case BRW_REGISTER_TYPE_UD:
 690       reg->dw1.d = -reg->dw1.d;
 691       return true;
 692    case BRW_REGISTER_TYPE_W:
 693    case BRW_REGISTER_TYPE_UW:
 694       reg->dw1.d = -(int16_t)reg->dw1.ud;
 695       return true;
 696    case BRW_REGISTER_TYPE_F:
 697       reg->dw1.f = -reg->dw1.f;
 698       return true;
 699    case BRW_REGISTER_TYPE_VF:
 700       reg->dw1.ud ^= 0x80808080;
 701       return true;
 702    case BRW_REGISTER_TYPE_UB:
 703    case BRW_REGISTER_TYPE_B:
 704       unreachable("no UB/B immediates");
 705    case BRW_REGISTER_TYPE_UV:
 706    case BRW_REGISTER_TYPE_V:
 707       assert(!"unimplemented: negate UV/V immediate");
 708    case BRW_REGISTER_TYPE_UQ:
 709    case BRW_REGISTER_TYPE_Q:
 710       assert(!"unimplemented: negate UQ/Q immediate");
 711    case BRW_REGISTER_TYPE_DF:
 712    case BRW_REGISTER_TYPE_HF:
 713       assert(!"unimplemented: negate DF/HF immediate");
 714    }
 715
 716    return false;
 717 }
 718
 719 bool
 720 brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg)
 721 {
 722    switch (type) {
 723    case BRW_REGISTER_TYPE_D:
 724       reg->dw1.d = abs(reg->dw1.d);
 725       return true;
 726    case BRW_REGISTER_TYPE_W:
 727       reg->dw1.d = abs((int16_t)reg->dw1.ud);
 728       return true;
 729    case BRW_REGISTER_TYPE_F:
 730       reg->dw1.f = fabsf(reg->dw1.f);
 731       return true;
 732    case BRW_REGISTER_TYPE_VF:
 733       reg->dw1.ud &= ~0x80808080;
 734       return true;
 735    case BRW_REGISTER_TYPE_UB:
 736    case BRW_REGISTER_TYPE_B:
 737       unreachable("no UB/B immediates");
 738    case BRW_REGISTER_TYPE_UQ:
 739    case BRW_REGISTER_TYPE_UD:
 740    case BRW_REGISTER_TYPE_UW:
 741    case BRW_REGISTER_TYPE_UV:
 742       /* Presumably the absolute value modifier on an unsigned source is a
 743        * nop, but it would be nice to confirm.
 744        */
 745       assert(!"unimplemented: abs unsigned immediate");
 746    case BRW_REGISTER_TYPE_V:
 747       assert(!"unimplemented: abs V immediate");
 748    case BRW_REGISTER_TYPE_Q:
 749       assert(!"unimplemented: abs Q immediate");
 750    case BRW_REGISTER_TYPE_DF:
 751    case BRW_REGISTER_TYPE_HF:
 752       assert(!"unimplemented: abs DF/HF immediate");
 753    }
 754
 755    return false;
 756 }
 757
 758 backend_visitor::backend_visitor(struct brw_context *brw,
 759                                  struct gl_shader_program *shader_prog,
 760                                  struct gl_program *prog,
 761                                  struct brw_stage_prog_data *stage_prog_data,
 762                                  gl_shader_stage stage)
 763    : brw(brw),
 764      devinfo(brw->intelScreen->devinfo),
 765      ctx(&brw->ctx),
 766      shader(shader_prog ?
 767         (struct brw_shader *)shader_prog->_LinkedShaders[stage] : NULL),
 768      shader_prog(shader_prog),
 769      prog(prog),
 770      stage_prog_data(stage_prog_data),
 771      cfg(NULL),
 772      stage(stage)
 773 {
 774    debug_enabled = INTEL_DEBUG & intel_debug_flag_for_shader_stage(stage);
 775    stage_name = _mesa_shader_stage_to_string(stage);
 776    stage_abbrev = _mesa_shader_stage_to_abbrev(stage);
 777 }
 778
 779 bool
 780 backend_reg::is_zero() const
 781 {
 782    if (file != IMM)
 783       return false;
 784
 785    return fixed_hw_reg.dw1.d == 0;
 786 }
 787
 788 bool
 789 backend_reg::is_one() const
 790 {
 791    if (file != IMM)
 792       return false;
 793
 794    return type == BRW_REGISTER_TYPE_F
 795           ? fixed_hw_reg.dw1.f == 1.0
 796           : fixed_hw_reg.dw1.d == 1;
 797 }
 798
 799 bool
 800 backend_reg::is_negative_one() const
 801 {
 802    if (file != IMM)
 803       return false;
 804
 805    switch (type) {
 806    case BRW_REGISTER_TYPE_F:
 807       return fixed_hw_reg.dw1.f == -1.0;
 808    case BRW_REGISTER_TYPE_D:
 809       return fixed_hw_reg.dw1.d == -1;
 810    default:
 811       return false;
 812    }
 813 }
 814
 815 bool
 816 backend_reg::is_null() const
 817 {
 818    return file == HW_REG &&
 819           fixed_hw_reg.file == BRW_ARCHITECTURE_REGISTER_FILE &&
 820           fixed_hw_reg.nr == BRW_ARF_NULL;
 821 }
 822
 823
 824 bool
 825 backend_reg::is_accumulator() const
 826 {
 827    return file == HW_REG &&
 828           fixed_hw_reg.file == BRW_ARCHITECTURE_REGISTER_FILE &&
 829           fixed_hw_reg.nr == BRW_ARF_ACCUMULATOR;
 830 }
 831
 832 bool
 833 backend_reg::in_range(const backend_reg &r, unsigned n) const
 834 {
 835    return (file == r.file &&
 836            reg == r.reg &&
 837            reg_offset >= r.reg_offset &&
 838            reg_offset < r.reg_offset + n);
 839 }
 840
 841 bool
 842 backend_instruction::is_commutative() const
 843 {
 844    switch (opcode) {
 845    case BRW_OPCODE_AND:
 846    case BRW_OPCODE_OR:
 847    case BRW_OPCODE_XOR:
 848    case BRW_OPCODE_ADD:
 849    case BRW_OPCODE_MUL:
 850       return true;
 851    case BRW_OPCODE_SEL:
 852       /* MIN and MAX are commutative. */
 853       if (conditional_mod == BRW_CONDITIONAL_GE ||
 854           conditional_mod == BRW_CONDITIONAL_L) {
 855          return true;
 856       }
 857       /* fallthrough */
 858    default:
 859       return false;
 860    }
 861 }
 862
 863 bool
 864 backend_instruction::is_3src() const
 865 {
 866    return opcode < ARRAY_SIZE(opcode_descs) && opcode_descs[opcode].nsrc == 3;
 867 }
 868
 869 bool
 870 backend_instruction::is_tex() const
 871 {
 872    return (opcode == SHADER_OPCODE_TEX ||
 873            opcode == FS_OPCODE_TXB ||
 874            opcode == SHADER_OPCODE_TXD ||
 875            opcode == SHADER_OPCODE_TXF ||
 876            opcode == SHADER_OPCODE_TXF_CMS ||
 877            opcode == SHADER_OPCODE_TXF_UMS ||
 878            opcode == SHADER_OPCODE_TXF_MCS ||
 879            opcode == SHADER_OPCODE_TXL ||
 880            opcode == SHADER_OPCODE_TXS ||
 881            opcode == SHADER_OPCODE_LOD ||
 882            opcode == SHADER_OPCODE_TG4 ||
 883            opcode == SHADER_OPCODE_TG4_OFFSET);
 884 }
 885
 886 bool
 887 backend_instruction::is_math() const
 888 {
 889    return (opcode == SHADER_OPCODE_RCP ||
 890            opcode == SHADER_OPCODE_RSQ ||
 891            opcode == SHADER_OPCODE_SQRT ||
 892            opcode == SHADER_OPCODE_EXP2 ||
 893            opcode == SHADER_OPCODE_LOG2 ||
 894            opcode == SHADER_OPCODE_SIN ||
 895            opcode == SHADER_OPCODE_COS ||
 896            opcode == SHADER_OPCODE_INT_QUOTIENT ||
 897            opcode == SHADER_OPCODE_INT_REMAINDER ||
 898            opcode == SHADER_OPCODE_POW);
 899 }
 900
 901 bool
 902 backend_instruction::is_control_flow() const
 903 {
 904    switch (opcode) {
 905    case BRW_OPCODE_DO:
 906    case BRW_OPCODE_WHILE:
 907    case BRW_OPCODE_IF:
 908    case BRW_OPCODE_ELSE:
 909    case BRW_OPCODE_ENDIF:
 910    case BRW_OPCODE_BREAK:
 911    case BRW_OPCODE_CONTINUE:
 912       return true;
 913    default:
 914       return false;
 915    }
 916 }
 917
 918 bool
 919 backend_instruction::can_do_source_mods() const
 920 {
 921    switch (opcode) {
 922    case BRW_OPCODE_ADDC:
 923    case BRW_OPCODE_BFE:
 924    case BRW_OPCODE_BFI1:
 925    case BRW_OPCODE_BFI2:
 926    case BRW_OPCODE_BFREV:
 927    case BRW_OPCODE_CBIT:
 928    case BRW_OPCODE_FBH:
 929    case BRW_OPCODE_FBL:
 930    case BRW_OPCODE_SUBB:
 931       return false;
 932    default:
 933       return true;
 934    }
 935 }
 936
 937 bool
 938 backend_instruction::can_do_saturate() const
 939 {
 940    switch (opcode) {
 941    case BRW_OPCODE_ADD:
 942    case BRW_OPCODE_ASR:
 943    case BRW_OPCODE_AVG:
 944    case BRW_OPCODE_DP2:
 945    case BRW_OPCODE_DP3:
 946    case BRW_OPCODE_DP4:
 947    case BRW_OPCODE_DPH:
 948    case BRW_OPCODE_F16TO32:
 949    case BRW_OPCODE_F32TO16:
 950    case BRW_OPCODE_LINE:
 951    case BRW_OPCODE_LRP:
 952    case BRW_OPCODE_MAC:
 953    case BRW_OPCODE_MACH:
 954    case BRW_OPCODE_MAD:
 955    case BRW_OPCODE_MATH:
 956    case BRW_OPCODE_MOV:
 957    case BRW_OPCODE_MUL:
 958    case BRW_OPCODE_PLN:
 959    case BRW_OPCODE_RNDD:
 960    case BRW_OPCODE_RNDE:
 961    case BRW_OPCODE_RNDU:
 962    case BRW_OPCODE_RNDZ:
 963    case BRW_OPCODE_SEL:
 964    case BRW_OPCODE_SHL:
 965    case BRW_OPCODE_SHR:
 966    case FS_OPCODE_LINTERP:
 967    case SHADER_OPCODE_COS:
 968    case SHADER_OPCODE_EXP2:
 969    case SHADER_OPCODE_LOG2:
 970    case SHADER_OPCODE_POW:
 971    case SHADER_OPCODE_RCP:
 972    case SHADER_OPCODE_RSQ:
 973    case SHADER_OPCODE_SIN:
 974    case SHADER_OPCODE_SQRT:
 975       return true;
 976    default:
 977       return false;
 978    }
 979 }
 980
 981 bool
 982 backend_instruction::can_do_cmod() const
 983 {
 984    switch (opcode) {
 985    case BRW_OPCODE_ADD:
 986    case BRW_OPCODE_ADDC:
 987    case BRW_OPCODE_AND:
 988    case BRW_OPCODE_ASR:
 989    case BRW_OPCODE_AVG:
 990    case BRW_OPCODE_CMP:
 991    case BRW_OPCODE_CMPN:
 992    case BRW_OPCODE_DP2:
 993    case BRW_OPCODE_DP3:
 994    case BRW_OPCODE_DP4:
 995    case BRW_OPCODE_DPH:
 996    case BRW_OPCODE_F16TO32:
 997    case BRW_OPCODE_F32TO16:
 998    case BRW_OPCODE_FRC:
 999    case BRW_OPCODE_LINE:
1000    case BRW_OPCODE_LRP:
1001    case BRW_OPCODE_LZD:
1002    case BRW_OPCODE_MAC:
1003    case BRW_OPCODE_MACH:
1004    case BRW_OPCODE_MAD:
1005    case BRW_OPCODE_MOV:
1006    case BRW_OPCODE_MUL:
1007    case BRW_OPCODE_NOT:
1008    case BRW_OPCODE_OR:
1009    case BRW_OPCODE_PLN:
1010    case BRW_OPCODE_RNDD:
1011    case BRW_OPCODE_RNDE:
1012    case BRW_OPCODE_RNDU:
1013    case BRW_OPCODE_RNDZ:
1014    case BRW_OPCODE_SAD2:
1015    case BRW_OPCODE_SADA2:
1016    case BRW_OPCODE_SHL:
1017    case BRW_OPCODE_SHR:
1018    case BRW_OPCODE_SUBB:
1019    case BRW_OPCODE_XOR:
1020    case FS_OPCODE_CINTERP:
1021    case FS_OPCODE_LINTERP:
1022       return true;
1023    default:
1024       return false;
1025    }
1026 }
1027
1028 bool
1029 backend_instruction::reads_accumulator_implicitly() const
1030 {
1031    switch (opcode) {
1032    case BRW_OPCODE_MAC:
1033    case BRW_OPCODE_MACH:
1034    case BRW_OPCODE_SADA2:
1035       return true;
1036    default:
1037       return false;
1038    }
1039 }
1040
1041 bool
1042 backend_instruction::writes_accumulator_implicitly(const struct brw_device_info *devinfo) const
1043 {
1044    return writes_accumulator ||
1045           (devinfo->gen < 6 &&
1046            ((opcode >= BRW_OPCODE_ADD && opcode < BRW_OPCODE_NOP) ||
1047             (opcode >= FS_OPCODE_DDX_COARSE && opcode <= FS_OPCODE_LINTERP &&
1048              opcode != FS_OPCODE_CINTERP)));
1049 }
1050
1051 bool
1052 backend_instruction::has_side_effects() const
1053 {
1054    switch (opcode) {
1055    case SHADER_OPCODE_UNTYPED_ATOMIC:
1056    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1057    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
1058    case SHADER_OPCODE_TYPED_ATOMIC:
1059    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
1060    case SHADER_OPCODE_MEMORY_FENCE:
1061    case SHADER_OPCODE_URB_WRITE_SIMD8:
1062    case FS_OPCODE_FB_WRITE:
1063       return true;
1064    default:
1065       return false;
1066    }
1067 }
1068
1069 #ifndef NDEBUG
1070 static bool
1071 inst_is_in_block(const bblock_t *block, const backend_instruction *inst)
1072 {
1073    bool found = false;
1074    foreach_inst_in_block (backend_instruction, i, block) {
1075       if (inst == i) {
1076          found = true;
1077       }
1078    }
1079    return found;
1080 }
1081 #endif
1082
1083 static void
1084 adjust_later_block_ips(bblock_t *start_block, int ip_adjustment)
1085 {
1086    for (bblock_t *block_iter = start_block->next();
1087         !block_iter->link.is_tail_sentinel();
1088         block_iter = block_iter->next()) {
1089       block_iter->start_ip += ip_adjustment;
1090       block_iter->end_ip += ip_adjustment;
1091    }
1092 }
1093
1094 void
1095 backend_instruction::insert_after(bblock_t *block, backend_instruction *inst)
1096 {
1097    if (!this->is_head_sentinel())
1098       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1099
1100    block->end_ip++;
1101
1102    adjust_later_block_ips(block, 1);
1103
1104    exec_node::insert_after(inst);
1105 }
1106
1107 void
1108 backend_instruction::insert_before(bblock_t *block, backend_instruction *inst)
1109 {
1110    if (!this->is_tail_sentinel())
1111       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1112
1113    block->end_ip++;
1114
1115    adjust_later_block_ips(block, 1);
1116
1117    exec_node::insert_before(inst);
1118 }
1119
1120 void
1121 backend_instruction::insert_before(bblock_t *block, exec_list *list)
1122 {
1123    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1124
1125    unsigned num_inst = list->length();
1126
1127    block->end_ip += num_inst;
1128
1129    adjust_later_block_ips(block, num_inst);
1130
1131    exec_node::insert_before(list);
1132 }
1133
1134 void
1135 backend_instruction::remove(bblock_t *block)
1136 {
1137    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1138
1139    adjust_later_block_ips(block, -1);
1140
1141    if (block->start_ip == block->end_ip) {
1142       block->cfg->remove_block(block);
1143    } else {
1144       block->end_ip--;
1145    }
1146
1147    exec_node::remove();
1148 }
1149
1150 void
1151 backend_visitor::dump_instructions()
1152 {
1153    dump_instructions(NULL);
1154 }
1155
1156 void
1157 backend_visitor::dump_instructions(const char *name)
1158 {
1159    FILE *file = stderr;
1160    if (name && geteuid() != 0) {
1161       file = fopen(name, "w");
1162       if (!file)
1163          file = stderr;
1164    }
1165
1166    if (cfg) {
1167       int ip = 0;
1168       foreach_block_and_inst(block, backend_instruction, inst, cfg) {
1169          fprintf(file, "%4d: ", ip++);
1170          dump_instruction(inst, file);
1171       }
1172    } else {
1173       int ip = 0;
1174       foreach_in_list(backend_instruction, inst, &instructions) {
1175          fprintf(file, "%4d: ", ip++);
1176          dump_instruction(inst, file);
1177       }
1178    }
1179
1180    if (file != stderr) {
1181       fclose(file);
1182    }
1183 }
1184
1185 void
1186 backend_visitor::calculate_cfg()
1187 {
1188    if (this->cfg)
1189       return;
1190    cfg = new(mem_ctx) cfg_t(&this->instructions);
1191 }
1192
1193 void
1194 backend_visitor::invalidate_cfg()
1195 {
1196    ralloc_free(this->cfg);
1197    this->cfg = NULL;
1198 }
1199
1200 /**
1201  * Sets up the starting offsets for the groups of binding table entries
1202  * commong to all pipeline stages.
1203  *
1204  * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
1205  * unused but also make sure that addition of small offsets to them will
1206  * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
1207  */
1208 void
1209 backend_visitor::assign_common_binding_table_offsets(uint32_t next_binding_table_offset)
1210 {
1211    int num_textures = _mesa_fls(prog->SamplersUsed);
1212
1213    stage_prog_data->binding_table.texture_start = next_binding_table_offset;
1214    next_binding_table_offset += num_textures;
1215
1216    if (shader) {
1217       stage_prog_data->binding_table.ubo_start = next_binding_table_offset;
1218       next_binding_table_offset += shader->base.NumUniformBlocks;
1219    } else {
1220       stage_prog_data->binding_table.ubo_start = 0xd0d0d0d0;
1221    }
1222
1223    if (INTEL_DEBUG & DEBUG_SHADER_TIME) {
1224       stage_prog_data->binding_table.shader_time_start = next_binding_table_offset;
1225       next_binding_table_offset++;
1226    } else {
1227       stage_prog_data->binding_table.shader_time_start = 0xd0d0d0d0;
1228    }
1229
1230    if (prog->UsesGather) {
1231       if (devinfo->gen >= 8) {
1232          stage_prog_data->binding_table.gather_texture_start =
1233             stage_prog_data->binding_table.texture_start;
1234       } else {
1235          stage_prog_data->binding_table.gather_texture_start = next_binding_table_offset;
1236          next_binding_table_offset += num_textures;
1237       }
1238    } else {
1239       stage_prog_data->binding_table.gather_texture_start = 0xd0d0d0d0;
1240    }
1241
1242    if (shader_prog && shader_prog->NumAtomicBuffers) {
1243       stage_prog_data->binding_table.abo_start = next_binding_table_offset;
1244       next_binding_table_offset += shader_prog->NumAtomicBuffers;
1245    } else {
1246       stage_prog_data->binding_table.abo_start = 0xd0d0d0d0;
1247    }
1248
1249    if (shader && shader->base.NumImages) {
1250       stage_prog_data->binding_table.image_start = next_binding_table_offset;
1251       next_binding_table_offset += shader->base.NumImages;
1252    } else {
1253       stage_prog_data->binding_table.image_start = 0xd0d0d0d0;
1254    }
1255
1256    /* This may or may not be used depending on how the compile goes. */
1257    stage_prog_data->binding_table.pull_constants_start = next_binding_table_offset;
1258    next_binding_table_offset++;
1259
1260    assert(next_binding_table_offset <= BRW_MAX_SURFACES);
1261
1262    /* prog_data->base.binding_table.size will be set by brw_mark_surface_used. */
1263 }