src/mesa/drivers/dri/i965/brw_shader.cpp

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "main/macros.h"
  25 #include "brw_context.h"
  26 #include "brw_vs.h"
  27 #include "brw_gs.h"
  28 #include "brw_fs.h"
  29 #include "brw_cfg.h"
  30 #include "brw_nir.h"
  31 #include "glsl/ir_optimization.h"
  32 #include "glsl/glsl_parser_extras.h"
  33 #include "main/shaderapi.h"
  34
  35 struct brw_compiler *
  36 brw_compiler_create(void *mem_ctx, const struct brw_device_info *devinfo)
  37 {
  38    struct brw_compiler *compiler = rzalloc(mem_ctx, struct brw_compiler);
  39
  40    compiler->devinfo = devinfo;
  41
  42    brw_fs_alloc_reg_sets(compiler);
  43    brw_vec4_alloc_reg_set(compiler);
  44
  45    return compiler;
  46 }
  47
  48 struct gl_shader *
  49 brw_new_shader(struct gl_context *ctx, GLuint name, GLuint type)
  50 {
  51    struct brw_shader *shader;
  52
  53    shader = rzalloc(NULL, struct brw_shader);
  54    if (shader) {
  55       shader->base.Type = type;
  56       shader->base.Stage = _mesa_shader_enum_to_shader_stage(type);
  57       shader->base.Name = name;
  58       _mesa_init_shader(ctx, &shader->base);
  59    }
  60
  61    return &shader->base;
  62 }
  63
  64 /**
  65  * Performs a compile of the shader stages even when we don't know
  66  * what non-orthogonal state will be set, in the hope that it reflects
  67  * the eventual NOS used, and thus allows us to produce link failures.
  68  */
  69 static bool
  70 brw_shader_precompile(struct gl_context *ctx,
  71                       struct gl_shader_program *sh_prog)
  72 {
  73    struct gl_shader *vs = sh_prog->_LinkedShaders[MESA_SHADER_VERTEX];
  74    struct gl_shader *gs = sh_prog->_LinkedShaders[MESA_SHADER_GEOMETRY];
  75    struct gl_shader *fs = sh_prog->_LinkedShaders[MESA_SHADER_FRAGMENT];
  76    struct gl_shader *cs = sh_prog->_LinkedShaders[MESA_SHADER_COMPUTE];
  77
  78    if (fs && !brw_fs_precompile(ctx, sh_prog, fs->Program))
  79       return false;
  80
  81    if (gs && !brw_gs_precompile(ctx, sh_prog, gs->Program))
  82       return false;
  83
  84    if (vs && !brw_vs_precompile(ctx, sh_prog, vs->Program))
  85       return false;
  86
  87    if (cs && !brw_cs_precompile(ctx, sh_prog, cs->Program))
  88       return false;
  89
  90    return true;
  91 }
  92
  93 static inline bool
  94 is_scalar_shader_stage(struct brw_context *brw, int stage)
  95 {
  96    switch (stage) {
  97    case MESA_SHADER_FRAGMENT:
  98       return true;
  99    case MESA_SHADER_VERTEX:
 100       return brw->scalar_vs;
 101    default:
 102       return false;
 103    }
 104 }
 105
 106 static void
 107 brw_lower_packing_builtins(struct brw_context *brw,
 108                            gl_shader_stage shader_type,
 109                            exec_list *ir)
 110 {
 111    int ops = LOWER_PACK_SNORM_2x16
 112            | LOWER_UNPACK_SNORM_2x16
 113            | LOWER_PACK_UNORM_2x16
 114            | LOWER_UNPACK_UNORM_2x16;
 115
 116    if (is_scalar_shader_stage(brw, shader_type)) {
 117       ops |= LOWER_UNPACK_UNORM_4x8
 118            | LOWER_UNPACK_SNORM_4x8
 119            | LOWER_PACK_UNORM_4x8
 120            | LOWER_PACK_SNORM_4x8;
 121    }
 122
 123    if (brw->gen >= 7) {
 124       /* Gen7 introduced the f32to16 and f16to32 instructions, which can be
 125        * used to execute packHalf2x16 and unpackHalf2x16. For AOS code, no
 126        * lowering is needed. For SOA code, the Half2x16 ops must be
 127        * scalarized.
 128        */
 129       if (is_scalar_shader_stage(brw, shader_type)) {
 130          ops |= LOWER_PACK_HALF_2x16_TO_SPLIT
 131              |  LOWER_UNPACK_HALF_2x16_TO_SPLIT;
 132       }
 133    } else {
 134       ops |= LOWER_PACK_HALF_2x16
 135           |  LOWER_UNPACK_HALF_2x16;
 136    }
 137
 138    lower_packing_builtins(ir, ops);
 139 }
 140
 141 static void
 142 process_glsl_ir(struct brw_context *brw,
 143                 struct gl_shader_program *shader_prog,
 144                 struct gl_shader *shader)
 145 {
 146    struct gl_context *ctx = &brw->ctx;
 147    const struct gl_shader_compiler_options *options =
 148       &ctx->Const.ShaderCompilerOptions[shader->Stage];
 149
 150    /* Temporary memory context for any new IR. */
 151    void *mem_ctx = ralloc_context(NULL);
 152
 153    ralloc_adopt(mem_ctx, shader->ir);
 154
 155    /* lower_packing_builtins() inserts arithmetic instructions, so it
 156     * must precede lower_instructions().
 157     */
 158    brw_lower_packing_builtins(brw, shader->Stage, shader->ir);
 159    do_mat_op_to_vec(shader->ir);
 160    const int bitfield_insert = brw->gen >= 7 ? BITFIELD_INSERT_TO_BFM_BFI : 0;
 161    lower_instructions(shader->ir,
 162                       MOD_TO_FLOOR |
 163                       DIV_TO_MUL_RCP |
 164                       SUB_TO_ADD_NEG |
 165                       EXP_TO_EXP2 |
 166                       LOG_TO_LOG2 |
 167                       bitfield_insert |
 168                       LDEXP_TO_ARITH);
 169
 170    /* Pre-gen6 HW can only nest if-statements 16 deep.  Beyond this,
 171     * if-statements need to be flattened.
 172     */
 173    if (brw->gen < 6)
 174       lower_if_to_cond_assign(shader->ir, 16);
 175
 176    do_lower_texture_projection(shader->ir);
 177    brw_lower_texture_gradients(brw, shader->ir);
 178    do_vec_index_to_cond_assign(shader->ir);
 179    lower_vector_insert(shader->ir, true);
 180    if (options->NirOptions == NULL)
 181       brw_do_cubemap_normalize(shader->ir);
 182    lower_offset_arrays(shader->ir);
 183    brw_do_lower_unnormalized_offset(shader->ir);
 184    lower_noise(shader->ir);
 185    lower_quadop_vector(shader->ir, false);
 186
 187    bool lowered_variable_indexing =
 188       lower_variable_index_to_cond_assign(shader->ir,
 189                                           options->EmitNoIndirectInput,
 190                                           options->EmitNoIndirectOutput,
 191                                           options->EmitNoIndirectTemp,
 192                                           options->EmitNoIndirectUniform);
 193
 194    if (unlikely(brw->perf_debug && lowered_variable_indexing)) {
 195       perf_debug("Unsupported form of variable indexing in FS; falling "
 196                  "back to very inefficient code generation\n");
 197    }
 198
 199    lower_ubo_reference(shader, shader->ir);
 200
 201    bool progress;
 202    do {
 203       progress = false;
 204
 205       if (is_scalar_shader_stage(brw, shader->Stage)) {
 206          brw_do_channel_expressions(shader->ir);
 207          brw_do_vector_splitting(shader->ir);
 208       }
 209
 210       progress = do_lower_jumps(shader->ir, true, true,
 211                                 true, /* main return */
 212                                 false, /* continue */
 213                                 false /* loops */
 214                                 ) || progress;
 215
 216       progress = do_common_optimization(shader->ir, true, true,
 217                                         options, ctx->Const.NativeIntegers) || progress;
 218    } while (progress);
 219
 220    if (options->NirOptions != NULL)
 221       lower_output_reads(shader->ir);
 222
 223    validate_ir_tree(shader->ir);
 224
 225    /* Now that we've finished altering the linked IR, reparent any live IR back
 226     * to the permanent memory context, and free the temporary one (discarding any
 227     * junk we optimized away).
 228     */
 229    reparent_ir(shader->ir, shader->ir);
 230    ralloc_free(mem_ctx);
 231
 232    if (ctx->_Shader->Flags & GLSL_DUMP) {
 233       fprintf(stderr, "\n");
 234       fprintf(stderr, "GLSL IR for linked %s program %d:\n",
 235               _mesa_shader_stage_to_string(shader->Stage),
 236               shader_prog->Name);
 237       _mesa_print_ir(stderr, shader->ir, NULL);
 238       fprintf(stderr, "\n");
 239    }
 240 }
 241
 242 GLboolean
 243 brw_link_shader(struct gl_context *ctx, struct gl_shader_program *shProg)
 244 {
 245    struct brw_context *brw = brw_context(ctx);
 246    unsigned int stage;
 247
 248    for (stage = 0; stage < ARRAY_SIZE(shProg->_LinkedShaders); stage++) {
 249       struct gl_shader *shader = shProg->_LinkedShaders[stage];
 250       const struct gl_shader_compiler_options *options =
 251          &ctx->Const.ShaderCompilerOptions[stage];
 252
 253       if (!shader)
 254          continue;
 255
 256       struct gl_program *prog =
 257          ctx->Driver.NewProgram(ctx, _mesa_shader_stage_to_program(stage),
 258                                 shader->Name);
 259       if (!prog)
 260         return false;
 261       prog->Parameters = _mesa_new_parameter_list();
 262
 263       _mesa_copy_linked_program_data((gl_shader_stage) stage, shProg, prog);
 264
 265       process_glsl_ir(brw, shProg, shader);
 266
 267       /* Make a pass over the IR to add state references for any built-in
 268        * uniforms that are used.  This has to be done now (during linking).
 269        * Code generation doesn't happen until the first time this shader is
 270        * used for rendering.  Waiting until then to generate the parameters is
 271        * too late.  At that point, the values for the built-in uniforms won't
 272        * get sent to the shader.
 273        */
 274       foreach_in_list(ir_instruction, node, shader->ir) {
 275          ir_variable *var = node->as_variable();
 276
 277          if ((var == NULL) || (var->data.mode != ir_var_uniform)
 278              || (strncmp(var->name, "gl_", 3) != 0))
 279             continue;
 280
 281          const ir_state_slot *const slots = var->get_state_slots();
 282          assert(slots != NULL);
 283
 284          for (unsigned int i = 0; i < var->get_num_state_slots(); i++) {
 285             _mesa_add_state_reference(prog->Parameters,
 286                                       (gl_state_index *) slots[i].tokens);
 287          }
 288       }
 289
 290       do_set_program_inouts(shader->ir, prog, shader->Stage);
 291
 292       prog->SamplersUsed = shader->active_samplers;
 293       prog->ShadowSamplers = shader->shadow_samplers;
 294       _mesa_update_shader_textures_used(shProg, prog);
 295
 296       _mesa_reference_program(ctx, &shader->Program, prog);
 297
 298       brw_add_texrect_params(prog);
 299
 300       if (options->NirOptions)
 301          prog->nir = brw_create_nir(brw, shProg, prog, (gl_shader_stage) stage);
 302
 303       _mesa_reference_program(ctx, &prog, NULL);
 304    }
 305
 306    if ((ctx->_Shader->Flags & GLSL_DUMP) && shProg->Name != 0) {
 307       for (unsigned i = 0; i < shProg->NumShaders; i++) {
 308          const struct gl_shader *sh = shProg->Shaders[i];
 309          if (!sh)
 310             continue;
 311
 312          fprintf(stderr, "GLSL %s shader %d source for linked program %d:\n",
 313                  _mesa_shader_stage_to_string(sh->Stage),
 314                  i, shProg->Name);
 315          fprintf(stderr, "%s", sh->Source);
 316          fprintf(stderr, "\n");
 317       }
 318    }
 319
 320    if (brw->precompile && !brw_shader_precompile(ctx, shProg))
 321       return false;
 322
 323    return true;
 324 }
 325
 326
 327 enum brw_reg_type
 328 brw_type_for_base_type(const struct glsl_type *type)
 329 {
 330    switch (type->base_type) {
 331    case GLSL_TYPE_FLOAT:
 332       return BRW_REGISTER_TYPE_F;
 333    case GLSL_TYPE_INT:
 334    case GLSL_TYPE_BOOL:
 335       return BRW_REGISTER_TYPE_D;
 336    case GLSL_TYPE_UINT:
 337       return BRW_REGISTER_TYPE_UD;
 338    case GLSL_TYPE_ARRAY:
 339       return brw_type_for_base_type(type->fields.array);
 340    case GLSL_TYPE_STRUCT:
 341    case GLSL_TYPE_SAMPLER:
 342    case GLSL_TYPE_ATOMIC_UINT:
 343       /* These should be overridden with the type of the member when
 344        * dereferenced into.  BRW_REGISTER_TYPE_UD seems like a likely
 345        * way to trip up if we don't.
 346        */
 347       return BRW_REGISTER_TYPE_UD;
 348    case GLSL_TYPE_IMAGE:
 349       return BRW_REGISTER_TYPE_UD;
 350    case GLSL_TYPE_VOID:
 351    case GLSL_TYPE_ERROR:
 352    case GLSL_TYPE_INTERFACE:
 353    case GLSL_TYPE_DOUBLE:
 354       unreachable("not reached");
 355    }
 356
 357    return BRW_REGISTER_TYPE_F;
 358 }
 359
 360 enum brw_conditional_mod
 361 brw_conditional_for_comparison(unsigned int op)
 362 {
 363    switch (op) {
 364    case ir_binop_less:
 365       return BRW_CONDITIONAL_L;
 366    case ir_binop_greater:
 367       return BRW_CONDITIONAL_G;
 368    case ir_binop_lequal:
 369       return BRW_CONDITIONAL_LE;
 370    case ir_binop_gequal:
 371       return BRW_CONDITIONAL_GE;
 372    case ir_binop_equal:
 373    case ir_binop_all_equal: /* same as equal for scalars */
 374       return BRW_CONDITIONAL_Z;
 375    case ir_binop_nequal:
 376    case ir_binop_any_nequal: /* same as nequal for scalars */
 377       return BRW_CONDITIONAL_NZ;
 378    default:
 379       unreachable("not reached: bad operation for comparison");
 380    }
 381 }
 382
 383 uint32_t
 384 brw_math_function(enum opcode op)
 385 {
 386    switch (op) {
 387    case SHADER_OPCODE_RCP:
 388       return BRW_MATH_FUNCTION_INV;
 389    case SHADER_OPCODE_RSQ:
 390       return BRW_MATH_FUNCTION_RSQ;
 391    case SHADER_OPCODE_SQRT:
 392       return BRW_MATH_FUNCTION_SQRT;
 393    case SHADER_OPCODE_EXP2:
 394       return BRW_MATH_FUNCTION_EXP;
 395    case SHADER_OPCODE_LOG2:
 396       return BRW_MATH_FUNCTION_LOG;
 397    case SHADER_OPCODE_POW:
 398       return BRW_MATH_FUNCTION_POW;
 399    case SHADER_OPCODE_SIN:
 400       return BRW_MATH_FUNCTION_SIN;
 401    case SHADER_OPCODE_COS:
 402       return BRW_MATH_FUNCTION_COS;
 403    case SHADER_OPCODE_INT_QUOTIENT:
 404       return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT;
 405    case SHADER_OPCODE_INT_REMAINDER:
 406       return BRW_MATH_FUNCTION_INT_DIV_REMAINDER;
 407    default:
 408       unreachable("not reached: unknown math function");
 409    }
 410 }
 411
 412 uint32_t
 413 brw_texture_offset(int *offsets, unsigned num_components)
 414 {
 415    if (!offsets) return 0;  /* nonconstant offset; caller will handle it. */
 416
 417    /* Combine all three offsets into a single unsigned dword:
 418     *
 419     *    bits 11:8 - U Offset (X component)
 420     *    bits  7:4 - V Offset (Y component)
 421     *    bits  3:0 - R Offset (Z component)
 422     */
 423    unsigned offset_bits = 0;
 424    for (unsigned i = 0; i < num_components; i++) {
 425       const unsigned shift = 4 * (2 - i);
 426       offset_bits |= (offsets[i] << shift) & (0xF << shift);
 427    }
 428    return offset_bits;
 429 }
 430
 431 const char *
 432 brw_instruction_name(enum opcode op)
 433 {
 434    switch (op) {
 435    case BRW_OPCODE_MOV ... BRW_OPCODE_NOP:
 436       assert(opcode_descs[op].name);
 437       return opcode_descs[op].name;
 438    case FS_OPCODE_FB_WRITE:
 439       return "fb_write";
 440    case FS_OPCODE_BLORP_FB_WRITE:
 441       return "blorp_fb_write";
 442    case FS_OPCODE_REP_FB_WRITE:
 443       return "rep_fb_write";
 444
 445    case SHADER_OPCODE_RCP:
 446       return "rcp";
 447    case SHADER_OPCODE_RSQ:
 448       return "rsq";
 449    case SHADER_OPCODE_SQRT:
 450       return "sqrt";
 451    case SHADER_OPCODE_EXP2:
 452       return "exp2";
 453    case SHADER_OPCODE_LOG2:
 454       return "log2";
 455    case SHADER_OPCODE_POW:
 456       return "pow";
 457    case SHADER_OPCODE_INT_QUOTIENT:
 458       return "int_quot";
 459    case SHADER_OPCODE_INT_REMAINDER:
 460       return "int_rem";
 461    case SHADER_OPCODE_SIN:
 462       return "sin";
 463    case SHADER_OPCODE_COS:
 464       return "cos";
 465
 466    case SHADER_OPCODE_TEX:
 467       return "tex";
 468    case SHADER_OPCODE_TXD:
 469       return "txd";
 470    case SHADER_OPCODE_TXF:
 471       return "txf";
 472    case SHADER_OPCODE_TXL:
 473       return "txl";
 474    case SHADER_OPCODE_TXS:
 475       return "txs";
 476    case FS_OPCODE_TXB:
 477       return "txb";
 478    case SHADER_OPCODE_TXF_CMS:
 479       return "txf_cms";
 480    case SHADER_OPCODE_TXF_UMS:
 481       return "txf_ums";
 482    case SHADER_OPCODE_TXF_MCS:
 483       return "txf_mcs";
 484    case SHADER_OPCODE_LOD:
 485       return "lod";
 486    case SHADER_OPCODE_TG4:
 487       return "tg4";
 488    case SHADER_OPCODE_TG4_OFFSET:
 489       return "tg4_offset";
 490    case SHADER_OPCODE_SHADER_TIME_ADD:
 491       return "shader_time_add";
 492
 493    case SHADER_OPCODE_UNTYPED_ATOMIC:
 494       return "untyped_atomic";
 495    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
 496       return "untyped_surface_read";
 497    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
 498       return "untyped_surface_write";
 499    case SHADER_OPCODE_TYPED_ATOMIC:
 500       return "typed_atomic";
 501    case SHADER_OPCODE_TYPED_SURFACE_READ:
 502       return "typed_surface_read";
 503    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
 504       return "typed_surface_write";
 505    case SHADER_OPCODE_MEMORY_FENCE:
 506       return "memory_fence";
 507
 508    case SHADER_OPCODE_LOAD_PAYLOAD:
 509       return "load_payload";
 510
 511    case SHADER_OPCODE_GEN4_SCRATCH_READ:
 512       return "gen4_scratch_read";
 513    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 514       return "gen4_scratch_write";
 515    case SHADER_OPCODE_GEN7_SCRATCH_READ:
 516       return "gen7_scratch_read";
 517    case SHADER_OPCODE_URB_WRITE_SIMD8:
 518       return "gen8_urb_write_simd8";
 519
 520    case SHADER_OPCODE_FIND_LIVE_CHANNEL:
 521       return "find_live_channel";
 522    case SHADER_OPCODE_BROADCAST:
 523       return "broadcast";
 524
 525    case VEC4_OPCODE_MOV_BYTES:
 526       return "mov_bytes";
 527    case VEC4_OPCODE_PACK_BYTES:
 528       return "pack_bytes";
 529    case VEC4_OPCODE_UNPACK_UNIFORM:
 530       return "unpack_uniform";
 531
 532    case FS_OPCODE_DDX_COARSE:
 533       return "ddx_coarse";
 534    case FS_OPCODE_DDX_FINE:
 535       return "ddx_fine";
 536    case FS_OPCODE_DDY_COARSE:
 537       return "ddy_coarse";
 538    case FS_OPCODE_DDY_FINE:
 539       return "ddy_fine";
 540
 541    case FS_OPCODE_CINTERP:
 542       return "cinterp";
 543    case FS_OPCODE_LINTERP:
 544       return "linterp";
 545
 546    case FS_OPCODE_PIXEL_X:
 547       return "pixel_x";
 548    case FS_OPCODE_PIXEL_Y:
 549       return "pixel_y";
 550
 551    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
 552       return "uniform_pull_const";
 553    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
 554       return "uniform_pull_const_gen7";
 555    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
 556       return "varying_pull_const";
 557    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
 558       return "varying_pull_const_gen7";
 559
 560    case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
 561       return "mov_dispatch_to_flags";
 562    case FS_OPCODE_DISCARD_JUMP:
 563       return "discard_jump";
 564
 565    case FS_OPCODE_SET_OMASK:
 566       return "set_omask";
 567    case FS_OPCODE_SET_SAMPLE_ID:
 568       return "set_sample_id";
 569    case FS_OPCODE_SET_SIMD4X2_OFFSET:
 570       return "set_simd4x2_offset";
 571
 572    case FS_OPCODE_PACK_HALF_2x16_SPLIT:
 573       return "pack_half_2x16_split";
 574    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
 575       return "unpack_half_2x16_split_x";
 576    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
 577       return "unpack_half_2x16_split_y";
 578
 579    case FS_OPCODE_PLACEHOLDER_HALT:
 580       return "placeholder_halt";
 581
 582    case FS_OPCODE_INTERPOLATE_AT_CENTROID:
 583       return "interp_centroid";
 584    case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
 585       return "interp_sample";
 586    case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
 587       return "interp_shared_offset";
 588    case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
 589       return "interp_per_slot_offset";
 590
 591    case VS_OPCODE_URB_WRITE:
 592       return "vs_urb_write";
 593    case VS_OPCODE_PULL_CONSTANT_LOAD:
 594       return "pull_constant_load";
 595    case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
 596       return "pull_constant_load_gen7";
 597
 598    case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
 599       return "set_simd4x2_header_gen9";
 600
 601    case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
 602       return "unpack_flags_simd4x2";
 603
 604    case GS_OPCODE_URB_WRITE:
 605       return "gs_urb_write";
 606    case GS_OPCODE_URB_WRITE_ALLOCATE:
 607       return "gs_urb_write_allocate";
 608    case GS_OPCODE_THREAD_END:
 609       return "gs_thread_end";
 610    case GS_OPCODE_SET_WRITE_OFFSET:
 611       return "set_write_offset";
 612    case GS_OPCODE_SET_VERTEX_COUNT:
 613       return "set_vertex_count";
 614    case GS_OPCODE_SET_DWORD_2:
 615       return "set_dword_2";
 616    case GS_OPCODE_PREPARE_CHANNEL_MASKS:
 617       return "prepare_channel_masks";
 618    case GS_OPCODE_SET_CHANNEL_MASKS:
 619       return "set_channel_masks";
 620    case GS_OPCODE_GET_INSTANCE_ID:
 621       return "get_instance_id";
 622    case GS_OPCODE_FF_SYNC:
 623       return "ff_sync";
 624    case GS_OPCODE_SET_PRIMITIVE_ID:
 625       return "set_primitive_id";
 626    case GS_OPCODE_SVB_WRITE:
 627       return "gs_svb_write";
 628    case GS_OPCODE_SVB_SET_DST_INDEX:
 629       return "gs_svb_set_dst_index";
 630    case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
 631       return "gs_ff_sync_set_primitives";
 632    case CS_OPCODE_CS_TERMINATE:
 633       return "cs_terminate";
 634    case SHADER_OPCODE_BARRIER:
 635       return "barrier";
 636    }
 637
 638    unreachable("not reached");
 639 }
 640
 641 bool
 642 brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 643 {
 644    union {
 645       unsigned ud;
 646       int d;
 647       float f;
 648    } imm = { reg->dw1.ud }, sat_imm = { 0 };
 649
 650    switch (type) {
 651    case BRW_REGISTER_TYPE_UD:
 652    case BRW_REGISTER_TYPE_D:
 653    case BRW_REGISTER_TYPE_UQ:
 654    case BRW_REGISTER_TYPE_Q:
 655       /* Nothing to do. */
 656       return false;
 657    case BRW_REGISTER_TYPE_UW:
 658       sat_imm.ud = CLAMP(imm.ud, 0, USHRT_MAX);
 659       break;
 660    case BRW_REGISTER_TYPE_W:
 661       sat_imm.d = CLAMP(imm.d, SHRT_MIN, SHRT_MAX);
 662       break;
 663    case BRW_REGISTER_TYPE_F:
 664       sat_imm.f = CLAMP(imm.f, 0.0f, 1.0f);
 665       break;
 666    case BRW_REGISTER_TYPE_UB:
 667    case BRW_REGISTER_TYPE_B:
 668       unreachable("no UB/B immediates");
 669    case BRW_REGISTER_TYPE_V:
 670    case BRW_REGISTER_TYPE_UV:
 671    case BRW_REGISTER_TYPE_VF:
 672       unreachable("unimplemented: saturate vector immediate");
 673    case BRW_REGISTER_TYPE_DF:
 674    case BRW_REGISTER_TYPE_HF:
 675       unreachable("unimplemented: saturate DF/HF immediate");
 676    }
 677
 678    if (imm.ud != sat_imm.ud) {
 679       reg->dw1.ud = sat_imm.ud;
 680       return true;
 681    }
 682    return false;
 683 }
 684
 685 bool
 686 brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 687 {
 688    switch (type) {
 689    case BRW_REGISTER_TYPE_D:
 690    case BRW_REGISTER_TYPE_UD:
 691       reg->dw1.d = -reg->dw1.d;
 692       return true;
 693    case BRW_REGISTER_TYPE_W:
 694    case BRW_REGISTER_TYPE_UW:
 695       reg->dw1.d = -(int16_t)reg->dw1.ud;
 696       return true;
 697    case BRW_REGISTER_TYPE_F:
 698       reg->dw1.f = -reg->dw1.f;
 699       return true;
 700    case BRW_REGISTER_TYPE_VF:
 701       reg->dw1.ud ^= 0x80808080;
 702       return true;
 703    case BRW_REGISTER_TYPE_UB:
 704    case BRW_REGISTER_TYPE_B:
 705       unreachable("no UB/B immediates");
 706    case BRW_REGISTER_TYPE_UV:
 707    case BRW_REGISTER_TYPE_V:
 708       assert(!"unimplemented: negate UV/V immediate");
 709    case BRW_REGISTER_TYPE_UQ:
 710    case BRW_REGISTER_TYPE_Q:
 711       assert(!"unimplemented: negate UQ/Q immediate");
 712    case BRW_REGISTER_TYPE_DF:
 713    case BRW_REGISTER_TYPE_HF:
 714       assert(!"unimplemented: negate DF/HF immediate");
 715    }
 716
 717    return false;
 718 }
 719
 720 bool
 721 brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg)
 722 {
 723    switch (type) {
 724    case BRW_REGISTER_TYPE_D:
 725       reg->dw1.d = abs(reg->dw1.d);
 726       return true;
 727    case BRW_REGISTER_TYPE_W:
 728       reg->dw1.d = abs((int16_t)reg->dw1.ud);
 729       return true;
 730    case BRW_REGISTER_TYPE_F:
 731       reg->dw1.f = fabsf(reg->dw1.f);
 732       return true;
 733    case BRW_REGISTER_TYPE_VF:
 734       reg->dw1.ud &= ~0x80808080;
 735       return true;
 736    case BRW_REGISTER_TYPE_UB:
 737    case BRW_REGISTER_TYPE_B:
 738       unreachable("no UB/B immediates");
 739    case BRW_REGISTER_TYPE_UQ:
 740    case BRW_REGISTER_TYPE_UD:
 741    case BRW_REGISTER_TYPE_UW:
 742    case BRW_REGISTER_TYPE_UV:
 743       /* Presumably the absolute value modifier on an unsigned source is a
 744        * nop, but it would be nice to confirm.
 745        */
 746       assert(!"unimplemented: abs unsigned immediate");
 747    case BRW_REGISTER_TYPE_V:
 748       assert(!"unimplemented: abs V immediate");
 749    case BRW_REGISTER_TYPE_Q:
 750       assert(!"unimplemented: abs Q immediate");
 751    case BRW_REGISTER_TYPE_DF:
 752    case BRW_REGISTER_TYPE_HF:
 753       assert(!"unimplemented: abs DF/HF immediate");
 754    }
 755
 756    return false;
 757 }
 758
 759 backend_shader::backend_shader(struct brw_context *brw,
 760                                void *mem_ctx,
 761                                struct gl_shader_program *shader_prog,
 762                                struct gl_program *prog,
 763                                struct brw_stage_prog_data *stage_prog_data,
 764                                gl_shader_stage stage)
 765    : brw(brw),
 766      devinfo(brw->intelScreen->devinfo),
 767      ctx(&brw->ctx),
 768      shader(shader_prog ?
 769         (struct brw_shader *)shader_prog->_LinkedShaders[stage] : NULL),
 770      shader_prog(shader_prog),
 771      prog(prog),
 772      stage_prog_data(stage_prog_data),
 773      mem_ctx(mem_ctx),
 774      cfg(NULL),
 775      stage(stage)
 776 {
 777    debug_enabled = INTEL_DEBUG & intel_debug_flag_for_shader_stage(stage);
 778    stage_name = _mesa_shader_stage_to_string(stage);
 779    stage_abbrev = _mesa_shader_stage_to_abbrev(stage);
 780 }
 781
 782 bool
 783 backend_reg::is_zero() const
 784 {
 785    if (file != IMM)
 786       return false;
 787
 788    return fixed_hw_reg.dw1.d == 0;
 789 }
 790
 791 bool
 792 backend_reg::is_one() const
 793 {
 794    if (file != IMM)
 795       return false;
 796
 797    return type == BRW_REGISTER_TYPE_F
 798           ? fixed_hw_reg.dw1.f == 1.0
 799           : fixed_hw_reg.dw1.d == 1;
 800 }
 801
 802 bool
 803 backend_reg::is_negative_one() const
 804 {
 805    if (file != IMM)
 806       return false;
 807
 808    switch (type) {
 809    case BRW_REGISTER_TYPE_F:
 810       return fixed_hw_reg.dw1.f == -1.0;
 811    case BRW_REGISTER_TYPE_D:
 812       return fixed_hw_reg.dw1.d == -1;
 813    default:
 814       return false;
 815    }
 816 }
 817
 818 bool
 819 backend_reg::is_null() const
 820 {
 821    return file == HW_REG &&
 822           fixed_hw_reg.file == BRW_ARCHITECTURE_REGISTER_FILE &&
 823           fixed_hw_reg.nr == BRW_ARF_NULL;
 824 }
 825
 826
 827 bool
 828 backend_reg::is_accumulator() const
 829 {
 830    return file == HW_REG &&
 831           fixed_hw_reg.file == BRW_ARCHITECTURE_REGISTER_FILE &&
 832           fixed_hw_reg.nr == BRW_ARF_ACCUMULATOR;
 833 }
 834
 835 bool
 836 backend_reg::in_range(const backend_reg &r, unsigned n) const
 837 {
 838    return (file == r.file &&
 839            reg == r.reg &&
 840            reg_offset >= r.reg_offset &&
 841            reg_offset < r.reg_offset + n);
 842 }
 843
 844 bool
 845 backend_instruction::is_commutative() const
 846 {
 847    switch (opcode) {
 848    case BRW_OPCODE_AND:
 849    case BRW_OPCODE_OR:
 850    case BRW_OPCODE_XOR:
 851    case BRW_OPCODE_ADD:
 852    case BRW_OPCODE_MUL:
 853       return true;
 854    case BRW_OPCODE_SEL:
 855       /* MIN and MAX are commutative. */
 856       if (conditional_mod == BRW_CONDITIONAL_GE ||
 857           conditional_mod == BRW_CONDITIONAL_L) {
 858          return true;
 859       }
 860       /* fallthrough */
 861    default:
 862       return false;
 863    }
 864 }
 865
 866 bool
 867 backend_instruction::is_3src() const
 868 {
 869    return opcode < ARRAY_SIZE(opcode_descs) && opcode_descs[opcode].nsrc == 3;
 870 }
 871
 872 bool
 873 backend_instruction::is_tex() const
 874 {
 875    return (opcode == SHADER_OPCODE_TEX ||
 876            opcode == FS_OPCODE_TXB ||
 877            opcode == SHADER_OPCODE_TXD ||
 878            opcode == SHADER_OPCODE_TXF ||
 879            opcode == SHADER_OPCODE_TXF_CMS ||
 880            opcode == SHADER_OPCODE_TXF_UMS ||
 881            opcode == SHADER_OPCODE_TXF_MCS ||
 882            opcode == SHADER_OPCODE_TXL ||
 883            opcode == SHADER_OPCODE_TXS ||
 884            opcode == SHADER_OPCODE_LOD ||
 885            opcode == SHADER_OPCODE_TG4 ||
 886            opcode == SHADER_OPCODE_TG4_OFFSET);
 887 }
 888
 889 bool
 890 backend_instruction::is_math() const
 891 {
 892    return (opcode == SHADER_OPCODE_RCP ||
 893            opcode == SHADER_OPCODE_RSQ ||
 894            opcode == SHADER_OPCODE_SQRT ||
 895            opcode == SHADER_OPCODE_EXP2 ||
 896            opcode == SHADER_OPCODE_LOG2 ||
 897            opcode == SHADER_OPCODE_SIN ||
 898            opcode == SHADER_OPCODE_COS ||
 899            opcode == SHADER_OPCODE_INT_QUOTIENT ||
 900            opcode == SHADER_OPCODE_INT_REMAINDER ||
 901            opcode == SHADER_OPCODE_POW);
 902 }
 903
 904 bool
 905 backend_instruction::is_control_flow() const
 906 {
 907    switch (opcode) {
 908    case BRW_OPCODE_DO:
 909    case BRW_OPCODE_WHILE:
 910    case BRW_OPCODE_IF:
 911    case BRW_OPCODE_ELSE:
 912    case BRW_OPCODE_ENDIF:
 913    case BRW_OPCODE_BREAK:
 914    case BRW_OPCODE_CONTINUE:
 915       return true;
 916    default:
 917       return false;
 918    }
 919 }
 920
 921 bool
 922 backend_instruction::can_do_source_mods() const
 923 {
 924    switch (opcode) {
 925    case BRW_OPCODE_ADDC:
 926    case BRW_OPCODE_BFE:
 927    case BRW_OPCODE_BFI1:
 928    case BRW_OPCODE_BFI2:
 929    case BRW_OPCODE_BFREV:
 930    case BRW_OPCODE_CBIT:
 931    case BRW_OPCODE_FBH:
 932    case BRW_OPCODE_FBL:
 933    case BRW_OPCODE_SUBB:
 934       return false;
 935    default:
 936       return true;
 937    }
 938 }
 939
 940 bool
 941 backend_instruction::can_do_saturate() const
 942 {
 943    switch (opcode) {
 944    case BRW_OPCODE_ADD:
 945    case BRW_OPCODE_ASR:
 946    case BRW_OPCODE_AVG:
 947    case BRW_OPCODE_DP2:
 948    case BRW_OPCODE_DP3:
 949    case BRW_OPCODE_DP4:
 950    case BRW_OPCODE_DPH:
 951    case BRW_OPCODE_F16TO32:
 952    case BRW_OPCODE_F32TO16:
 953    case BRW_OPCODE_LINE:
 954    case BRW_OPCODE_LRP:
 955    case BRW_OPCODE_MAC:
 956    case BRW_OPCODE_MAD:
 957    case BRW_OPCODE_MATH:
 958    case BRW_OPCODE_MOV:
 959    case BRW_OPCODE_MUL:
 960    case BRW_OPCODE_PLN:
 961    case BRW_OPCODE_RNDD:
 962    case BRW_OPCODE_RNDE:
 963    case BRW_OPCODE_RNDU:
 964    case BRW_OPCODE_RNDZ:
 965    case BRW_OPCODE_SEL:
 966    case BRW_OPCODE_SHL:
 967    case BRW_OPCODE_SHR:
 968    case FS_OPCODE_LINTERP:
 969    case SHADER_OPCODE_COS:
 970    case SHADER_OPCODE_EXP2:
 971    case SHADER_OPCODE_LOG2:
 972    case SHADER_OPCODE_POW:
 973    case SHADER_OPCODE_RCP:
 974    case SHADER_OPCODE_RSQ:
 975    case SHADER_OPCODE_SIN:
 976    case SHADER_OPCODE_SQRT:
 977       return true;
 978    default:
 979       return false;
 980    }
 981 }
 982
 983 bool
 984 backend_instruction::can_do_cmod() const
 985 {
 986    switch (opcode) {
 987    case BRW_OPCODE_ADD:
 988    case BRW_OPCODE_ADDC:
 989    case BRW_OPCODE_AND:
 990    case BRW_OPCODE_ASR:
 991    case BRW_OPCODE_AVG:
 992    case BRW_OPCODE_CMP:
 993    case BRW_OPCODE_CMPN:
 994    case BRW_OPCODE_DP2:
 995    case BRW_OPCODE_DP3:
 996    case BRW_OPCODE_DP4:
 997    case BRW_OPCODE_DPH:
 998    case BRW_OPCODE_F16TO32:
 999    case BRW_OPCODE_F32TO16:
1000    case BRW_OPCODE_FRC:
1001    case BRW_OPCODE_LINE:
1002    case BRW_OPCODE_LRP:
1003    case BRW_OPCODE_LZD:
1004    case BRW_OPCODE_MAC:
1005    case BRW_OPCODE_MACH:
1006    case BRW_OPCODE_MAD:
1007    case BRW_OPCODE_MOV:
1008    case BRW_OPCODE_MUL:
1009    case BRW_OPCODE_NOT:
1010    case BRW_OPCODE_OR:
1011    case BRW_OPCODE_PLN:
1012    case BRW_OPCODE_RNDD:
1013    case BRW_OPCODE_RNDE:
1014    case BRW_OPCODE_RNDU:
1015    case BRW_OPCODE_RNDZ:
1016    case BRW_OPCODE_SAD2:
1017    case BRW_OPCODE_SADA2:
1018    case BRW_OPCODE_SHL:
1019    case BRW_OPCODE_SHR:
1020    case BRW_OPCODE_SUBB:
1021    case BRW_OPCODE_XOR:
1022    case FS_OPCODE_CINTERP:
1023    case FS_OPCODE_LINTERP:
1024       return true;
1025    default:
1026       return false;
1027    }
1028 }
1029
1030 bool
1031 backend_instruction::reads_accumulator_implicitly() const
1032 {
1033    switch (opcode) {
1034    case BRW_OPCODE_MAC:
1035    case BRW_OPCODE_MACH:
1036    case BRW_OPCODE_SADA2:
1037       return true;
1038    default:
1039       return false;
1040    }
1041 }
1042
1043 bool
1044 backend_instruction::writes_accumulator_implicitly(const struct brw_device_info *devinfo) const
1045 {
1046    return writes_accumulator ||
1047           (devinfo->gen < 6 &&
1048            ((opcode >= BRW_OPCODE_ADD && opcode < BRW_OPCODE_NOP) ||
1049             (opcode >= FS_OPCODE_DDX_COARSE && opcode <= FS_OPCODE_LINTERP &&
1050              opcode != FS_OPCODE_CINTERP)));
1051 }
1052
1053 bool
1054 backend_instruction::has_side_effects() const
1055 {
1056    switch (opcode) {
1057    case SHADER_OPCODE_UNTYPED_ATOMIC:
1058    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1059    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
1060    case SHADER_OPCODE_TYPED_ATOMIC:
1061    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
1062    case SHADER_OPCODE_MEMORY_FENCE:
1063    case SHADER_OPCODE_URB_WRITE_SIMD8:
1064    case FS_OPCODE_FB_WRITE:
1065    case SHADER_OPCODE_BARRIER:
1066       return true;
1067    default:
1068       return false;
1069    }
1070 }
1071
1072 #ifndef NDEBUG
1073 static bool
1074 inst_is_in_block(const bblock_t *block, const backend_instruction *inst)
1075 {
1076    bool found = false;
1077    foreach_inst_in_block (backend_instruction, i, block) {
1078       if (inst == i) {
1079          found = true;
1080       }
1081    }
1082    return found;
1083 }
1084 #endif
1085
1086 static void
1087 adjust_later_block_ips(bblock_t *start_block, int ip_adjustment)
1088 {
1089    for (bblock_t *block_iter = start_block->next();
1090         !block_iter->link.is_tail_sentinel();
1091         block_iter = block_iter->next()) {
1092       block_iter->start_ip += ip_adjustment;
1093       block_iter->end_ip += ip_adjustment;
1094    }
1095 }
1096
1097 void
1098 backend_instruction::insert_after(bblock_t *block, backend_instruction *inst)
1099 {
1100    if (!this->is_head_sentinel())
1101       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1102
1103    block->end_ip++;
1104
1105    adjust_later_block_ips(block, 1);
1106
1107    exec_node::insert_after(inst);
1108 }
1109
1110 void
1111 backend_instruction::insert_before(bblock_t *block, backend_instruction *inst)
1112 {
1113    if (!this->is_tail_sentinel())
1114       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1115
1116    block->end_ip++;
1117
1118    adjust_later_block_ips(block, 1);
1119
1120    exec_node::insert_before(inst);
1121 }
1122
1123 void
1124 backend_instruction::insert_before(bblock_t *block, exec_list *list)
1125 {
1126    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1127
1128    unsigned num_inst = list->length();
1129
1130    block->end_ip += num_inst;
1131
1132    adjust_later_block_ips(block, num_inst);
1133
1134    exec_node::insert_before(list);
1135 }
1136
1137 void
1138 backend_instruction::remove(bblock_t *block)
1139 {
1140    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1141
1142    adjust_later_block_ips(block, -1);
1143
1144    if (block->start_ip == block->end_ip) {
1145       block->cfg->remove_block(block);
1146    } else {
1147       block->end_ip--;
1148    }
1149
1150    exec_node::remove();
1151 }
1152
1153 void
1154 backend_shader::dump_instructions()
1155 {
1156    dump_instructions(NULL);
1157 }
1158
1159 void
1160 backend_shader::dump_instructions(const char *name)
1161 {
1162    FILE *file = stderr;
1163    if (name && geteuid() != 0) {
1164       file = fopen(name, "w");
1165       if (!file)
1166          file = stderr;
1167    }
1168
1169    if (cfg) {
1170       int ip = 0;
1171       foreach_block_and_inst(block, backend_instruction, inst, cfg) {
1172          fprintf(file, "%4d: ", ip++);
1173          dump_instruction(inst, file);
1174       }
1175    } else {
1176       int ip = 0;
1177       foreach_in_list(backend_instruction, inst, &instructions) {
1178          fprintf(file, "%4d: ", ip++);
1179          dump_instruction(inst, file);
1180       }
1181    }
1182
1183    if (file != stderr) {
1184       fclose(file);
1185    }
1186 }
1187
1188 void
1189 backend_shader::calculate_cfg()
1190 {
1191    if (this->cfg)
1192       return;
1193    cfg = new(mem_ctx) cfg_t(&this->instructions);
1194 }
1195
1196 void
1197 backend_shader::invalidate_cfg()
1198 {
1199    ralloc_free(this->cfg);
1200    this->cfg = NULL;
1201 }
1202
1203 /**
1204  * Sets up the starting offsets for the groups of binding table entries
1205  * commong to all pipeline stages.
1206  *
1207  * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
1208  * unused but also make sure that addition of small offsets to them will
1209  * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
1210  */
1211 void
1212 backend_shader::assign_common_binding_table_offsets(uint32_t next_binding_table_offset)
1213 {
1214    int num_textures = _mesa_fls(prog->SamplersUsed);
1215
1216    stage_prog_data->binding_table.texture_start = next_binding_table_offset;
1217    next_binding_table_offset += num_textures;
1218
1219    if (shader) {
1220       stage_prog_data->binding_table.ubo_start = next_binding_table_offset;
1221       next_binding_table_offset += shader->base.NumUniformBlocks;
1222    } else {
1223       stage_prog_data->binding_table.ubo_start = 0xd0d0d0d0;
1224    }
1225
1226    if (INTEL_DEBUG & DEBUG_SHADER_TIME) {
1227       stage_prog_data->binding_table.shader_time_start = next_binding_table_offset;
1228       next_binding_table_offset++;
1229    } else {
1230       stage_prog_data->binding_table.shader_time_start = 0xd0d0d0d0;
1231    }
1232
1233    if (prog->UsesGather) {
1234       if (devinfo->gen >= 8) {
1235          stage_prog_data->binding_table.gather_texture_start =
1236             stage_prog_data->binding_table.texture_start;
1237       } else {
1238          stage_prog_data->binding_table.gather_texture_start = next_binding_table_offset;
1239          next_binding_table_offset += num_textures;
1240       }
1241    } else {
1242       stage_prog_data->binding_table.gather_texture_start = 0xd0d0d0d0;
1243    }
1244
1245    if (shader_prog && shader_prog->NumAtomicBuffers) {
1246       stage_prog_data->binding_table.abo_start = next_binding_table_offset;
1247       next_binding_table_offset += shader_prog->NumAtomicBuffers;
1248    } else {
1249       stage_prog_data->binding_table.abo_start = 0xd0d0d0d0;
1250    }
1251
1252    if (shader && shader->base.NumImages) {
1253       stage_prog_data->binding_table.image_start = next_binding_table_offset;
1254       next_binding_table_offset += shader->base.NumImages;
1255    } else {
1256       stage_prog_data->binding_table.image_start = 0xd0d0d0d0;
1257    }
1258
1259    /* This may or may not be used depending on how the compile goes. */
1260    stage_prog_data->binding_table.pull_constants_start = next_binding_table_offset;
1261    next_binding_table_offset++;
1262
1263    assert(next_binding_table_offset <= BRW_MAX_SURFACES);
1264
1265    /* prog_data->base.binding_table.size will be set by brw_mark_surface_used. */
1266 }