src/mesa/drivers/dri/i965/brw_shader.cpp

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "main/macros.h"
  25 #include "brw_context.h"
  26 #include "brw_vs.h"
  27 #include "brw_gs.h"
  28 #include "brw_fs.h"
  29 #include "brw_cfg.h"
  30 #include "brw_nir.h"
  31 #include "glsl/ir_optimization.h"
  32 #include "glsl/glsl_parser_extras.h"
  33 #include "main/shaderapi.h"
  34
  35 static void
  36 shader_debug_log_mesa(void *data, const char *fmt, ...)
  37 {
  38    struct brw_context *brw = (struct brw_context *)data;
  39    va_list args;
  40
  41    va_start(args, fmt);
  42    GLuint msg_id = 0;
  43    _mesa_gl_vdebug(&brw->ctx, &msg_id,
  44                    MESA_DEBUG_SOURCE_SHADER_COMPILER,
  45                    MESA_DEBUG_TYPE_OTHER,
  46                    MESA_DEBUG_SEVERITY_NOTIFICATION, fmt, args);
  47    va_end(args);
  48 }
  49
  50 static void
  51 shader_perf_log_mesa(void *data, const char *fmt, ...)
  52 {
  53    struct brw_context *brw = (struct brw_context *)data;
  54
  55    va_list args;
  56    va_start(args, fmt);
  57
  58    if (unlikely(INTEL_DEBUG & DEBUG_PERF)) {
  59       va_list args_copy;
  60       va_copy(args_copy, args);
  61       vfprintf(stderr, fmt, args_copy);
  62       va_end(args_copy);
  63    }
  64
  65    if (brw->perf_debug) {
  66       GLuint msg_id = 0;
  67       _mesa_gl_vdebug(&brw->ctx, &msg_id,
  68                       MESA_DEBUG_SOURCE_SHADER_COMPILER,
  69                       MESA_DEBUG_TYPE_PERFORMANCE,
  70                       MESA_DEBUG_SEVERITY_MEDIUM, fmt, args);
  71    }
  72    va_end(args);
  73 }
  74
  75 struct brw_compiler *
  76 brw_compiler_create(void *mem_ctx, const struct brw_device_info *devinfo)
  77 {
  78    struct brw_compiler *compiler = rzalloc(mem_ctx, struct brw_compiler);
  79
  80    compiler->devinfo = devinfo;
  81    compiler->shader_debug_log = shader_debug_log_mesa;
  82    compiler->shader_perf_log = shader_perf_log_mesa;
  83
  84    brw_fs_alloc_reg_sets(compiler);
  85    brw_vec4_alloc_reg_set(compiler);
  86
  87    if (devinfo->gen >= 8 && !(INTEL_DEBUG & DEBUG_VEC4VS))
  88       compiler->scalar_vs = true;
  89
  90    nir_shader_compiler_options *nir_options =
  91       rzalloc(compiler, nir_shader_compiler_options);
  92    nir_options->native_integers = true;
  93    /* In order to help allow for better CSE at the NIR level we tell NIR
  94     * to split all ffma instructions during opt_algebraic and we then
  95     * re-combine them as a later step.
  96     */
  97    nir_options->lower_ffma = true;
  98    nir_options->lower_sub = true;
  99
 100    /* We want the GLSL compiler to emit code that uses condition codes */
 101    for (int i = 0; i < MESA_SHADER_STAGES; i++) {
 102       compiler->glsl_compiler_options[i].MaxUnrollIterations = 32;
 103       compiler->glsl_compiler_options[i].MaxIfDepth =
 104          devinfo->gen < 6 ? 16 : UINT_MAX;
 105
 106       compiler->glsl_compiler_options[i].EmitCondCodes = true;
 107       compiler->glsl_compiler_options[i].EmitNoNoise = true;
 108       compiler->glsl_compiler_options[i].EmitNoMainReturn = true;
 109       compiler->glsl_compiler_options[i].EmitNoIndirectInput = true;
 110       compiler->glsl_compiler_options[i].EmitNoIndirectOutput =
 111          (i == MESA_SHADER_FRAGMENT);
 112       compiler->glsl_compiler_options[i].EmitNoIndirectTemp =
 113          (i == MESA_SHADER_FRAGMENT);
 114       compiler->glsl_compiler_options[i].EmitNoIndirectUniform = false;
 115       compiler->glsl_compiler_options[i].LowerClipDistance = true;
 116
 117       /* !ARB_gpu_shader5 */
 118       if (devinfo->gen < 7)
 119          compiler->glsl_compiler_options[i].EmitNoIndirectSampler = true;
 120    }
 121
 122    compiler->glsl_compiler_options[MESA_SHADER_VERTEX].OptimizeForAOS = true;
 123    compiler->glsl_compiler_options[MESA_SHADER_GEOMETRY].OptimizeForAOS = true;
 124
 125    if (compiler->scalar_vs) {
 126       /* If we're using the scalar backend for vertex shaders, we need to
 127        * configure these accordingly.
 128        */
 129       compiler->glsl_compiler_options[MESA_SHADER_VERTEX].EmitNoIndirectOutput = true;
 130       compiler->glsl_compiler_options[MESA_SHADER_VERTEX].EmitNoIndirectTemp = true;
 131       compiler->glsl_compiler_options[MESA_SHADER_VERTEX].OptimizeForAOS = false;
 132
 133       compiler->glsl_compiler_options[MESA_SHADER_VERTEX].NirOptions = nir_options;
 134    }
 135
 136    compiler->glsl_compiler_options[MESA_SHADER_FRAGMENT].NirOptions = nir_options;
 137    compiler->glsl_compiler_options[MESA_SHADER_COMPUTE].NirOptions = nir_options;
 138
 139    return compiler;
 140 }
 141
 142 struct gl_shader *
 143 brw_new_shader(struct gl_context *ctx, GLuint name, GLuint type)
 144 {
 145    struct brw_shader *shader;
 146
 147    shader = rzalloc(NULL, struct brw_shader);
 148    if (shader) {
 149       shader->base.Type = type;
 150       shader->base.Stage = _mesa_shader_enum_to_shader_stage(type);
 151       shader->base.Name = name;
 152       _mesa_init_shader(ctx, &shader->base);
 153    }
 154
 155    return &shader->base;
 156 }
 157
 158 /**
 159  * Performs a compile of the shader stages even when we don't know
 160  * what non-orthogonal state will be set, in the hope that it reflects
 161  * the eventual NOS used, and thus allows us to produce link failures.
 162  */
 163 static bool
 164 brw_shader_precompile(struct gl_context *ctx,
 165                       struct gl_shader_program *sh_prog)
 166 {
 167    struct gl_shader *vs = sh_prog->_LinkedShaders[MESA_SHADER_VERTEX];
 168    struct gl_shader *gs = sh_prog->_LinkedShaders[MESA_SHADER_GEOMETRY];
 169    struct gl_shader *fs = sh_prog->_LinkedShaders[MESA_SHADER_FRAGMENT];
 170    struct gl_shader *cs = sh_prog->_LinkedShaders[MESA_SHADER_COMPUTE];
 171
 172    if (fs && !brw_fs_precompile(ctx, sh_prog, fs->Program))
 173       return false;
 174
 175    if (gs && !brw_gs_precompile(ctx, sh_prog, gs->Program))
 176       return false;
 177
 178    if (vs && !brw_vs_precompile(ctx, sh_prog, vs->Program))
 179       return false;
 180
 181    if (cs && !brw_cs_precompile(ctx, sh_prog, cs->Program))
 182       return false;
 183
 184    return true;
 185 }
 186
 187 static inline bool
 188 is_scalar_shader_stage(struct brw_context *brw, int stage)
 189 {
 190    switch (stage) {
 191    case MESA_SHADER_FRAGMENT:
 192       return true;
 193    case MESA_SHADER_VERTEX:
 194       return brw->intelScreen->compiler->scalar_vs;
 195    default:
 196       return false;
 197    }
 198 }
 199
 200 static void
 201 brw_lower_packing_builtins(struct brw_context *brw,
 202                            gl_shader_stage shader_type,
 203                            exec_list *ir)
 204 {
 205    int ops = LOWER_PACK_SNORM_2x16
 206            | LOWER_UNPACK_SNORM_2x16
 207            | LOWER_PACK_UNORM_2x16
 208            | LOWER_UNPACK_UNORM_2x16;
 209
 210    if (is_scalar_shader_stage(brw, shader_type)) {
 211       ops |= LOWER_UNPACK_UNORM_4x8
 212            | LOWER_UNPACK_SNORM_4x8
 213            | LOWER_PACK_UNORM_4x8
 214            | LOWER_PACK_SNORM_4x8;
 215    }
 216
 217    if (brw->gen >= 7) {
 218       /* Gen7 introduced the f32to16 and f16to32 instructions, which can be
 219        * used to execute packHalf2x16 and unpackHalf2x16. For AOS code, no
 220        * lowering is needed. For SOA code, the Half2x16 ops must be
 221        * scalarized.
 222        */
 223       if (is_scalar_shader_stage(brw, shader_type)) {
 224          ops |= LOWER_PACK_HALF_2x16_TO_SPLIT
 225              |  LOWER_UNPACK_HALF_2x16_TO_SPLIT;
 226       }
 227    } else {
 228       ops |= LOWER_PACK_HALF_2x16
 229           |  LOWER_UNPACK_HALF_2x16;
 230    }
 231
 232    lower_packing_builtins(ir, ops);
 233 }
 234
 235 static void
 236 process_glsl_ir(gl_shader_stage stage,
 237                 struct brw_context *brw,
 238                 struct gl_shader_program *shader_prog,
 239                 struct gl_shader *shader)
 240 {
 241    struct gl_context *ctx = &brw->ctx;
 242    const struct gl_shader_compiler_options *options =
 243       &ctx->Const.ShaderCompilerOptions[shader->Stage];
 244
 245    /* Temporary memory context for any new IR. */
 246    void *mem_ctx = ralloc_context(NULL);
 247
 248    ralloc_adopt(mem_ctx, shader->ir);
 249
 250    /* lower_packing_builtins() inserts arithmetic instructions, so it
 251     * must precede lower_instructions().
 252     */
 253    brw_lower_packing_builtins(brw, shader->Stage, shader->ir);
 254    do_mat_op_to_vec(shader->ir);
 255    const int bitfield_insert = brw->gen >= 7 ? BITFIELD_INSERT_TO_BFM_BFI : 0;
 256    lower_instructions(shader->ir,
 257                       MOD_TO_FLOOR |
 258                       DIV_TO_MUL_RCP |
 259                       SUB_TO_ADD_NEG |
 260                       EXP_TO_EXP2 |
 261                       LOG_TO_LOG2 |
 262                       bitfield_insert |
 263                       LDEXP_TO_ARITH |
 264                       CARRY_TO_ARITH |
 265                       BORROW_TO_ARITH);
 266
 267    /* Pre-gen6 HW can only nest if-statements 16 deep.  Beyond this,
 268     * if-statements need to be flattened.
 269     */
 270    if (brw->gen < 6)
 271       lower_if_to_cond_assign(shader->ir, 16);
 272
 273    do_lower_texture_projection(shader->ir);
 274    brw_lower_texture_gradients(brw, shader->ir);
 275    do_vec_index_to_cond_assign(shader->ir);
 276    lower_vector_insert(shader->ir, true);
 277    if (options->NirOptions == NULL)
 278       brw_do_cubemap_normalize(shader->ir);
 279    lower_offset_arrays(shader->ir);
 280    brw_do_lower_unnormalized_offset(shader->ir);
 281    lower_noise(shader->ir);
 282    lower_quadop_vector(shader->ir, false);
 283
 284    bool lowered_variable_indexing =
 285       lower_variable_index_to_cond_assign((gl_shader_stage)stage,
 286                                           shader->ir,
 287                                           options->EmitNoIndirectInput,
 288                                           options->EmitNoIndirectOutput,
 289                                           options->EmitNoIndirectTemp,
 290                                           options->EmitNoIndirectUniform);
 291
 292    if (unlikely(brw->perf_debug && lowered_variable_indexing)) {
 293       perf_debug("Unsupported form of variable indexing in %s; falling "
 294                  "back to very inefficient code generation\n",
 295                  _mesa_shader_stage_to_abbrev(shader->Stage));
 296    }
 297
 298    lower_ubo_reference(shader, shader->ir);
 299
 300    bool progress;
 301    do {
 302       progress = false;
 303
 304       if (is_scalar_shader_stage(brw, shader->Stage)) {
 305          brw_do_channel_expressions(shader->ir);
 306          brw_do_vector_splitting(shader->ir);
 307       }
 308
 309       progress = do_lower_jumps(shader->ir, true, true,
 310                                 true, /* main return */
 311                                 false, /* continue */
 312                                 false /* loops */
 313                                 ) || progress;
 314
 315       progress = do_common_optimization(shader->ir, true, true,
 316                                         options, ctx->Const.NativeIntegers) || progress;
 317    } while (progress);
 318
 319    if (options->NirOptions != NULL)
 320       lower_output_reads(stage, shader->ir);
 321
 322    validate_ir_tree(shader->ir);
 323
 324    /* Now that we've finished altering the linked IR, reparent any live IR back
 325     * to the permanent memory context, and free the temporary one (discarding any
 326     * junk we optimized away).
 327     */
 328    reparent_ir(shader->ir, shader->ir);
 329    ralloc_free(mem_ctx);
 330
 331    if (ctx->_Shader->Flags & GLSL_DUMP) {
 332       fprintf(stderr, "\n");
 333       fprintf(stderr, "GLSL IR for linked %s program %d:\n",
 334               _mesa_shader_stage_to_string(shader->Stage),
 335               shader_prog->Name);
 336       _mesa_print_ir(stderr, shader->ir, NULL);
 337       fprintf(stderr, "\n");
 338    }
 339 }
 340
 341 GLboolean
 342 brw_link_shader(struct gl_context *ctx, struct gl_shader_program *shProg)
 343 {
 344    struct brw_context *brw = brw_context(ctx);
 345    unsigned int stage;
 346
 347    for (stage = 0; stage < ARRAY_SIZE(shProg->_LinkedShaders); stage++) {
 348       struct gl_shader *shader = shProg->_LinkedShaders[stage];
 349       const struct gl_shader_compiler_options *options =
 350          &ctx->Const.ShaderCompilerOptions[stage];
 351
 352       if (!shader)
 353          continue;
 354
 355       struct gl_program *prog =
 356          ctx->Driver.NewProgram(ctx, _mesa_shader_stage_to_program(stage),
 357                                 shader->Name);
 358       if (!prog)
 359         return false;
 360       prog->Parameters = _mesa_new_parameter_list();
 361
 362       _mesa_copy_linked_program_data((gl_shader_stage) stage, shProg, prog);
 363
 364       process_glsl_ir((gl_shader_stage) stage, brw, shProg, shader);
 365
 366       /* Make a pass over the IR to add state references for any built-in
 367        * uniforms that are used.  This has to be done now (during linking).
 368        * Code generation doesn't happen until the first time this shader is
 369        * used for rendering.  Waiting until then to generate the parameters is
 370        * too late.  At that point, the values for the built-in uniforms won't
 371        * get sent to the shader.
 372        */
 373       foreach_in_list(ir_instruction, node, shader->ir) {
 374          ir_variable *var = node->as_variable();
 375
 376          if ((var == NULL) || (var->data.mode != ir_var_uniform)
 377              || (strncmp(var->name, "gl_", 3) != 0))
 378             continue;
 379
 380          const ir_state_slot *const slots = var->get_state_slots();
 381          assert(slots != NULL);
 382
 383          for (unsigned int i = 0; i < var->get_num_state_slots(); i++) {
 384             _mesa_add_state_reference(prog->Parameters,
 385                                       (gl_state_index *) slots[i].tokens);
 386          }
 387       }
 388
 389       do_set_program_inouts(shader->ir, prog, shader->Stage);
 390
 391       prog->SamplersUsed = shader->active_samplers;
 392       prog->ShadowSamplers = shader->shadow_samplers;
 393       _mesa_update_shader_textures_used(shProg, prog);
 394
 395       _mesa_reference_program(ctx, &shader->Program, prog);
 396
 397       brw_add_texrect_params(prog);
 398
 399       if (options->NirOptions)
 400          prog->nir = brw_create_nir(brw, shProg, prog, (gl_shader_stage) stage);
 401
 402       _mesa_reference_program(ctx, &prog, NULL);
 403    }
 404
 405    if ((ctx->_Shader->Flags & GLSL_DUMP) && shProg->Name != 0) {
 406       for (unsigned i = 0; i < shProg->NumShaders; i++) {
 407          const struct gl_shader *sh = shProg->Shaders[i];
 408          if (!sh)
 409             continue;
 410
 411          fprintf(stderr, "GLSL %s shader %d source for linked program %d:\n",
 412                  _mesa_shader_stage_to_string(sh->Stage),
 413                  i, shProg->Name);
 414          fprintf(stderr, "%s", sh->Source);
 415          fprintf(stderr, "\n");
 416       }
 417    }
 418
 419    if (brw->precompile && !brw_shader_precompile(ctx, shProg))
 420       return false;
 421
 422    return true;
 423 }
 424
 425
 426 enum brw_reg_type
 427 brw_type_for_base_type(const struct glsl_type *type)
 428 {
 429    switch (type->base_type) {
 430    case GLSL_TYPE_FLOAT:
 431       return BRW_REGISTER_TYPE_F;
 432    case GLSL_TYPE_INT:
 433    case GLSL_TYPE_BOOL:
 434    case GLSL_TYPE_SUBROUTINE:
 435       return BRW_REGISTER_TYPE_D;
 436    case GLSL_TYPE_UINT:
 437       return BRW_REGISTER_TYPE_UD;
 438    case GLSL_TYPE_ARRAY:
 439       return brw_type_for_base_type(type->fields.array);
 440    case GLSL_TYPE_STRUCT:
 441    case GLSL_TYPE_SAMPLER:
 442    case GLSL_TYPE_ATOMIC_UINT:
 443       /* These should be overridden with the type of the member when
 444        * dereferenced into.  BRW_REGISTER_TYPE_UD seems like a likely
 445        * way to trip up if we don't.
 446        */
 447       return BRW_REGISTER_TYPE_UD;
 448    case GLSL_TYPE_IMAGE:
 449       return BRW_REGISTER_TYPE_UD;
 450    case GLSL_TYPE_VOID:
 451    case GLSL_TYPE_ERROR:
 452    case GLSL_TYPE_INTERFACE:
 453    case GLSL_TYPE_DOUBLE:
 454       unreachable("not reached");
 455    }
 456
 457    return BRW_REGISTER_TYPE_F;
 458 }
 459
 460 enum brw_conditional_mod
 461 brw_conditional_for_comparison(unsigned int op)
 462 {
 463    switch (op) {
 464    case ir_binop_less:
 465       return BRW_CONDITIONAL_L;
 466    case ir_binop_greater:
 467       return BRW_CONDITIONAL_G;
 468    case ir_binop_lequal:
 469       return BRW_CONDITIONAL_LE;
 470    case ir_binop_gequal:
 471       return BRW_CONDITIONAL_GE;
 472    case ir_binop_equal:
 473    case ir_binop_all_equal: /* same as equal for scalars */
 474       return BRW_CONDITIONAL_Z;
 475    case ir_binop_nequal:
 476    case ir_binop_any_nequal: /* same as nequal for scalars */
 477       return BRW_CONDITIONAL_NZ;
 478    default:
 479       unreachable("not reached: bad operation for comparison");
 480    }
 481 }
 482
 483 uint32_t
 484 brw_math_function(enum opcode op)
 485 {
 486    switch (op) {
 487    case SHADER_OPCODE_RCP:
 488       return BRW_MATH_FUNCTION_INV;
 489    case SHADER_OPCODE_RSQ:
 490       return BRW_MATH_FUNCTION_RSQ;
 491    case SHADER_OPCODE_SQRT:
 492       return BRW_MATH_FUNCTION_SQRT;
 493    case SHADER_OPCODE_EXP2:
 494       return BRW_MATH_FUNCTION_EXP;
 495    case SHADER_OPCODE_LOG2:
 496       return BRW_MATH_FUNCTION_LOG;
 497    case SHADER_OPCODE_POW:
 498       return BRW_MATH_FUNCTION_POW;
 499    case SHADER_OPCODE_SIN:
 500       return BRW_MATH_FUNCTION_SIN;
 501    case SHADER_OPCODE_COS:
 502       return BRW_MATH_FUNCTION_COS;
 503    case SHADER_OPCODE_INT_QUOTIENT:
 504       return BRW_MATH_FUNCTION_INT_DIV_QUOTIENT;
 505    case SHADER_OPCODE_INT_REMAINDER:
 506       return BRW_MATH_FUNCTION_INT_DIV_REMAINDER;
 507    default:
 508       unreachable("not reached: unknown math function");
 509    }
 510 }
 511
 512 uint32_t
 513 brw_texture_offset(int *offsets, unsigned num_components)
 514 {
 515    if (!offsets) return 0;  /* nonconstant offset; caller will handle it. */
 516
 517    /* Combine all three offsets into a single unsigned dword:
 518     *
 519     *    bits 11:8 - U Offset (X component)
 520     *    bits  7:4 - V Offset (Y component)
 521     *    bits  3:0 - R Offset (Z component)
 522     */
 523    unsigned offset_bits = 0;
 524    for (unsigned i = 0; i < num_components; i++) {
 525       const unsigned shift = 4 * (2 - i);
 526       offset_bits |= (offsets[i] << shift) & (0xF << shift);
 527    }
 528    return offset_bits;
 529 }
 530
 531 const char *
 532 brw_instruction_name(enum opcode op)
 533 {
 534    switch (op) {
 535    case BRW_OPCODE_MOV ... BRW_OPCODE_NOP:
 536       assert(opcode_descs[op].name);
 537       return opcode_descs[op].name;
 538    case FS_OPCODE_FB_WRITE:
 539       return "fb_write";
 540    case FS_OPCODE_FB_WRITE_LOGICAL:
 541       return "fb_write_logical";
 542    case FS_OPCODE_BLORP_FB_WRITE:
 543       return "blorp_fb_write";
 544    case FS_OPCODE_REP_FB_WRITE:
 545       return "rep_fb_write";
 546
 547    case SHADER_OPCODE_RCP:
 548       return "rcp";
 549    case SHADER_OPCODE_RSQ:
 550       return "rsq";
 551    case SHADER_OPCODE_SQRT:
 552       return "sqrt";
 553    case SHADER_OPCODE_EXP2:
 554       return "exp2";
 555    case SHADER_OPCODE_LOG2:
 556       return "log2";
 557    case SHADER_OPCODE_POW:
 558       return "pow";
 559    case SHADER_OPCODE_INT_QUOTIENT:
 560       return "int_quot";
 561    case SHADER_OPCODE_INT_REMAINDER:
 562       return "int_rem";
 563    case SHADER_OPCODE_SIN:
 564       return "sin";
 565    case SHADER_OPCODE_COS:
 566       return "cos";
 567
 568    case SHADER_OPCODE_TEX:
 569       return "tex";
 570    case SHADER_OPCODE_TXD:
 571       return "txd";
 572    case SHADER_OPCODE_TXF:
 573       return "txf";
 574    case SHADER_OPCODE_TXL:
 575       return "txl";
 576    case SHADER_OPCODE_TXS:
 577       return "txs";
 578    case FS_OPCODE_TXB:
 579       return "txb";
 580    case SHADER_OPCODE_TXF_CMS:
 581       return "txf_cms";
 582    case SHADER_OPCODE_TXF_UMS:
 583       return "txf_ums";
 584    case SHADER_OPCODE_TXF_MCS:
 585       return "txf_mcs";
 586    case SHADER_OPCODE_LOD:
 587       return "lod";
 588    case SHADER_OPCODE_TG4:
 589       return "tg4";
 590    case SHADER_OPCODE_TG4_OFFSET:
 591       return "tg4_offset";
 592    case SHADER_OPCODE_SHADER_TIME_ADD:
 593       return "shader_time_add";
 594
 595    case SHADER_OPCODE_UNTYPED_ATOMIC:
 596       return "untyped_atomic";
 597    case SHADER_OPCODE_UNTYPED_SURFACE_READ:
 598       return "untyped_surface_read";
 599    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
 600       return "untyped_surface_write";
 601    case SHADER_OPCODE_TYPED_ATOMIC:
 602       return "typed_atomic";
 603    case SHADER_OPCODE_TYPED_SURFACE_READ:
 604       return "typed_surface_read";
 605    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
 606       return "typed_surface_write";
 607    case SHADER_OPCODE_MEMORY_FENCE:
 608       return "memory_fence";
 609
 610    case SHADER_OPCODE_LOAD_PAYLOAD:
 611       return "load_payload";
 612
 613    case SHADER_OPCODE_GEN4_SCRATCH_READ:
 614       return "gen4_scratch_read";
 615    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
 616       return "gen4_scratch_write";
 617    case SHADER_OPCODE_GEN7_SCRATCH_READ:
 618       return "gen7_scratch_read";
 619    case SHADER_OPCODE_URB_WRITE_SIMD8:
 620       return "gen8_urb_write_simd8";
 621
 622    case SHADER_OPCODE_FIND_LIVE_CHANNEL:
 623       return "find_live_channel";
 624    case SHADER_OPCODE_BROADCAST:
 625       return "broadcast";
 626
 627    case VEC4_OPCODE_MOV_BYTES:
 628       return "mov_bytes";
 629    case VEC4_OPCODE_PACK_BYTES:
 630       return "pack_bytes";
 631    case VEC4_OPCODE_UNPACK_UNIFORM:
 632       return "unpack_uniform";
 633
 634    case FS_OPCODE_DDX_COARSE:
 635       return "ddx_coarse";
 636    case FS_OPCODE_DDX_FINE:
 637       return "ddx_fine";
 638    case FS_OPCODE_DDY_COARSE:
 639       return "ddy_coarse";
 640    case FS_OPCODE_DDY_FINE:
 641       return "ddy_fine";
 642
 643    case FS_OPCODE_CINTERP:
 644       return "cinterp";
 645    case FS_OPCODE_LINTERP:
 646       return "linterp";
 647
 648    case FS_OPCODE_PIXEL_X:
 649       return "pixel_x";
 650    case FS_OPCODE_PIXEL_Y:
 651       return "pixel_y";
 652
 653    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
 654       return "uniform_pull_const";
 655    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
 656       return "uniform_pull_const_gen7";
 657    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
 658       return "varying_pull_const";
 659    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
 660       return "varying_pull_const_gen7";
 661
 662    case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
 663       return "mov_dispatch_to_flags";
 664    case FS_OPCODE_DISCARD_JUMP:
 665       return "discard_jump";
 666
 667    case FS_OPCODE_SET_SAMPLE_ID:
 668       return "set_sample_id";
 669    case FS_OPCODE_SET_SIMD4X2_OFFSET:
 670       return "set_simd4x2_offset";
 671
 672    case FS_OPCODE_PACK_HALF_2x16_SPLIT:
 673       return "pack_half_2x16_split";
 674    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
 675       return "unpack_half_2x16_split_x";
 676    case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
 677       return "unpack_half_2x16_split_y";
 678
 679    case FS_OPCODE_PLACEHOLDER_HALT:
 680       return "placeholder_halt";
 681
 682    case FS_OPCODE_INTERPOLATE_AT_CENTROID:
 683       return "interp_centroid";
 684    case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
 685       return "interp_sample";
 686    case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
 687       return "interp_shared_offset";
 688    case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
 689       return "interp_per_slot_offset";
 690
 691    case VS_OPCODE_URB_WRITE:
 692       return "vs_urb_write";
 693    case VS_OPCODE_PULL_CONSTANT_LOAD:
 694       return "pull_constant_load";
 695    case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
 696       return "pull_constant_load_gen7";
 697
 698    case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
 699       return "set_simd4x2_header_gen9";
 700
 701    case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
 702       return "unpack_flags_simd4x2";
 703
 704    case GS_OPCODE_URB_WRITE:
 705       return "gs_urb_write";
 706    case GS_OPCODE_URB_WRITE_ALLOCATE:
 707       return "gs_urb_write_allocate";
 708    case GS_OPCODE_THREAD_END:
 709       return "gs_thread_end";
 710    case GS_OPCODE_SET_WRITE_OFFSET:
 711       return "set_write_offset";
 712    case GS_OPCODE_SET_VERTEX_COUNT:
 713       return "set_vertex_count";
 714    case GS_OPCODE_SET_DWORD_2:
 715       return "set_dword_2";
 716    case GS_OPCODE_PREPARE_CHANNEL_MASKS:
 717       return "prepare_channel_masks";
 718    case GS_OPCODE_SET_CHANNEL_MASKS:
 719       return "set_channel_masks";
 720    case GS_OPCODE_GET_INSTANCE_ID:
 721       return "get_instance_id";
 722    case GS_OPCODE_FF_SYNC:
 723       return "ff_sync";
 724    case GS_OPCODE_SET_PRIMITIVE_ID:
 725       return "set_primitive_id";
 726    case GS_OPCODE_SVB_WRITE:
 727       return "gs_svb_write";
 728    case GS_OPCODE_SVB_SET_DST_INDEX:
 729       return "gs_svb_set_dst_index";
 730    case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
 731       return "gs_ff_sync_set_primitives";
 732    case CS_OPCODE_CS_TERMINATE:
 733       return "cs_terminate";
 734    case SHADER_OPCODE_BARRIER:
 735       return "barrier";
 736    }
 737
 738    unreachable("not reached");
 739 }
 740
 741 bool
 742 brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 743 {
 744    union {
 745       unsigned ud;
 746       int d;
 747       float f;
 748    } imm = { reg->dw1.ud }, sat_imm = { 0 };
 749
 750    switch (type) {
 751    case BRW_REGISTER_TYPE_UD:
 752    case BRW_REGISTER_TYPE_D:
 753    case BRW_REGISTER_TYPE_UQ:
 754    case BRW_REGISTER_TYPE_Q:
 755       /* Nothing to do. */
 756       return false;
 757    case BRW_REGISTER_TYPE_UW:
 758       sat_imm.ud = CLAMP(imm.ud, 0, USHRT_MAX);
 759       break;
 760    case BRW_REGISTER_TYPE_W:
 761       sat_imm.d = CLAMP(imm.d, SHRT_MIN, SHRT_MAX);
 762       break;
 763    case BRW_REGISTER_TYPE_F:
 764       sat_imm.f = CLAMP(imm.f, 0.0f, 1.0f);
 765       break;
 766    case BRW_REGISTER_TYPE_UB:
 767    case BRW_REGISTER_TYPE_B:
 768       unreachable("no UB/B immediates");
 769    case BRW_REGISTER_TYPE_V:
 770    case BRW_REGISTER_TYPE_UV:
 771    case BRW_REGISTER_TYPE_VF:
 772       unreachable("unimplemented: saturate vector immediate");
 773    case BRW_REGISTER_TYPE_DF:
 774    case BRW_REGISTER_TYPE_HF:
 775       unreachable("unimplemented: saturate DF/HF immediate");
 776    }
 777
 778    if (imm.ud != sat_imm.ud) {
 779       reg->dw1.ud = sat_imm.ud;
 780       return true;
 781    }
 782    return false;
 783 }
 784
 785 bool
 786 brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg)
 787 {
 788    switch (type) {
 789    case BRW_REGISTER_TYPE_D:
 790    case BRW_REGISTER_TYPE_UD:
 791       reg->dw1.d = -reg->dw1.d;
 792       return true;
 793    case BRW_REGISTER_TYPE_W:
 794    case BRW_REGISTER_TYPE_UW:
 795       reg->dw1.d = -(int16_t)reg->dw1.ud;
 796       return true;
 797    case BRW_REGISTER_TYPE_F:
 798       reg->dw1.f = -reg->dw1.f;
 799       return true;
 800    case BRW_REGISTER_TYPE_VF:
 801       reg->dw1.ud ^= 0x80808080;
 802       return true;
 803    case BRW_REGISTER_TYPE_UB:
 804    case BRW_REGISTER_TYPE_B:
 805       unreachable("no UB/B immediates");
 806    case BRW_REGISTER_TYPE_UV:
 807    case BRW_REGISTER_TYPE_V:
 808       assert(!"unimplemented: negate UV/V immediate");
 809    case BRW_REGISTER_TYPE_UQ:
 810    case BRW_REGISTER_TYPE_Q:
 811       assert(!"unimplemented: negate UQ/Q immediate");
 812    case BRW_REGISTER_TYPE_DF:
 813    case BRW_REGISTER_TYPE_HF:
 814       assert(!"unimplemented: negate DF/HF immediate");
 815    }
 816
 817    return false;
 818 }
 819
 820 bool
 821 brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg)
 822 {
 823    switch (type) {
 824    case BRW_REGISTER_TYPE_D:
 825       reg->dw1.d = abs(reg->dw1.d);
 826       return true;
 827    case BRW_REGISTER_TYPE_W:
 828       reg->dw1.d = abs((int16_t)reg->dw1.ud);
 829       return true;
 830    case BRW_REGISTER_TYPE_F:
 831       reg->dw1.f = fabsf(reg->dw1.f);
 832       return true;
 833    case BRW_REGISTER_TYPE_VF:
 834       reg->dw1.ud &= ~0x80808080;
 835       return true;
 836    case BRW_REGISTER_TYPE_UB:
 837    case BRW_REGISTER_TYPE_B:
 838       unreachable("no UB/B immediates");
 839    case BRW_REGISTER_TYPE_UQ:
 840    case BRW_REGISTER_TYPE_UD:
 841    case BRW_REGISTER_TYPE_UW:
 842    case BRW_REGISTER_TYPE_UV:
 843       /* Presumably the absolute value modifier on an unsigned source is a
 844        * nop, but it would be nice to confirm.
 845        */
 846       assert(!"unimplemented: abs unsigned immediate");
 847    case BRW_REGISTER_TYPE_V:
 848       assert(!"unimplemented: abs V immediate");
 849    case BRW_REGISTER_TYPE_Q:
 850       assert(!"unimplemented: abs Q immediate");
 851    case BRW_REGISTER_TYPE_DF:
 852    case BRW_REGISTER_TYPE_HF:
 853       assert(!"unimplemented: abs DF/HF immediate");
 854    }
 855
 856    return false;
 857 }
 858
 859 backend_shader::backend_shader(const struct brw_compiler *compiler,
 860                                void *log_data,
 861                                void *mem_ctx,
 862                                struct gl_shader_program *shader_prog,
 863                                struct gl_program *prog,
 864                                struct brw_stage_prog_data *stage_prog_data,
 865                                gl_shader_stage stage)
 866    : compiler(compiler),
 867      log_data(log_data),
 868      devinfo(compiler->devinfo),
 869      shader(shader_prog ?
 870         (struct brw_shader *)shader_prog->_LinkedShaders[stage] : NULL),
 871      shader_prog(shader_prog),
 872      prog(prog),
 873      stage_prog_data(stage_prog_data),
 874      mem_ctx(mem_ctx),
 875      cfg(NULL),
 876      stage(stage)
 877 {
 878    debug_enabled = INTEL_DEBUG & intel_debug_flag_for_shader_stage(stage);
 879    stage_name = _mesa_shader_stage_to_string(stage);
 880    stage_abbrev = _mesa_shader_stage_to_abbrev(stage);
 881 }
 882
 883 bool
 884 backend_reg::is_zero() const
 885 {
 886    if (file != IMM)
 887       return false;
 888
 889    return fixed_hw_reg.dw1.d == 0;
 890 }
 891
 892 bool
 893 backend_reg::is_one() const
 894 {
 895    if (file != IMM)
 896       return false;
 897
 898    return type == BRW_REGISTER_TYPE_F
 899           ? fixed_hw_reg.dw1.f == 1.0
 900           : fixed_hw_reg.dw1.d == 1;
 901 }
 902
 903 bool
 904 backend_reg::is_negative_one() const
 905 {
 906    if (file != IMM)
 907       return false;
 908
 909    switch (type) {
 910    case BRW_REGISTER_TYPE_F:
 911       return fixed_hw_reg.dw1.f == -1.0;
 912    case BRW_REGISTER_TYPE_D:
 913       return fixed_hw_reg.dw1.d == -1;
 914    default:
 915       return false;
 916    }
 917 }
 918
 919 bool
 920 backend_reg::is_null() const
 921 {
 922    return file == HW_REG &&
 923           fixed_hw_reg.file == BRW_ARCHITECTURE_REGISTER_FILE &&
 924           fixed_hw_reg.nr == BRW_ARF_NULL;
 925 }
 926
 927
 928 bool
 929 backend_reg::is_accumulator() const
 930 {
 931    return file == HW_REG &&
 932           fixed_hw_reg.file == BRW_ARCHITECTURE_REGISTER_FILE &&
 933           fixed_hw_reg.nr == BRW_ARF_ACCUMULATOR;
 934 }
 935
 936 bool
 937 backend_reg::in_range(const backend_reg &r, unsigned n) const
 938 {
 939    return (file == r.file &&
 940            reg == r.reg &&
 941            reg_offset >= r.reg_offset &&
 942            reg_offset < r.reg_offset + n);
 943 }
 944
 945 bool
 946 backend_instruction::is_commutative() const
 947 {
 948    switch (opcode) {
 949    case BRW_OPCODE_AND:
 950    case BRW_OPCODE_OR:
 951    case BRW_OPCODE_XOR:
 952    case BRW_OPCODE_ADD:
 953    case BRW_OPCODE_MUL:
 954       return true;
 955    case BRW_OPCODE_SEL:
 956       /* MIN and MAX are commutative. */
 957       if (conditional_mod == BRW_CONDITIONAL_GE ||
 958           conditional_mod == BRW_CONDITIONAL_L) {
 959          return true;
 960       }
 961       /* fallthrough */
 962    default:
 963       return false;
 964    }
 965 }
 966
 967 bool
 968 backend_instruction::is_3src() const
 969 {
 970    return opcode < ARRAY_SIZE(opcode_descs) && opcode_descs[opcode].nsrc == 3;
 971 }
 972
 973 bool
 974 backend_instruction::is_tex() const
 975 {
 976    return (opcode == SHADER_OPCODE_TEX ||
 977            opcode == FS_OPCODE_TXB ||
 978            opcode == SHADER_OPCODE_TXD ||
 979            opcode == SHADER_OPCODE_TXF ||
 980            opcode == SHADER_OPCODE_TXF_CMS ||
 981            opcode == SHADER_OPCODE_TXF_UMS ||
 982            opcode == SHADER_OPCODE_TXF_MCS ||
 983            opcode == SHADER_OPCODE_TXL ||
 984            opcode == SHADER_OPCODE_TXS ||
 985            opcode == SHADER_OPCODE_LOD ||
 986            opcode == SHADER_OPCODE_TG4 ||
 987            opcode == SHADER_OPCODE_TG4_OFFSET);
 988 }
 989
 990 bool
 991 backend_instruction::is_math() const
 992 {
 993    return (opcode == SHADER_OPCODE_RCP ||
 994            opcode == SHADER_OPCODE_RSQ ||
 995            opcode == SHADER_OPCODE_SQRT ||
 996            opcode == SHADER_OPCODE_EXP2 ||
 997            opcode == SHADER_OPCODE_LOG2 ||
 998            opcode == SHADER_OPCODE_SIN ||
 999            opcode == SHADER_OPCODE_COS ||
1000            opcode == SHADER_OPCODE_INT_QUOTIENT ||
1001            opcode == SHADER_OPCODE_INT_REMAINDER ||
1002            opcode == SHADER_OPCODE_POW);
1003 }
1004
1005 bool
1006 backend_instruction::is_control_flow() const
1007 {
1008    switch (opcode) {
1009    case BRW_OPCODE_DO:
1010    case BRW_OPCODE_WHILE:
1011    case BRW_OPCODE_IF:
1012    case BRW_OPCODE_ELSE:
1013    case BRW_OPCODE_ENDIF:
1014    case BRW_OPCODE_BREAK:
1015    case BRW_OPCODE_CONTINUE:
1016       return true;
1017    default:
1018       return false;
1019    }
1020 }
1021
1022 bool
1023 backend_instruction::can_do_source_mods() const
1024 {
1025    switch (opcode) {
1026    case BRW_OPCODE_ADDC:
1027    case BRW_OPCODE_BFE:
1028    case BRW_OPCODE_BFI1:
1029    case BRW_OPCODE_BFI2:
1030    case BRW_OPCODE_BFREV:
1031    case BRW_OPCODE_CBIT:
1032    case BRW_OPCODE_FBH:
1033    case BRW_OPCODE_FBL:
1034    case BRW_OPCODE_SUBB:
1035       return false;
1036    default:
1037       return true;
1038    }
1039 }
1040
1041 bool
1042 backend_instruction::can_do_saturate() const
1043 {
1044    switch (opcode) {
1045    case BRW_OPCODE_ADD:
1046    case BRW_OPCODE_ASR:
1047    case BRW_OPCODE_AVG:
1048    case BRW_OPCODE_DP2:
1049    case BRW_OPCODE_DP3:
1050    case BRW_OPCODE_DP4:
1051    case BRW_OPCODE_DPH:
1052    case BRW_OPCODE_F16TO32:
1053    case BRW_OPCODE_F32TO16:
1054    case BRW_OPCODE_LINE:
1055    case BRW_OPCODE_LRP:
1056    case BRW_OPCODE_MAC:
1057    case BRW_OPCODE_MAD:
1058    case BRW_OPCODE_MATH:
1059    case BRW_OPCODE_MOV:
1060    case BRW_OPCODE_MUL:
1061    case BRW_OPCODE_PLN:
1062    case BRW_OPCODE_RNDD:
1063    case BRW_OPCODE_RNDE:
1064    case BRW_OPCODE_RNDU:
1065    case BRW_OPCODE_RNDZ:
1066    case BRW_OPCODE_SEL:
1067    case BRW_OPCODE_SHL:
1068    case BRW_OPCODE_SHR:
1069    case FS_OPCODE_LINTERP:
1070    case SHADER_OPCODE_COS:
1071    case SHADER_OPCODE_EXP2:
1072    case SHADER_OPCODE_LOG2:
1073    case SHADER_OPCODE_POW:
1074    case SHADER_OPCODE_RCP:
1075    case SHADER_OPCODE_RSQ:
1076    case SHADER_OPCODE_SIN:
1077    case SHADER_OPCODE_SQRT:
1078       return true;
1079    default:
1080       return false;
1081    }
1082 }
1083
1084 bool
1085 backend_instruction::can_do_cmod() const
1086 {
1087    switch (opcode) {
1088    case BRW_OPCODE_ADD:
1089    case BRW_OPCODE_ADDC:
1090    case BRW_OPCODE_AND:
1091    case BRW_OPCODE_ASR:
1092    case BRW_OPCODE_AVG:
1093    case BRW_OPCODE_CMP:
1094    case BRW_OPCODE_CMPN:
1095    case BRW_OPCODE_DP2:
1096    case BRW_OPCODE_DP3:
1097    case BRW_OPCODE_DP4:
1098    case BRW_OPCODE_DPH:
1099    case BRW_OPCODE_F16TO32:
1100    case BRW_OPCODE_F32TO16:
1101    case BRW_OPCODE_FRC:
1102    case BRW_OPCODE_LINE:
1103    case BRW_OPCODE_LRP:
1104    case BRW_OPCODE_LZD:
1105    case BRW_OPCODE_MAC:
1106    case BRW_OPCODE_MACH:
1107    case BRW_OPCODE_MAD:
1108    case BRW_OPCODE_MOV:
1109    case BRW_OPCODE_MUL:
1110    case BRW_OPCODE_NOT:
1111    case BRW_OPCODE_OR:
1112    case BRW_OPCODE_PLN:
1113    case BRW_OPCODE_RNDD:
1114    case BRW_OPCODE_RNDE:
1115    case BRW_OPCODE_RNDU:
1116    case BRW_OPCODE_RNDZ:
1117    case BRW_OPCODE_SAD2:
1118    case BRW_OPCODE_SADA2:
1119    case BRW_OPCODE_SHL:
1120    case BRW_OPCODE_SHR:
1121    case BRW_OPCODE_SUBB:
1122    case BRW_OPCODE_XOR:
1123    case FS_OPCODE_CINTERP:
1124    case FS_OPCODE_LINTERP:
1125       return true;
1126    default:
1127       return false;
1128    }
1129 }
1130
1131 bool
1132 backend_instruction::reads_accumulator_implicitly() const
1133 {
1134    switch (opcode) {
1135    case BRW_OPCODE_MAC:
1136    case BRW_OPCODE_MACH:
1137    case BRW_OPCODE_SADA2:
1138       return true;
1139    default:
1140       return false;
1141    }
1142 }
1143
1144 bool
1145 backend_instruction::writes_accumulator_implicitly(const struct brw_device_info *devinfo) const
1146 {
1147    return writes_accumulator ||
1148           (devinfo->gen < 6 &&
1149            ((opcode >= BRW_OPCODE_ADD && opcode < BRW_OPCODE_NOP) ||
1150             (opcode >= FS_OPCODE_DDX_COARSE && opcode <= FS_OPCODE_LINTERP &&
1151              opcode != FS_OPCODE_CINTERP)));
1152 }
1153
1154 bool
1155 backend_instruction::has_side_effects() const
1156 {
1157    switch (opcode) {
1158    case SHADER_OPCODE_UNTYPED_ATOMIC:
1159    case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1160    case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
1161    case SHADER_OPCODE_TYPED_ATOMIC:
1162    case SHADER_OPCODE_TYPED_SURFACE_WRITE:
1163    case SHADER_OPCODE_MEMORY_FENCE:
1164    case SHADER_OPCODE_URB_WRITE_SIMD8:
1165    case FS_OPCODE_FB_WRITE:
1166    case SHADER_OPCODE_BARRIER:
1167       return true;
1168    default:
1169       return false;
1170    }
1171 }
1172
1173 #ifndef NDEBUG
1174 static bool
1175 inst_is_in_block(const bblock_t *block, const backend_instruction *inst)
1176 {
1177    bool found = false;
1178    foreach_inst_in_block (backend_instruction, i, block) {
1179       if (inst == i) {
1180          found = true;
1181       }
1182    }
1183    return found;
1184 }
1185 #endif
1186
1187 static void
1188 adjust_later_block_ips(bblock_t *start_block, int ip_adjustment)
1189 {
1190    for (bblock_t *block_iter = start_block->next();
1191         !block_iter->link.is_tail_sentinel();
1192         block_iter = block_iter->next()) {
1193       block_iter->start_ip += ip_adjustment;
1194       block_iter->end_ip += ip_adjustment;
1195    }
1196 }
1197
1198 void
1199 backend_instruction::insert_after(bblock_t *block, backend_instruction *inst)
1200 {
1201    if (!this->is_head_sentinel())
1202       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1203
1204    block->end_ip++;
1205
1206    adjust_later_block_ips(block, 1);
1207
1208    exec_node::insert_after(inst);
1209 }
1210
1211 void
1212 backend_instruction::insert_before(bblock_t *block, backend_instruction *inst)
1213 {
1214    if (!this->is_tail_sentinel())
1215       assert(inst_is_in_block(block, this) || !"Instruction not in block");
1216
1217    block->end_ip++;
1218
1219    adjust_later_block_ips(block, 1);
1220
1221    exec_node::insert_before(inst);
1222 }
1223
1224 void
1225 backend_instruction::insert_before(bblock_t *block, exec_list *list)
1226 {
1227    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1228
1229    unsigned num_inst = list->length();
1230
1231    block->end_ip += num_inst;
1232
1233    adjust_later_block_ips(block, num_inst);
1234
1235    exec_node::insert_before(list);
1236 }
1237
1238 void
1239 backend_instruction::remove(bblock_t *block)
1240 {
1241    assert(inst_is_in_block(block, this) || !"Instruction not in block");
1242
1243    adjust_later_block_ips(block, -1);
1244
1245    if (block->start_ip == block->end_ip) {
1246       block->cfg->remove_block(block);
1247    } else {
1248       block->end_ip--;
1249    }
1250
1251    exec_node::remove();
1252 }
1253
1254 void
1255 backend_shader::dump_instructions()
1256 {
1257    dump_instructions(NULL);
1258 }
1259
1260 void
1261 backend_shader::dump_instructions(const char *name)
1262 {
1263    FILE *file = stderr;
1264    if (name && geteuid() != 0) {
1265       file = fopen(name, "w");
1266       if (!file)
1267          file = stderr;
1268    }
1269
1270    if (cfg) {
1271       int ip = 0;
1272       foreach_block_and_inst(block, backend_instruction, inst, cfg) {
1273          fprintf(file, "%4d: ", ip++);
1274          dump_instruction(inst, file);
1275       }
1276    } else {
1277       int ip = 0;
1278       foreach_in_list(backend_instruction, inst, &instructions) {
1279          fprintf(file, "%4d: ", ip++);
1280          dump_instruction(inst, file);
1281       }
1282    }
1283
1284    if (file != stderr) {
1285       fclose(file);
1286    }
1287 }
1288
1289 void
1290 backend_shader::calculate_cfg()
1291 {
1292    if (this->cfg)
1293       return;
1294    cfg = new(mem_ctx) cfg_t(&this->instructions);
1295 }
1296
1297 void
1298 backend_shader::invalidate_cfg()
1299 {
1300    ralloc_free(this->cfg);
1301    this->cfg = NULL;
1302 }
1303
1304 /**
1305  * Sets up the starting offsets for the groups of binding table entries
1306  * commong to all pipeline stages.
1307  *
1308  * Unused groups are initialized to 0xd0d0d0d0 to make it obvious that they're
1309  * unused but also make sure that addition of small offsets to them will
1310  * trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
1311  */
1312 void
1313 backend_shader::assign_common_binding_table_offsets(uint32_t next_binding_table_offset)
1314 {
1315    int num_textures = _mesa_fls(prog->SamplersUsed);
1316
1317    stage_prog_data->binding_table.texture_start = next_binding_table_offset;
1318    next_binding_table_offset += num_textures;
1319
1320    if (shader) {
1321       stage_prog_data->binding_table.ubo_start = next_binding_table_offset;
1322       next_binding_table_offset += shader->base.NumUniformBlocks;
1323    } else {
1324       stage_prog_data->binding_table.ubo_start = 0xd0d0d0d0;
1325    }
1326
1327    if (INTEL_DEBUG & DEBUG_SHADER_TIME) {
1328       stage_prog_data->binding_table.shader_time_start = next_binding_table_offset;
1329       next_binding_table_offset++;
1330    } else {
1331       stage_prog_data->binding_table.shader_time_start = 0xd0d0d0d0;
1332    }
1333
1334    if (prog->UsesGather) {
1335       if (devinfo->gen >= 8) {
1336          stage_prog_data->binding_table.gather_texture_start =
1337             stage_prog_data->binding_table.texture_start;
1338       } else {
1339          stage_prog_data->binding_table.gather_texture_start = next_binding_table_offset;
1340          next_binding_table_offset += num_textures;
1341       }
1342    } else {
1343       stage_prog_data->binding_table.gather_texture_start = 0xd0d0d0d0;
1344    }
1345
1346    if (shader_prog && shader_prog->NumAtomicBuffers) {
1347       stage_prog_data->binding_table.abo_start = next_binding_table_offset;
1348       next_binding_table_offset += shader_prog->NumAtomicBuffers;
1349    } else {
1350       stage_prog_data->binding_table.abo_start = 0xd0d0d0d0;
1351    }
1352
1353    if (shader && shader->base.NumImages) {
1354       stage_prog_data->binding_table.image_start = next_binding_table_offset;
1355       next_binding_table_offset += shader->base.NumImages;
1356    } else {
1357       stage_prog_data->binding_table.image_start = 0xd0d0d0d0;
1358    }
1359
1360    /* This may or may not be used depending on how the compile goes. */
1361    stage_prog_data->binding_table.pull_constants_start = next_binding_table_offset;
1362    next_binding_table_offset++;
1363
1364    assert(next_binding_table_offset <= BRW_MAX_SURFACES);
1365
1366    /* prog_data->base.binding_table.size will be set by brw_mark_surface_used. */
1367 }