src/mesa/drivers/dri/i965/brw_shader.h

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <stdint.h>
  25 #include "brw_reg.h"
  26 #include "brw_defines.h"
  27 #include "brw_context.h"
  28 #include "main/compiler.h"
  29 #include "glsl/ir.h"
  30 #include "program/prog_parameter.h"
  31
  32 #ifdef __cplusplus
  33 #include "brw_ir_allocator.h"
  34 #endif
  35
  36 #pragma once
  37
  38 #define MAX_SAMPLER_MESSAGE_SIZE 11
  39 #define MAX_VGRF_SIZE 16
  40
  41 #ifdef __cplusplus
  42 struct backend_reg : public brw_reg
  43 {
  44    backend_reg() {}
  45    backend_reg(struct brw_reg reg) : brw_reg(reg) {}
  46
  47    bool is_zero() const;
  48    bool is_one() const;
  49    bool is_negative_one() const;
  50    bool is_null() const;
  51    bool is_accumulator() const;
  52    bool in_range(const backend_reg &r, unsigned n) const;
  53
  54    /**
  55     * Offset within the virtual register.
  56     *
  57     * In the scalar backend, this is in units of a float per pixel for pre-
  58     * register allocation registers (i.e., one register in SIMD8 mode and two
  59     * registers in SIMD16 mode).
  60     *
  61     * For uniforms, this is in units of 1 float.
  62     */
  63    uint16_t reg_offset;
  64 };
  65 #endif
  66
  67 struct cfg_t;
  68 struct bblock_t;
  69
  70 #ifdef __cplusplus
  71 struct backend_instruction : public exec_node {
  72    bool is_3src() const;
  73    bool is_tex() const;
  74    bool is_math() const;
  75    bool is_control_flow() const;
  76    bool is_commutative() const;
  77    bool can_do_source_mods() const;
  78    bool can_do_saturate() const;
  79    bool can_do_cmod() const;
  80    bool reads_accumulator_implicitly() const;
  81    bool writes_accumulator_implicitly(const struct brw_device_info *devinfo) const;
  82
  83    void remove(bblock_t *block);
  84    void insert_after(bblock_t *block, backend_instruction *inst);
  85    void insert_before(bblock_t *block, backend_instruction *inst);
  86    void insert_before(bblock_t *block, exec_list *list);
  87
  88    /**
  89     * True if the instruction has side effects other than writing to
  90     * its destination registers.  You are expected not to reorder or
  91     * optimize these out unless you know what you are doing.
  92     */
  93    bool has_side_effects() const;
  94
  95    /**
  96     * True if the instruction might be affected by side effects of other
  97     * instructions.
  98     */
  99    bool is_volatile() const;
 100 #else
 101 struct backend_instruction {
 102    struct exec_node link;
 103 #endif
 104    /** @{
 105     * Annotation for the generated IR.  One of the two can be set.
 106     */
 107    const void *ir;
 108    const char *annotation;
 109    /** @} */
 110
 111    uint32_t offset; /**< spill/unspill offset or texture offset bitfield */
 112    uint8_t mlen; /**< SEND message length */
 113    int8_t base_mrf; /**< First MRF in the SEND message, if mlen is nonzero. */
 114    uint8_t target; /**< MRT target. */
 115    uint8_t regs_written; /**< Number of registers written by the instruction. */
 116
 117    enum opcode opcode; /* BRW_OPCODE_* or FS_OPCODE_* */
 118    enum brw_conditional_mod conditional_mod; /**< BRW_CONDITIONAL_* */
 119    enum brw_predicate predicate;
 120    bool predicate_inverse:1;
 121    bool writes_accumulator:1; /**< instruction implicitly writes accumulator */
 122    bool force_writemask_all:1;
 123    bool no_dd_clear:1;
 124    bool no_dd_check:1;
 125    bool saturate:1;
 126    bool shadow_compare:1;
 127
 128    /* Chooses which flag subregister (f0.0 or f0.1) is used for conditional
 129     * mod and predication.
 130     */
 131    unsigned flag_subreg:1;
 132
 133    /** The number of hardware registers used for a message header. */
 134    uint8_t header_size;
 135 };
 136
 137 #ifdef __cplusplus
 138
 139 enum instruction_scheduler_mode {
 140    SCHEDULE_PRE,
 141    SCHEDULE_PRE_NON_LIFO,
 142    SCHEDULE_PRE_LIFO,
 143    SCHEDULE_POST,
 144 };
 145
 146 struct backend_shader {
 147 protected:
 148
 149    backend_shader(const struct brw_compiler *compiler,
 150                   void *log_data,
 151                   void *mem_ctx,
 152                   const nir_shader *shader,
 153                   struct brw_stage_prog_data *stage_prog_data);
 154
 155 public:
 156
 157    const struct brw_compiler *compiler;
 158    void *log_data; /* Passed to compiler->*_log functions */
 159
 160    const struct brw_device_info * const devinfo;
 161    const nir_shader *nir;
 162    struct brw_stage_prog_data * const stage_prog_data;
 163
 164    /** ralloc context for temporary data used during compile */
 165    void *mem_ctx;
 166
 167    /**
 168     * List of either fs_inst or vec4_instruction (inheriting from
 169     * backend_instruction)
 170     */
 171    exec_list instructions;
 172
 173    cfg_t *cfg;
 174
 175    gl_shader_stage stage;
 176    bool debug_enabled;
 177    const char *stage_name;
 178    const char *stage_abbrev;
 179
 180    brw::simple_allocator alloc;
 181
 182    virtual void dump_instruction(backend_instruction *inst) = 0;
 183    virtual void dump_instruction(backend_instruction *inst, FILE *file) = 0;
 184    virtual void dump_instructions();
 185    virtual void dump_instructions(const char *name);
 186
 187    void calculate_cfg();
 188    void invalidate_cfg();
 189
 190    virtual void invalidate_live_intervals() = 0;
 191 };
 192
 193 uint32_t brw_texture_offset(int *offsets, unsigned num_components);
 194
 195 void brw_setup_image_uniform_values(gl_shader_stage stage,
 196                                     struct brw_stage_prog_data *stage_prog_data,
 197                                     unsigned param_start_index,
 198                                     const gl_uniform_storage *storage);
 199
 200 #else
 201 struct backend_shader;
 202 #endif /* __cplusplus */
 203
 204 enum brw_reg_type brw_type_for_base_type(const struct glsl_type *type);
 205 enum brw_conditional_mod brw_conditional_for_comparison(unsigned int op);
 206 uint32_t brw_math_function(enum opcode op);
 207 const char *brw_instruction_name(enum opcode op);
 208 bool brw_saturate_immediate(enum brw_reg_type type, struct brw_reg *reg);
 209 bool brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg);
 210 bool brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg);
 211
 212 bool opt_predicated_break(struct backend_shader *s);
 213
 214 #ifdef __cplusplus
 215 extern "C" {
 216 #endif
 217
 218 /**
 219  * Scratch data used when compiling a GLSL geometry shader.
 220  */
 221 struct brw_gs_compile
 222 {
 223    struct brw_gs_prog_key key;
 224    struct brw_vue_map input_vue_map;
 225
 226    unsigned control_data_bits_per_vertex;
 227    unsigned control_data_header_size_bits;
 228 };
 229
 230 void
 231 brw_assign_common_binding_table_offsets(gl_shader_stage stage,
 232                                         const struct brw_device_info *devinfo,
 233                                         const struct gl_shader_program *shader_prog,
 234                                         const struct gl_program *prog,
 235                                         struct brw_stage_prog_data *stage_prog_data,
 236                                         uint32_t next_binding_table_offset);
 237
 238 bool brw_vs_precompile(struct gl_context *ctx,
 239                        struct gl_shader_program *shader_prog,
 240                        struct gl_program *prog);
 241 bool brw_gs_precompile(struct gl_context *ctx,
 242                        struct gl_shader_program *shader_prog,
 243                        struct gl_program *prog);
 244 bool brw_fs_precompile(struct gl_context *ctx,
 245                        struct gl_shader_program *shader_prog,
 246                        struct gl_program *prog);
 247 bool brw_cs_precompile(struct gl_context *ctx,
 248                        struct gl_shader_program *shader_prog,
 249                        struct gl_program *prog);
 250
 251 int type_size_scalar(const struct glsl_type *type);
 252 int type_size_vec4(const struct glsl_type *type);
 253 int type_size_vec4_times_4(const struct glsl_type *type);
 254
 255 #ifdef __cplusplus
 256 }
 257 #endif