src/mesa/drivers/dri/i965/brw_state_batch.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33
  34 #include "brw_state.h"
  35 #include "intel_batchbuffer.h"
  36 #include "main/imports.h"
  37
  38
  39
  40 /* A facility similar to the data caching code above, which aims to
  41  * prevent identical commands being issued repeatedly.
  42  */
  43 GLboolean brw_cached_batch_struct( struct brw_context *brw,
  44                                    const void *data,
  45                                    GLuint sz )
  46 {
  47    struct brw_cached_batch_item *item = brw->cached_batch_items;
  48    struct header *newheader = (struct header *)data;
  49
  50    if (brw->emit_state_always) {
  51       intel_batchbuffer_data(brw->intel.batch, data, sz, false);
  52       return GL_TRUE;
  53    }
  54
  55    while (item) {
  56       if (item->header->opcode == newheader->opcode) {
  57          if (item->sz == sz && memcmp(item->header, newheader, sz) == 0)
  58             return GL_FALSE;
  59          if (item->sz != sz) {
  60             free(item->header);
  61             item->header = malloc(sz);
  62             item->sz = sz;
  63          }
  64          goto emit;
  65       }
  66       item = item->next;
  67    }
  68
  69    assert(!item);
  70    item = CALLOC_STRUCT(brw_cached_batch_item);
  71    item->header = malloc(sz);
  72    item->sz = sz;
  73    item->next = brw->cached_batch_items;
  74    brw->cached_batch_items = item;
  75
  76  emit:
  77    memcpy(item->header, newheader, sz);
  78    intel_batchbuffer_data(brw->intel.batch, data, sz, false);
  79    return GL_TRUE;
  80 }
  81
  82 void brw_clear_batch_cache( struct brw_context *brw )
  83 {
  84    struct brw_cached_batch_item *item = brw->cached_batch_items;
  85
  86    while (item) {
  87       struct brw_cached_batch_item *next = item->next;
  88       free((void *)item->header);
  89       free(item);
  90       item = next;
  91    }
  92
  93    brw->cached_batch_items = NULL;
  94 }
  95
  96 void brw_destroy_batch_cache( struct brw_context *brw )
  97 {
  98    brw_clear_batch_cache(brw);
  99 }
 100
 101 /**
 102  * Allocates a block of space in the batchbuffer for indirect state.
 103  *
 104  * We don't want to allocate separate BOs for every bit of indirect
 105  * state in the driver.  It means overallocating by a significant
 106  * margin (4096 bytes, even if the object is just a 20-byte surface
 107  * state), and more buffers to walk and count for aperture size checking.
 108  *
 109  * However, due to the restrictions inposed by the aperture size
 110  * checking performance hacks, we can't have the batch point at a
 111  * separate indirect state buffer, because once the batch points at
 112  * it, no more relocations can be added to it.  So, we sneak these
 113  * buffers in at the top of the batchbuffer.
 114  */
 115 void *
 116 brw_state_batch(struct brw_context *brw,
 117                 int size,
 118                 int alignment,
 119                 drm_intel_bo **out_bo,
 120                 uint32_t *out_offset)
 121 {
 122    struct intel_batchbuffer *batch = brw->intel.batch;
 123    uint32_t offset;
 124
 125    assert(size < batch->buf->size);
 126    offset = ROUND_DOWN_TO(batch->state_batch_offset - size, alignment);
 127
 128    /* If allocating from the top would wrap below the batchbuffer, or
 129     * if the batch's used space (plus the reserved pad) collides with our
 130     * space, then flush and try again.
 131     */
 132    if (batch->state_batch_offset < size ||
 133        offset < batch->ptr - batch->map + batch->reserved_space) {
 134       intel_batchbuffer_flush(batch);
 135       offset = ROUND_DOWN_TO(batch->state_batch_offset - size, alignment);
 136    }
 137
 138    batch->state_batch_offset = offset;
 139
 140    if (*out_bo != batch->buf) {
 141       drm_intel_bo_unreference(*out_bo);
 142       drm_intel_bo_reference(batch->buf);
 143       *out_bo = batch->buf;
 144    }
 145
 146    *out_offset = offset;
 147    return batch->map + offset;
 148 }