src/mesa/drivers/dri/i965/brw_state_upload.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33
  34 #include "brw_context.h"
  35 #include "brw_state.h"
  36 #include "intel_batchbuffer.h"
  37 #include "intel_buffers.h"
  38
  39 static const struct brw_tracked_state *atoms[] =
  40 {
  41    &brw_check_fallback,
  42
  43    &brw_wm_input_sizes,
  44    &brw_vs_prog,
  45    &brw_gs_prog,
  46    &brw_clip_prog,
  47    &brw_sf_prog,
  48    &brw_wm_prog,
  49
  50    /* Once all the programs are done, we know how large urb entry
  51     * sizes need to be and can decide if we need to change the urb
  52     * layout.
  53     */
  54    &brw_curbe_offsets,
  55    &brw_recalculate_urb_fence,
  56
  57    &brw_cc_vp,
  58    &brw_cc_unit,
  59
  60    &brw_vs_surfaces,            /* must do before unit */
  61    &brw_wm_constant_surface,    /* must do before wm surfaces/bind bo */
  62    &brw_wm_surfaces,            /* must do before samplers and unit */
  63    &brw_wm_samplers,
  64
  65    &brw_wm_unit,
  66    &brw_sf_vp,
  67    &brw_sf_unit,
  68    &brw_vs_unit,                /* always required, enabled or not */
  69    &brw_clip_unit,
  70    &brw_gs_unit,
  71
  72    /* Command packets:
  73     */
  74    &brw_invarient_state,
  75    &brw_state_base_address,
  76
  77    &brw_binding_table_pointers,
  78    &brw_blend_constant_color,
  79
  80    &brw_depthbuffer,
  81
  82    &brw_polygon_stipple,
  83    &brw_polygon_stipple_offset,
  84
  85    &brw_line_stipple,
  86    &brw_aa_line_parameters,
  87
  88    &brw_psp_urb_cbs,
  89
  90    &brw_drawing_rect,
  91    &brw_indices,
  92    &brw_index_buffer,
  93    &brw_vertices,
  94
  95    &brw_constant_buffer
  96 };
  97
  98
  99 void brw_init_state( struct brw_context *brw )
 100 {
 101    brw_init_caches(brw);
 102 }
 103
 104
 105 void brw_destroy_state( struct brw_context *brw )
 106 {
 107    brw_destroy_caches(brw);
 108    brw_destroy_batch_cache(brw);
 109 }
 110
 111 /***********************************************************************
 112  */
 113
 114 static GLboolean check_state( const struct brw_state_flags *a,
 115                               const struct brw_state_flags *b )
 116 {
 117    return ((a->mesa & b->mesa) ||
 118            (a->brw & b->brw) ||
 119            (a->cache & b->cache));
 120 }
 121
 122 static void accumulate_state( struct brw_state_flags *a,
 123                               const struct brw_state_flags *b )
 124 {
 125    a->mesa |= b->mesa;
 126    a->brw |= b->brw;
 127    a->cache |= b->cache;
 128 }
 129
 130
 131 static void xor_states( struct brw_state_flags *result,
 132                              const struct brw_state_flags *a,
 133                               const struct brw_state_flags *b )
 134 {
 135    result->mesa = a->mesa ^ b->mesa;
 136    result->brw = a->brw ^ b->brw;
 137    result->cache = a->cache ^ b->cache;
 138 }
 139
 140 void
 141 brw_clear_validated_bos(struct brw_context *brw)
 142 {
 143    int i;
 144
 145    /* Clear the last round of validated bos */
 146    for (i = 0; i < brw->state.validated_bo_count; i++) {
 147       dri_bo_unreference(brw->state.validated_bos[i]);
 148       brw->state.validated_bos[i] = NULL;
 149    }
 150    brw->state.validated_bo_count = 0;
 151 }
 152
 153 struct dirty_bit_map {
 154    uint32_t bit;
 155    char *name;
 156    uint32_t count;
 157 };
 158
 159 #define DEFINE_BIT(name) {name, #name, 0}
 160
 161 static struct dirty_bit_map mesa_bits[] = {
 162    DEFINE_BIT(_NEW_MODELVIEW),
 163    DEFINE_BIT(_NEW_PROJECTION),
 164    DEFINE_BIT(_NEW_TEXTURE_MATRIX),
 165    DEFINE_BIT(_NEW_COLOR_MATRIX),
 166    DEFINE_BIT(_NEW_ACCUM),
 167    DEFINE_BIT(_NEW_COLOR),
 168    DEFINE_BIT(_NEW_DEPTH),
 169    DEFINE_BIT(_NEW_EVAL),
 170    DEFINE_BIT(_NEW_FOG),
 171    DEFINE_BIT(_NEW_HINT),
 172    DEFINE_BIT(_NEW_LIGHT),
 173    DEFINE_BIT(_NEW_LINE),
 174    DEFINE_BIT(_NEW_PIXEL),
 175    DEFINE_BIT(_NEW_POINT),
 176    DEFINE_BIT(_NEW_POLYGON),
 177    DEFINE_BIT(_NEW_POLYGONSTIPPLE),
 178    DEFINE_BIT(_NEW_SCISSOR),
 179    DEFINE_BIT(_NEW_STENCIL),
 180    DEFINE_BIT(_NEW_TEXTURE),
 181    DEFINE_BIT(_NEW_TRANSFORM),
 182    DEFINE_BIT(_NEW_VIEWPORT),
 183    DEFINE_BIT(_NEW_PACKUNPACK),
 184    DEFINE_BIT(_NEW_ARRAY),
 185    DEFINE_BIT(_NEW_RENDERMODE),
 186    DEFINE_BIT(_NEW_BUFFERS),
 187    DEFINE_BIT(_NEW_MULTISAMPLE),
 188    DEFINE_BIT(_NEW_TRACK_MATRIX),
 189    DEFINE_BIT(_NEW_PROGRAM),
 190    DEFINE_BIT(_NEW_PROGRAM_CONSTANTS),
 191    {0, 0, 0}
 192 };
 193
 194 static struct dirty_bit_map brw_bits[] = {
 195    DEFINE_BIT(BRW_NEW_URB_FENCE),
 196    DEFINE_BIT(BRW_NEW_FRAGMENT_PROGRAM),
 197    DEFINE_BIT(BRW_NEW_VERTEX_PROGRAM),
 198    DEFINE_BIT(BRW_NEW_INPUT_DIMENSIONS),
 199    DEFINE_BIT(BRW_NEW_CURBE_OFFSETS),
 200    DEFINE_BIT(BRW_NEW_REDUCED_PRIMITIVE),
 201    DEFINE_BIT(BRW_NEW_PRIMITIVE),
 202    DEFINE_BIT(BRW_NEW_CONTEXT),
 203    DEFINE_BIT(BRW_NEW_WM_INPUT_DIMENSIONS),
 204    DEFINE_BIT(BRW_NEW_PSP),
 205    DEFINE_BIT(BRW_NEW_INDICES),
 206    DEFINE_BIT(BRW_NEW_INDEX_BUFFER),
 207    DEFINE_BIT(BRW_NEW_VERTICES),
 208    DEFINE_BIT(BRW_NEW_BATCH),
 209    DEFINE_BIT(BRW_NEW_DEPTH_BUFFER),
 210    {0, 0, 0}
 211 };
 212
 213 static struct dirty_bit_map cache_bits[] = {
 214    DEFINE_BIT(CACHE_NEW_CC_VP),
 215    DEFINE_BIT(CACHE_NEW_CC_UNIT),
 216    DEFINE_BIT(CACHE_NEW_WM_PROG),
 217    DEFINE_BIT(CACHE_NEW_SAMPLER_DEFAULT_COLOR),
 218    DEFINE_BIT(CACHE_NEW_SAMPLER),
 219    DEFINE_BIT(CACHE_NEW_WM_UNIT),
 220    DEFINE_BIT(CACHE_NEW_SF_PROG),
 221    DEFINE_BIT(CACHE_NEW_SF_VP),
 222    DEFINE_BIT(CACHE_NEW_SF_UNIT),
 223    DEFINE_BIT(CACHE_NEW_VS_UNIT),
 224    DEFINE_BIT(CACHE_NEW_VS_PROG),
 225    DEFINE_BIT(CACHE_NEW_GS_UNIT),
 226    DEFINE_BIT(CACHE_NEW_GS_PROG),
 227    DEFINE_BIT(CACHE_NEW_CLIP_VP),
 228    DEFINE_BIT(CACHE_NEW_CLIP_UNIT),
 229    DEFINE_BIT(CACHE_NEW_CLIP_PROG),
 230    DEFINE_BIT(CACHE_NEW_SURFACE),
 231    DEFINE_BIT(CACHE_NEW_SURF_BIND),
 232    {0, 0, 0}
 233 };
 234
 235
 236 static void
 237 brw_update_dirty_count(struct dirty_bit_map *bit_map, int32_t bits)
 238 {
 239    int i;
 240
 241    for (i = 0; i < 32; i++) {
 242       if (bit_map[i].bit == 0)
 243          return;
 244
 245       if (bit_map[i].bit & bits)
 246          bit_map[i].count++;
 247    }
 248 }
 249
 250 static void
 251 brw_print_dirty_count(struct dirty_bit_map *bit_map, int32_t bits)
 252 {
 253    int i;
 254
 255    for (i = 0; i < 32; i++) {
 256       if (bit_map[i].bit == 0)
 257          return;
 258
 259       fprintf(stderr, "0x%08x: %12d (%s)\n",
 260               bit_map[i].bit, bit_map[i].count, bit_map[i].name);
 261    }
 262 }
 263
 264 /***********************************************************************
 265  * Emit all state:
 266  */
 267 void brw_validate_state( struct brw_context *brw )
 268 {
 269    GLcontext *ctx = &brw->intel.ctx;
 270    struct intel_context *intel = &brw->intel;
 271    struct brw_state_flags *state = &brw->state.dirty;
 272    GLuint i;
 273
 274    brw_clear_validated_bos(brw);
 275
 276    state->mesa |= brw->intel.NewGLState;
 277    brw->intel.NewGLState = 0;
 278
 279    brw_add_validated_bo(brw, intel->batch->buf);
 280
 281    if (brw->emit_state_always) {
 282       state->mesa |= ~0;
 283       state->brw |= ~0;
 284       state->cache |= ~0;
 285    }
 286
 287    if (brw->fragment_program != ctx->FragmentProgram._Current) {
 288       brw->fragment_program = ctx->FragmentProgram._Current;
 289       brw->state.dirty.brw |= BRW_NEW_FRAGMENT_PROGRAM;
 290    }
 291
 292    if (brw->vertex_program != ctx->VertexProgram._Current) {
 293       brw->vertex_program = ctx->VertexProgram._Current;
 294       brw->state.dirty.brw |= BRW_NEW_VERTEX_PROGRAM;
 295    }
 296
 297    if (state->mesa == 0 &&
 298        state->cache == 0 &&
 299        state->brw == 0)
 300       return;
 301
 302    if (brw->state.dirty.brw & BRW_NEW_CONTEXT)
 303       brw_clear_batch_cache(brw);
 304
 305    brw->intel.Fallback = GL_FALSE; /* boolean, not bitfield */
 306
 307    /* do prepare stage for all atoms */
 308    for (i = 0; i < Elements(atoms); i++) {
 309       const struct brw_tracked_state *atom = atoms[i];
 310
 311       if (brw->intel.Fallback)
 312          break;
 313
 314       if (check_state(state, &atom->dirty)) {
 315          if (atom->prepare) {
 316             atom->prepare(brw);
 317         }
 318       }
 319    }
 320
 321    intel_check_front_buffer_rendering(intel);
 322
 323    /* Make sure that the textures which are referenced by the current
 324     * brw fragment program are actually present/valid.
 325     * If this fails, we can experience GPU lock-ups.
 326     */
 327    {
 328       const struct brw_fragment_program *fp;
 329       fp = brw_fragment_program_const(brw->fragment_program);
 330       if (fp) {
 331          assert((fp->tex_units_used & ctx->Texture._EnabledUnits)
 332                 == fp->tex_units_used);
 333       }
 334    }
 335 }
 336
 337
 338 void brw_upload_state(struct brw_context *brw)
 339 {
 340    struct brw_state_flags *state = &brw->state.dirty;
 341    int i;
 342    static int dirty_count = 0;
 343
 344    brw_clear_validated_bos(brw);
 345
 346    if (INTEL_DEBUG) {
 347       /* Debug version which enforces various sanity checks on the
 348        * state flags which are generated and checked to help ensure
 349        * state atoms are ordered correctly in the list.
 350        */
 351       struct brw_state_flags examined, prev;
 352       _mesa_memset(&examined, 0, sizeof(examined));
 353       prev = *state;
 354
 355       for (i = 0; i < Elements(atoms); i++) {
 356          const struct brw_tracked_state *atom = atoms[i];
 357          struct brw_state_flags generated;
 358
 359          assert(atom->dirty.mesa ||
 360                 atom->dirty.brw ||
 361                 atom->dirty.cache);
 362
 363          if (brw->intel.Fallback)
 364             break;
 365
 366          if (check_state(state, &atom->dirty)) {
 367             if (atom->emit) {
 368                atom->emit( brw );
 369             }
 370          }
 371
 372          accumulate_state(&examined, &atom->dirty);
 373
 374          /* generated = (prev ^ state)
 375           * if (examined & generated)
 376           *     fail;
 377           */
 378          xor_states(&generated, &prev, state);
 379          assert(!check_state(&examined, &generated));
 380          prev = *state;
 381       }
 382    }
 383    else {
 384       for (i = 0; i < Elements(atoms); i++) {
 385          const struct brw_tracked_state *atom = atoms[i];
 386
 387          if (brw->intel.Fallback)
 388             break;
 389
 390          if (check_state(state, &atom->dirty)) {
 391             if (atom->emit) {
 392                atom->emit( brw );
 393             }
 394          }
 395       }
 396    }
 397
 398    if (INTEL_DEBUG & DEBUG_STATE) {
 399       brw_update_dirty_count(mesa_bits, state->mesa);
 400       brw_update_dirty_count(brw_bits, state->brw);
 401       brw_update_dirty_count(cache_bits, state->cache);
 402       if (dirty_count++ % 1000 == 0) {
 403          brw_print_dirty_count(mesa_bits, state->mesa);
 404          brw_print_dirty_count(brw_bits, state->brw);
 405          brw_print_dirty_count(cache_bits, state->cache);
 406          fprintf(stderr, "\n");
 407       }
 408    }
 409
 410    if (!brw->intel.Fallback)
 411       memset(state, 0, sizeof(*state));
 412 }