src/mesa/drivers/dri/i965/brw_tcs.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 /**
  25  * \file brw_tcs.c
  26  *
  27  * Tessellation control shader state upload code.
  28  */
  29
  30 #include "brw_context.h"
  31 #include "compiler/brw_nir.h"
  32 #include "brw_program.h"
  33 #include "brw_state.h"
  34 #include "program/prog_parameter.h"
  35 #include "nir_builder.h"
  36
  37 static bool
  38 brw_codegen_tcs_prog(struct brw_context *brw, struct brw_program *tcp,
  39                      struct brw_program *tep, struct brw_tcs_prog_key *key)
  40 {
  41    struct gl_context *ctx = &brw->ctx;
  42    const struct brw_compiler *compiler = brw->screen->compiler;
  43    const struct gen_device_info *devinfo = compiler->devinfo;
  44    struct brw_stage_state *stage_state = &brw->tcs.base;
  45    nir_shader *nir;
  46    struct brw_tcs_prog_data prog_data;
  47    bool start_busy = false;
  48    double start_time = 0;
  49
  50    void *mem_ctx = ralloc_context(NULL);
  51    if (tcp) {
  52       nir = nir_shader_clone(mem_ctx, tcp->program.nir);
  53    } else {
  54       const nir_shader_compiler_options *options =
  55          ctx->Const.ShaderCompilerOptions[MESA_SHADER_TESS_CTRL].NirOptions;
  56       nir = brw_nir_create_passthrough_tcs(mem_ctx, compiler, options, key);
  57    }
  58
  59    memset(&prog_data, 0, sizeof(prog_data));
  60
  61    if (tcp) {
  62       brw_assign_common_binding_table_offsets(devinfo, &tcp->program,
  63                                               &prog_data.base.base, 0);
  64
  65       brw_nir_setup_glsl_uniforms(mem_ctx, nir, &tcp->program,
  66                                   &prog_data.base.base,
  67                                   compiler->scalar_stage[MESA_SHADER_TESS_CTRL]);
  68       brw_nir_analyze_ubo_ranges(compiler, nir, NULL,
  69                                  prog_data.base.base.ubo_ranges);
  70    } else {
  71       /* Upload the Patch URB Header as the first two uniforms.
  72        * Do the annoying scrambling so the shader doesn't have to.
  73        */
  74       assert(nir->num_uniforms == 32);
  75       prog_data.base.base.param = rzalloc_array(mem_ctx, uint32_t, 8);
  76       prog_data.base.base.nr_params = 8;
  77
  78       uint32_t *param = prog_data.base.base.param;
  79       for (int i = 0; i < 8; i++)
  80          param[i] = BRW_PARAM_BUILTIN_ZERO;
  81
  82       if (key->tes_primitive_mode == GL_QUADS) {
  83          for (int i = 0; i < 4; i++)
  84             param[7 - i] = BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_X + i;
  85
  86          param[3] = BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_X;
  87          param[2] = BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_Y;
  88       } else if (key->tes_primitive_mode == GL_TRIANGLES) {
  89          for (int i = 0; i < 3; i++)
  90             param[7 - i] = BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_X + i;
  91
  92          param[4] = BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_X;
  93       } else {
  94          assert(key->tes_primitive_mode == GL_ISOLINES);
  95          param[7] = BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_Y;
  96          param[6] = BRW_PARAM_BUILTIN_TESS_LEVEL_OUTER_X;
  97       }
  98    }
  99
 100    int st_index = -1;
 101    if (unlikely((INTEL_DEBUG & DEBUG_SHADER_TIME) && tep))
 102       st_index = brw_get_shader_time_index(brw, &tep->program, ST_TCS, true);
 103
 104    if (unlikely(brw->perf_debug)) {
 105       start_busy = brw->batch.last_bo && brw_bo_busy(brw->batch.last_bo);
 106       start_time = get_time();
 107    }
 108
 109    char *error_str;
 110    const unsigned *program =
 111       brw_compile_tcs(compiler, brw, mem_ctx, key, &prog_data, nir, st_index,
 112                       NULL, &error_str);
 113    if (program == NULL) {
 114       if (tep) {
 115          tep->program.sh.data->LinkStatus = LINKING_FAILURE;
 116          ralloc_strcat(&tep->program.sh.data->InfoLog, error_str);
 117       }
 118
 119       _mesa_problem(NULL, "Failed to compile tessellation control shader: "
 120                     "%s\n", error_str);
 121
 122       ralloc_free(mem_ctx);
 123       return false;
 124    }
 125
 126    if (unlikely(brw->perf_debug)) {
 127       if (tcp) {
 128          if (tcp->compiled_once) {
 129             brw_debug_recompile(brw, MESA_SHADER_TESS_CTRL, tcp->program.Id,
 130                                 &key->base);
 131          }
 132          tcp->compiled_once = true;
 133       }
 134
 135       if (start_busy && !brw_bo_busy(brw->batch.last_bo)) {
 136          perf_debug("TCS compile took %.03f ms and stalled the GPU\n",
 137                     (get_time() - start_time) * 1000);
 138       }
 139    }
 140
 141    /* Scratch space is used for register spilling */
 142    brw_alloc_stage_scratch(brw, stage_state,
 143                            prog_data.base.base.total_scratch);
 144
 145    /* The param and pull_param arrays will be freed by the shader cache. */
 146    ralloc_steal(NULL, prog_data.base.base.param);
 147    ralloc_steal(NULL, prog_data.base.base.pull_param);
 148    brw_upload_cache(&brw->cache, BRW_CACHE_TCS_PROG,
 149                     key, sizeof(*key),
 150                     program, prog_data.base.base.program_size,
 151                     &prog_data, sizeof(prog_data),
 152                     &stage_state->prog_offset, &brw->tcs.base.prog_data);
 153    ralloc_free(mem_ctx);
 154
 155    return true;
 156 }
 157
 158 void
 159 brw_tcs_populate_key(struct brw_context *brw,
 160                      struct brw_tcs_prog_key *key)
 161 {
 162    const struct gen_device_info *devinfo = &brw->screen->devinfo;
 163    const struct brw_compiler *compiler = brw->screen->compiler;
 164    struct brw_program *tcp =
 165       (struct brw_program *) brw->programs[MESA_SHADER_TESS_CTRL];
 166    struct brw_program *tep =
 167       (struct brw_program *) brw->programs[MESA_SHADER_TESS_EVAL];
 168    struct gl_program *tes_prog = &tep->program;
 169
 170    uint64_t per_vertex_slots = tes_prog->info.inputs_read;
 171    uint32_t per_patch_slots = tes_prog->info.patch_inputs_read;
 172
 173    memset(key, 0, sizeof(*key));
 174
 175    if (tcp) {
 176       struct gl_program *prog = &tcp->program;
 177       per_vertex_slots |= prog->info.outputs_written;
 178       per_patch_slots |= prog->info.patch_outputs_written;
 179    }
 180
 181    if (devinfo->gen < 8 || !tcp || compiler->use_tcs_8_patch)
 182       key->input_vertices = brw->ctx.TessCtrlProgram.patch_vertices;
 183    key->outputs_written = per_vertex_slots;
 184    key->patch_outputs_written = per_patch_slots;
 185
 186    /* We need to specialize our code generation for tessellation levels
 187     * based on the domain the DS is expecting to tessellate.
 188     */
 189    key->tes_primitive_mode = tep->program.info.tess.primitive_mode;
 190    key->quads_workaround = devinfo->gen < 9 &&
 191                            tep->program.info.tess.primitive_mode == GL_QUADS &&
 192                            tep->program.info.tess.spacing == TESS_SPACING_EQUAL;
 193
 194    if (tcp) {
 195       /* _NEW_TEXTURE */
 196       brw_populate_base_prog_key(&brw->ctx, tcp, &key->base);
 197    }
 198 }
 199
 200 void
 201 brw_upload_tcs_prog(struct brw_context *brw)
 202 {
 203    struct brw_stage_state *stage_state = &brw->tcs.base;
 204    struct brw_tcs_prog_key key;
 205    /* BRW_NEW_TESS_PROGRAMS */
 206    struct brw_program *tcp =
 207       (struct brw_program *) brw->programs[MESA_SHADER_TESS_CTRL];
 208    ASSERTED struct brw_program *tep =
 209       (struct brw_program *) brw->programs[MESA_SHADER_TESS_EVAL];
 210    assert(tep);
 211
 212    if (!brw_state_dirty(brw,
 213                         _NEW_TEXTURE,
 214                         BRW_NEW_PATCH_PRIMITIVE |
 215                         BRW_NEW_TESS_PROGRAMS))
 216       return;
 217
 218    brw_tcs_populate_key(brw, &key);
 219
 220    if (brw_search_cache(&brw->cache, BRW_CACHE_TCS_PROG, &key, sizeof(key),
 221                         &stage_state->prog_offset, &brw->tcs.base.prog_data,
 222                         true))
 223       return;
 224
 225    if (brw_disk_cache_upload_program(brw, MESA_SHADER_TESS_CTRL))
 226       return;
 227
 228    tcp = (struct brw_program *) brw->programs[MESA_SHADER_TESS_CTRL];
 229    if (tcp)
 230       tcp->id = key.base.program_string_id;
 231
 232    ASSERTED bool success = brw_codegen_tcs_prog(brw, tcp, tep, &key);
 233    assert(success);
 234 }
 235
 236 void
 237 brw_tcs_populate_default_key(const struct brw_compiler *compiler,
 238                              struct brw_tcs_prog_key *key,
 239                              struct gl_shader_program *sh_prog,
 240                              struct gl_program *prog)
 241 {
 242    const struct gen_device_info *devinfo = compiler->devinfo;
 243    struct brw_program *btcp = brw_program(prog);
 244    const struct gl_linked_shader *tes =
 245       sh_prog->_LinkedShaders[MESA_SHADER_TESS_EVAL];
 246
 247    memset(key, 0, sizeof(*key));
 248
 249    brw_populate_default_base_prog_key(devinfo, btcp, &key->base);
 250
 251    /* Guess that the input and output patches have the same dimensionality. */
 252    if (devinfo->gen < 8 || compiler->use_tcs_8_patch)
 253       key->input_vertices = prog->info.tess.tcs_vertices_out;
 254
 255    if (tes) {
 256       key->tes_primitive_mode = tes->Program->info.tess.primitive_mode;
 257       key->quads_workaround = devinfo->gen < 9 &&
 258                               tes->Program->info.tess.primitive_mode == GL_QUADS &&
 259                               tes->Program->info.tess.spacing == TESS_SPACING_EQUAL;
 260    } else {
 261       key->tes_primitive_mode = GL_TRIANGLES;
 262    }
 263
 264    key->outputs_written = prog->nir->info.outputs_written;
 265    key->patch_outputs_written = prog->nir->info.patch_outputs_written;
 266 }
 267
 268 bool
 269 brw_tcs_precompile(struct gl_context *ctx,
 270                    struct gl_shader_program *shader_prog,
 271                    struct gl_program *prog)
 272 {
 273    struct brw_context *brw = brw_context(ctx);
 274    const struct brw_compiler *compiler = brw->screen->compiler;
 275    struct brw_tcs_prog_key key;
 276    uint32_t old_prog_offset = brw->tcs.base.prog_offset;
 277    struct brw_stage_prog_data *old_prog_data = brw->tcs.base.prog_data;
 278    bool success;
 279
 280    struct brw_program *btcp = brw_program(prog);
 281    const struct gl_linked_shader *tes =
 282       shader_prog->_LinkedShaders[MESA_SHADER_TESS_EVAL];
 283    struct brw_program *btep = tes ? brw_program(tes->Program) : NULL;
 284
 285    brw_tcs_populate_default_key(compiler, &key, shader_prog, prog);
 286
 287    success = brw_codegen_tcs_prog(brw, btcp, btep, &key);
 288
 289    brw->tcs.base.prog_offset = old_prog_offset;
 290    brw->tcs.base.prog_data = old_prog_data;
 291
 292    return success;
 293 }