src/mesa/drivers/dri/i965/brw_tcs.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 /**
  25  * \file brw_tcs.c
  26  *
  27  * Tessellation control shader state upload code.
  28  */
  29
  30 #include "brw_context.h"
  31 #include "brw_nir.h"
  32 #include "brw_program.h"
  33 #include "brw_shader.h"
  34 #include "brw_state.h"
  35 #include "program/prog_parameter.h"
  36 #include "nir_builder.h"
  37
  38 static nir_shader *
  39 create_passthrough_tcs(const struct brw_compiler *compiler,
  40                        const nir_shader_compiler_options *options,
  41                        const struct brw_tcs_prog_key *key)
  42 {
  43    nir_builder b;
  44    nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_TESS_CTRL, options);
  45    nir_shader *nir = b.shader;
  46    nir_variable *var;
  47    nir_intrinsic_instr *load;
  48    nir_intrinsic_instr *store;
  49    nir_ssa_def *zero = nir_imm_int(&b, 0);
  50    nir_ssa_def *invoc_id =
  51       nir_load_system_value(&b, nir_intrinsic_load_invocation_id, 0);
  52
  53    nir->info.inputs_read = key->outputs_written;
  54    nir->info.outputs_written = key->outputs_written;
  55    nir->info.tcs.vertices_out = key->input_vertices;
  56    nir->info.name = ralloc_strdup(nir, "passthrough");
  57    nir->num_uniforms = 8 * sizeof(uint32_t);
  58
  59    var = nir_variable_create(nir, nir_var_uniform, glsl_vec4_type(), "hdr_0");
  60    var->data.location = 0;
  61    var = nir_variable_create(nir, nir_var_uniform, glsl_vec4_type(), "hdr_1");
  62    var->data.location = 1;
  63
  64    /* Write the patch URB header. */
  65    for (int i = 0; i <= 1; i++) {
  66       load = nir_intrinsic_instr_create(nir, nir_intrinsic_load_uniform);
  67       load->num_components = 4;
  68       load->src[0] = nir_src_for_ssa(zero);
  69       nir_ssa_dest_init(&load->instr, &load->dest, 4, 32, NULL);
  70       nir_intrinsic_set_base(load, i * 4 * sizeof(uint32_t));
  71       nir_builder_instr_insert(&b, &load->instr);
  72
  73       store = nir_intrinsic_instr_create(nir, nir_intrinsic_store_output);
  74       store->num_components = 4;
  75       store->src[0] = nir_src_for_ssa(&load->dest.ssa);
  76       store->src[1] = nir_src_for_ssa(zero);
  77       nir_intrinsic_set_base(store, VARYING_SLOT_TESS_LEVEL_INNER - i);
  78       nir_intrinsic_set_write_mask(store, WRITEMASK_XYZW);
  79       nir_builder_instr_insert(&b, &store->instr);
  80    }
  81
  82    /* Copy inputs to outputs. */
  83    uint64_t varyings = key->outputs_written;
  84
  85    while (varyings != 0) {
  86       const int varying = ffsll(varyings) - 1;
  87
  88       load = nir_intrinsic_instr_create(nir,
  89                                         nir_intrinsic_load_per_vertex_input);
  90       load->num_components = 4;
  91       load->src[0] = nir_src_for_ssa(invoc_id);
  92       load->src[1] = nir_src_for_ssa(zero);
  93       nir_ssa_dest_init(&load->instr, &load->dest, 4, 32, NULL);
  94       nir_intrinsic_set_base(load, varying);
  95       nir_builder_instr_insert(&b, &load->instr);
  96
  97       store = nir_intrinsic_instr_create(nir,
  98                                          nir_intrinsic_store_per_vertex_output);
  99       store->num_components = 4;
 100       store->src[0] = nir_src_for_ssa(&load->dest.ssa);
 101       store->src[1] = nir_src_for_ssa(invoc_id);
 102       store->src[2] = nir_src_for_ssa(zero);
 103       nir_intrinsic_set_base(store, varying);
 104       nir_intrinsic_set_write_mask(store, WRITEMASK_XYZW);
 105       nir_builder_instr_insert(&b, &store->instr);
 106
 107       varyings &= ~BITFIELD64_BIT(varying);
 108    }
 109
 110    nir_validate_shader(nir);
 111
 112    nir = brw_preprocess_nir(compiler, nir);
 113
 114    return nir;
 115 }
 116
 117 static void
 118 brw_tcs_debug_recompile(struct brw_context *brw,
 119                        struct gl_shader_program *shader_prog,
 120                        const struct brw_tcs_prog_key *key)
 121 {
 122    struct brw_cache_item *c = NULL;
 123    const struct brw_tcs_prog_key *old_key = NULL;
 124    bool found = false;
 125
 126    perf_debug("Recompiling tessellation control shader for program %d\n",
 127               shader_prog->Name);
 128
 129    for (unsigned int i = 0; i < brw->cache.size; i++) {
 130       for (c = brw->cache.items[i]; c; c = c->next) {
 131          if (c->cache_id == BRW_CACHE_TCS_PROG) {
 132             old_key = c->key;
 133
 134             if (old_key->program_string_id == key->program_string_id)
 135                break;
 136          }
 137       }
 138       if (c)
 139          break;
 140    }
 141
 142    if (!c) {
 143       perf_debug("  Didn't find previous compile in the shader cache for "
 144                  "debug\n");
 145       return;
 146    }
 147
 148    found |= key_debug(brw, "input vertices", old_key->input_vertices,
 149                       key->input_vertices);
 150    found |= key_debug(brw, "outputs written", old_key->outputs_written,
 151                       key->outputs_written);
 152    found |= key_debug(brw, "patch outputs written", old_key->patch_outputs_written,
 153                       key->patch_outputs_written);
 154    found |= key_debug(brw, "TES primitive mode", old_key->tes_primitive_mode,
 155                       key->tes_primitive_mode);
 156    found |= brw_debug_recompile_sampler_key(brw, &old_key->tex, &key->tex);
 157
 158    if (!found) {
 159       perf_debug("  Something else\n");
 160    }
 161 }
 162
 163 static bool
 164 brw_codegen_tcs_prog(struct brw_context *brw,
 165                      struct gl_shader_program *shader_prog,
 166                      struct brw_tess_ctrl_program *tcp,
 167                      struct brw_tcs_prog_key *key)
 168 {
 169    struct gl_context *ctx = &brw->ctx;
 170    const struct brw_compiler *compiler = brw->intelScreen->compiler;
 171    struct brw_stage_state *stage_state = &brw->tcs.base;
 172    nir_shader *nir;
 173    struct brw_tcs_prog_data prog_data;
 174    bool start_busy = false;
 175    double start_time = 0;
 176
 177    if (tcp) {
 178       nir = tcp->program.Base.nir;
 179    } else {
 180       /* Create a dummy nir_shader.  We won't actually use NIR code to
 181        * generate assembly (it's easier to generate assembly directly),
 182        * but the whole compiler assumes one of these exists.
 183        */
 184       const nir_shader_compiler_options *options =
 185          ctx->Const.ShaderCompilerOptions[MESA_SHADER_TESS_CTRL].NirOptions;
 186       nir = create_passthrough_tcs(compiler, options, key);
 187    }
 188
 189    memset(&prog_data, 0, sizeof(prog_data));
 190
 191    /* Allocate the references to the uniforms that will end up in the
 192     * prog_data associated with the compiled program, and which will be freed
 193     * by the state cache.
 194     *
 195     * Note: param_count needs to be num_uniform_components * 4, since we add
 196     * padding around uniform values below vec4 size, so the worst case is that
 197     * every uniform is a float which gets padded to the size of a vec4.
 198     */
 199    struct gl_shader *tcs = shader_prog ?
 200       shader_prog->_LinkedShaders[MESA_SHADER_TESS_CTRL] : NULL;
 201    int param_count = nir->num_uniforms;
 202    if (!compiler->scalar_stage[MESA_SHADER_TESS_CTRL])
 203       param_count *= 4;
 204
 205    prog_data.base.base.param =
 206       rzalloc_array(NULL, const gl_constant_value *, param_count);
 207    prog_data.base.base.pull_param =
 208       rzalloc_array(NULL, const gl_constant_value *, param_count);
 209    prog_data.base.base.nr_params = param_count;
 210
 211    if (tcs) {
 212       prog_data.base.base.image_param =
 213          rzalloc_array(NULL, struct brw_image_param, tcs->NumImages);
 214       prog_data.base.base.nr_image_params = tcs->NumImages;
 215
 216       brw_nir_setup_glsl_uniforms(nir, shader_prog, &tcp->program.Base,
 217                                   &prog_data.base.base,
 218                                   compiler->scalar_stage[MESA_SHADER_TESS_CTRL]);
 219    } else {
 220       /* Upload the Patch URB Header as the first two uniforms.
 221        * Do the annoying scrambling so the shader doesn't have to.
 222        */
 223       const float **param = (const float **) prog_data.base.base.param;
 224       static float zero = 0.0f;
 225       for (int i = 0; i < 4; i++) {
 226          param[7 - i] = &ctx->TessCtrlProgram.patch_default_outer_level[i];
 227       }
 228
 229       if (key->tes_primitive_mode == GL_QUADS) {
 230          param[3] = &ctx->TessCtrlProgram.patch_default_inner_level[0];
 231          param[2] = &ctx->TessCtrlProgram.patch_default_inner_level[1];
 232          param[1] = &zero;
 233          param[0] = &zero;
 234       } else if (key->tes_primitive_mode == GL_TRIANGLES) {
 235          param[4] = &ctx->TessCtrlProgram.patch_default_inner_level[0];
 236          for (int i = 0; i < 4; i++)
 237             param[i] = &zero;
 238       }
 239    }
 240
 241    if (unlikely(INTEL_DEBUG & DEBUG_TCS) && tcs)
 242       brw_dump_ir("tessellation control", shader_prog, tcs, NULL);
 243
 244    int st_index = -1;
 245    if (unlikely(INTEL_DEBUG & DEBUG_SHADER_TIME))
 246       st_index = brw_get_shader_time_index(brw, shader_prog, NULL, ST_TCS);
 247
 248    if (unlikely(brw->perf_debug)) {
 249       start_busy = brw->batch.last_bo && drm_intel_bo_busy(brw->batch.last_bo);
 250       start_time = get_time();
 251    }
 252
 253    void *mem_ctx = ralloc_context(NULL);
 254    unsigned program_size;
 255    char *error_str;
 256    const unsigned *program =
 257       brw_compile_tcs(compiler, brw, mem_ctx, key, &prog_data, nir, st_index,
 258                       &program_size, &error_str);
 259    if (program == NULL) {
 260       if (shader_prog) {
 261          shader_prog->LinkStatus = false;
 262          ralloc_strcat(&shader_prog->InfoLog, error_str);
 263       } else {
 264          ralloc_free(nir);
 265       }
 266
 267       _mesa_problem(NULL, "Failed to compile tessellation control shader: "
 268                     "%s\n", error_str);
 269
 270       ralloc_free(mem_ctx);
 271       return false;
 272    }
 273
 274    if (unlikely(brw->perf_debug)) {
 275       struct brw_shader *btcs = (struct brw_shader *) tcs;
 276       if (btcs->compiled_once) {
 277          brw_tcs_debug_recompile(brw, shader_prog, key);
 278       }
 279       if (start_busy && !drm_intel_bo_busy(brw->batch.last_bo)) {
 280          perf_debug("TCS compile took %.03f ms and stalled the GPU\n",
 281                     (get_time() - start_time) * 1000);
 282       }
 283       btcs->compiled_once = true;
 284    }
 285
 286    /* Scratch space is used for register spilling */
 287    if (prog_data.base.base.total_scratch) {
 288       brw_get_scratch_bo(brw, &stage_state->scratch_bo,
 289                          prog_data.base.base.total_scratch *
 290                          brw->max_hs_threads);
 291    }
 292
 293    brw_upload_cache(&brw->cache, BRW_CACHE_TCS_PROG,
 294                     key, sizeof(*key),
 295                     program, program_size,
 296                     &prog_data, sizeof(prog_data),
 297                     &stage_state->prog_offset, &brw->tcs.prog_data);
 298    ralloc_free(mem_ctx);
 299    if (!tcs)
 300       ralloc_free(nir);
 301
 302    return true;
 303 }
 304
 305
 306 void
 307 brw_upload_tcs_prog(struct brw_context *brw,
 308                     uint64_t per_vertex_slots,
 309                     uint32_t per_patch_slots)
 310 {
 311    struct gl_context *ctx = &brw->ctx;
 312    struct gl_shader_program **current = ctx->_Shader->CurrentProgram;
 313    struct brw_stage_state *stage_state = &brw->tcs.base;
 314    struct brw_tcs_prog_key key;
 315    /* BRW_NEW_TESS_PROGRAMS */
 316    struct brw_tess_ctrl_program *tcp =
 317       (struct brw_tess_ctrl_program *) brw->tess_ctrl_program;
 318    struct brw_tess_eval_program *tep =
 319       (struct brw_tess_eval_program *) brw->tess_eval_program;
 320    assert(tep);
 321
 322    if (!brw_state_dirty(brw,
 323                         _NEW_TEXTURE,
 324                         BRW_NEW_PATCH_PRIMITIVE |
 325                         BRW_NEW_TESS_PROGRAMS))
 326       return;
 327
 328    struct gl_program *prog = &tcp->program.Base;
 329
 330    memset(&key, 0, sizeof(key));
 331
 332    key.input_vertices = ctx->TessCtrlProgram.patch_vertices;
 333    key.outputs_written = per_vertex_slots;
 334    key.patch_outputs_written = per_patch_slots;
 335
 336    /* We need to specialize our code generation for tessellation levels
 337     * based on the domain the DS is expecting to tessellate.
 338     */
 339    key.tes_primitive_mode = tep->program.PrimitiveMode;
 340
 341    if (tcp) {
 342       key.program_string_id = tcp->id;
 343
 344       /* _NEW_TEXTURE */
 345       brw_populate_sampler_prog_key_data(ctx, prog, stage_state->sampler_count,
 346                                          &key.tex);
 347    } else {
 348       key.outputs_written = tep->program.Base.InputsRead;
 349    }
 350
 351
 352    if (!brw_search_cache(&brw->cache, BRW_CACHE_TCS_PROG,
 353                          &key, sizeof(key),
 354                          &stage_state->prog_offset, &brw->tcs.prog_data)) {
 355       bool success = brw_codegen_tcs_prog(brw, current[MESA_SHADER_TESS_CTRL],
 356                                           tcp, &key);
 357       assert(success);
 358       (void)success;
 359    }
 360    brw->tcs.base.prog_data = &brw->tcs.prog_data->base.base;
 361 }
 362
 363
 364 bool
 365 brw_tcs_precompile(struct gl_context *ctx,
 366                    struct gl_shader_program *shader_prog,
 367                    struct gl_program *prog)
 368 {
 369    struct brw_context *brw = brw_context(ctx);
 370    struct brw_tcs_prog_key key;
 371    uint32_t old_prog_offset = brw->tcs.base.prog_offset;
 372    struct brw_tcs_prog_data *old_prog_data = brw->tcs.prog_data;
 373    bool success;
 374
 375    struct gl_tess_ctrl_program *tcp = (struct gl_tess_ctrl_program *)prog;
 376    struct brw_tess_ctrl_program *btcp = brw_tess_ctrl_program(tcp);
 377
 378    memset(&key, 0, sizeof(key));
 379
 380    key.program_string_id = btcp->id;
 381    brw_setup_tex_for_precompile(brw, &key.tex, prog);
 382
 383    /* Guess that the input and output patches have the same dimensionality. */
 384    key.input_vertices = shader_prog->TessCtrl.VerticesOut;
 385
 386    key.tes_primitive_mode =
 387       shader_prog->_LinkedShaders[MESA_SHADER_TESS_EVAL] ?
 388       shader_prog->TessEval.PrimitiveMode : GL_TRIANGLES;
 389
 390    key.outputs_written = prog->OutputsWritten;
 391    key.patch_outputs_written = prog->PatchOutputsWritten;
 392
 393    success = brw_codegen_tcs_prog(brw, shader_prog, btcp, &key);
 394
 395    brw->tcs.base.prog_offset = old_prog_offset;
 396    brw->tcs.prog_data = old_prog_data;
 397
 398    return success;
 399 }