2 * Copyright 2006 VMware, Inc.
3 * Copyright © 2006 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial
15 * portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 * \file brw_tex_layout.cpp
29 * Code to lay out images in a mipmap tree.
31 * \author Keith Whitwell <keithw@vmware.com>
32 * \author Michel Dänzer <daenzer@vmware.com>
35 #include "intel_mipmap_tree.h"
36 #include "brw_context.h"
37 #include "main/macros.h"
38 #include "main/glformats.h"
40 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
43 tr_mode_horizontal_texture_alignment(const struct brw_context
*brw
,
44 const struct intel_mipmap_tree
*mt
)
46 const unsigned *align_yf
, *align_ys
;
47 const unsigned bpp
= _mesa_get_format_bytes(mt
->format
) * 8;
48 unsigned ret_align
, divisor
;
50 /* Horizontal alignment tables for TRMODE_{YF,YS}. Value in below
51 * tables specifies the horizontal alignment requirement in elements
52 * for the surface. An element is defined as a pixel in uncompressed
53 * surface formats, and as a compression block in compressed surface
54 * formats. For MSFMT_DEPTH_STENCIL type multisampled surfaces, an
55 * element is a sample.
57 const unsigned align_1d_yf
[] = {4096, 2048, 1024, 512, 256};
58 const unsigned align_1d_ys
[] = {65536, 32768, 16384, 8192, 4096};
59 const unsigned align_2d_yf
[] = {64, 64, 32, 32, 16};
60 const unsigned align_2d_ys
[] = {256, 256, 128, 128, 64};
61 const unsigned align_3d_yf
[] = {16, 8, 8, 8, 4};
62 const unsigned align_3d_ys
[] = {64, 32, 32, 32, 16};
65 /* Alignment computations below assume bpp >= 8 and a power of 2. */
66 assert (bpp
>= 8 && bpp
<= 128 && _mesa_is_pow_two(bpp
));
70 case GL_TEXTURE_1D_ARRAY
:
71 align_yf
= align_1d_yf
;
72 align_ys
= align_1d_ys
;
75 case GL_TEXTURE_RECTANGLE
:
76 case GL_TEXTURE_2D_ARRAY
:
77 case GL_TEXTURE_CUBE_MAP
:
78 case GL_TEXTURE_CUBE_MAP_ARRAY
:
79 case GL_TEXTURE_2D_MULTISAMPLE
:
80 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
81 align_yf
= align_2d_yf
;
82 align_ys
= align_2d_ys
;
85 align_yf
= align_3d_yf
;
86 align_ys
= align_3d_ys
;
89 unreachable("not reached");
92 /* Compute array index. */
95 ret_align
= mt
->tr_mode
== INTEL_MIPTREE_TRMODE_YF
?
96 align_yf
[i
] : align_ys
[i
];
98 assert(_mesa_is_pow_two(mt
->num_samples
));
100 switch (mt
->num_samples
) {
113 return ret_align
/ divisor
;
118 intel_horizontal_texture_alignment_unit(struct brw_context
*brw
,
119 struct intel_mipmap_tree
*mt
,
120 uint32_t layout_flags
)
122 if (layout_flags
& MIPTREE_LAYOUT_FORCE_HALIGN16
)
126 * +----------------------------------------------------------------------+
127 * | | alignment unit width ("i") |
128 * | Surface Property |-----------------------------|
129 * | | 915 | 965 | ILK | SNB | IVB |
130 * +----------------------------------------------------------------------+
131 * | YUV 4:2:2 format | 8 | 4 | 4 | 4 | 4 |
132 * | BC1-5 compressed format (DXTn/S3TC) | 4 | 4 | 4 | 4 | 4 |
133 * | FXT1 compressed format | 8 | 8 | 8 | 8 | 8 |
134 * | Depth Buffer (16-bit) | 4 | 4 | 4 | 4 | 8 |
135 * | Depth Buffer (other) | 4 | 4 | 4 | 4 | 4 |
136 * | Separate Stencil Buffer | N/A | N/A | 8 | 8 | 8 |
137 * | All Others | 4 | 4 | 4 | 4 | 4 |
138 * +----------------------------------------------------------------------+
140 * On IVB+, non-special cases can be overridden by setting the SURFACE_STATE
141 * "Surface Horizontal Alignment" field to HALIGN_4 or HALIGN_8.
144 if (brw
->gen
>= 7 && mt
->format
== MESA_FORMAT_Z_UNORM16
)
151 tr_mode_vertical_texture_alignment(const struct brw_context
*brw
,
152 const struct intel_mipmap_tree
*mt
)
154 const unsigned *align_yf
, *align_ys
;
155 const unsigned bpp
= _mesa_get_format_bytes(mt
->format
) * 8;
156 unsigned ret_align
, divisor
;
158 /* Vertical alignment tables for TRMODE_YF and TRMODE_YS. */
159 const unsigned align_2d_yf
[] = {64, 32, 32, 16, 16};
160 const unsigned align_2d_ys
[] = {256, 128, 128, 64, 64};
161 const unsigned align_3d_yf
[] = {16, 16, 16, 8, 8};
162 const unsigned align_3d_ys
[] = {32, 32, 32, 16, 16};
165 assert(brw
->gen
>= 9 &&
166 mt
->target
!= GL_TEXTURE_1D
&&
167 mt
->target
!= GL_TEXTURE_1D_ARRAY
);
169 /* Alignment computations below assume bpp >= 8 and a power of 2. */
170 assert (bpp
>= 8 && bpp
<= 128 && _mesa_is_pow_two(bpp
)) ;
174 case GL_TEXTURE_RECTANGLE
:
175 case GL_TEXTURE_2D_ARRAY
:
176 case GL_TEXTURE_CUBE_MAP
:
177 case GL_TEXTURE_CUBE_MAP_ARRAY
:
178 case GL_TEXTURE_2D_MULTISAMPLE
:
179 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
180 align_yf
= align_2d_yf
;
181 align_ys
= align_2d_ys
;
184 align_yf
= align_3d_yf
;
185 align_ys
= align_3d_ys
;
188 unreachable("not reached");
191 /* Compute array index. */
192 i
= ffs(bpp
/ 8) - 1;
194 ret_align
= mt
->tr_mode
== INTEL_MIPTREE_TRMODE_YF
?
195 align_yf
[i
] : align_ys
[i
];
197 assert(_mesa_is_pow_two(mt
->num_samples
));
199 switch (mt
->num_samples
) {
211 return ret_align
/ divisor
;
215 intel_vertical_texture_alignment_unit(struct brw_context
*brw
,
216 const struct intel_mipmap_tree
*mt
)
219 * +----------------------------------------------------------------------+
220 * | | alignment unit height ("j") |
221 * | Surface Property |-----------------------------|
222 * | | 915 | 965 | ILK | SNB | IVB |
223 * +----------------------------------------------------------------------+
224 * | BC1-5 compressed format (DXTn/S3TC) | 4 | 4 | 4 | 4 | 4 |
225 * | FXT1 compressed format | 4 | 4 | 4 | 4 | 4 |
226 * | Depth Buffer | 2 | 2 | 2 | 4 | 4 |
227 * | Separate Stencil Buffer | N/A | N/A | N/A | 4 | 8 |
228 * | Multisampled (4x or 8x) render target | N/A | N/A | N/A | 4 | 4 |
229 * | All Others | 2 | 2 | 2 | * | * |
230 * +----------------------------------------------------------------------+
232 * Where "*" means either VALIGN_2 or VALIGN_4 depending on the setting of
233 * the SURFACE_STATE "Surface Vertical Alignment" field.
236 /* Broadwell only supports VALIGN of 4, 8, and 16. The BSpec says 4
237 * should always be used, except for stencil buffers, which should be 8.
242 if (mt
->num_samples
> 1)
245 GLenum base_format
= _mesa_get_format_base_format(mt
->format
);
248 (base_format
== GL_DEPTH_COMPONENT
||
249 base_format
== GL_DEPTH_STENCIL
)) {
254 /* On Gen7, we prefer a vertical alignment of 4 when possible, because
255 * that allows Y tiled render targets.
257 * From the Ivy Bridge PRM, Vol4 Part1 2.12.2.1 (SURFACE_STATE for most
258 * messages), on p64, under the heading "Surface Vertical Alignment":
260 * Value of 1 [VALIGN_4] is not supported for format YCRCB_NORMAL
261 * (0x182), YCRCB_SWAPUVY (0x183), YCRCB_SWAPUV (0x18f), YCRCB_SWAPY
264 * VALIGN_4 is not supported for surface format R32G32B32_FLOAT.
266 if (base_format
== GL_YCBCR_MESA
|| mt
->format
== MESA_FORMAT_RGB_FLOAT32
)
276 gen9_miptree_layout_1d(struct intel_mipmap_tree
*mt
)
279 unsigned width
= mt
->physical_width0
;
280 unsigned depth
= mt
->physical_depth0
; /* number of array layers. */
282 /* When this layout is used the horizontal alignment is fixed at 64 and the
283 * hardware ignores the value given in the surface state
285 const unsigned int halign
= 64;
287 mt
->total_height
= mt
->physical_height0
;
290 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; level
++) {
293 intel_miptree_set_level_info(mt
, level
, x
, 0, depth
);
295 img_width
= ALIGN(width
, halign
);
297 mt
->total_width
= MAX2(mt
->total_width
, x
+ img_width
);
301 width
= minify(width
, 1);
306 brw_miptree_layout_2d(struct intel_mipmap_tree
*mt
)
310 unsigned width
= mt
->physical_width0
;
311 unsigned height
= mt
->physical_height0
;
312 unsigned depth
= mt
->physical_depth0
; /* number of array layers. */
315 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
317 mt
->total_width
= mt
->physical_width0
;
320 mt
->total_width
= ALIGN_NPOT(mt
->total_width
, bw
);
322 /* May need to adjust width to accommodate the placement of
323 * the 2nd mipmap. This occurs when the alignment
324 * constraints of mipmap placement push the right edge of the
325 * 2nd mipmap out past the width of its parent.
327 if (mt
->first_level
!= mt
->last_level
) {
330 if (mt
->compressed
) {
331 mip1_width
= ALIGN_NPOT(minify(mt
->physical_width0
, 1), mt
->halign
) +
332 ALIGN_NPOT(minify(mt
->physical_width0
, 2), bw
);
334 mip1_width
= ALIGN_NPOT(minify(mt
->physical_width0
, 1), mt
->halign
) +
335 minify(mt
->physical_width0
, 2);
338 if (mip1_width
> mt
->total_width
) {
339 mt
->total_width
= mip1_width
;
343 mt
->total_width
/= bw
;
344 mt
->total_height
= 0;
346 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; level
++) {
349 intel_miptree_set_level_info(mt
, level
, x
, y
, depth
);
351 img_height
= ALIGN_NPOT(height
, mt
->valign
);
355 if (mt
->array_layout
== ALL_SLICES_AT_EACH_LOD
) {
356 /* Compact arrays with separated miplevels */
360 /* Because the images are packed better, the final offset
361 * might not be the maximal one:
363 mt
->total_height
= MAX2(mt
->total_height
, y
+ img_height
);
365 /* Layout_below: step right after second mipmap.
367 if (level
== mt
->first_level
+ 1) {
368 x
+= ALIGN_NPOT(width
, mt
->halign
) / bw
;
373 width
= minify(width
, 1);
374 height
= minify(height
, 1);
376 if (mt
->target
== GL_TEXTURE_3D
)
377 depth
= minify(depth
, 1);
382 brw_miptree_get_horizontal_slice_pitch(const struct brw_context
*brw
,
383 const struct intel_mipmap_tree
*mt
,
386 if ((brw
->gen
< 9 && mt
->target
== GL_TEXTURE_3D
) ||
387 (brw
->gen
== 4 && mt
->target
== GL_TEXTURE_CUBE_MAP
)) {
388 return ALIGN_NPOT(minify(mt
->physical_width0
, level
), mt
->halign
);
395 brw_miptree_get_vertical_slice_pitch(const struct brw_context
*brw
,
396 const struct intel_mipmap_tree
*mt
,
400 /* ALL_SLICES_AT_EACH_LOD isn't supported on Gen8+ but this code will
401 * effectively end up with a packed qpitch anyway whenever
402 * mt->first_level == mt->last_level.
404 assert(mt
->array_layout
!= ALL_SLICES_AT_EACH_LOD
);
406 /* On Gen9 we can pick whatever qpitch we like as long as it's aligned
407 * to the vertical alignment so we don't need to add any extra rows.
409 unsigned qpitch
= mt
->total_height
;
411 /* If the surface might be used as a stencil buffer or HiZ buffer then
412 * it needs to be a multiple of 8.
414 const GLenum base_format
= _mesa_get_format_base_format(mt
->format
);
415 if (_mesa_is_depth_or_stencil_format(base_format
))
416 qpitch
= ALIGN(qpitch
, 8);
418 /* 3D textures need to be aligned to the tile height. At this point we
419 * don't know which tiling will be used so let's just align it to 32
421 if (mt
->target
== GL_TEXTURE_3D
)
422 qpitch
= ALIGN(qpitch
, 32);
426 } else if (mt
->target
== GL_TEXTURE_3D
||
427 (brw
->gen
== 4 && mt
->target
== GL_TEXTURE_CUBE_MAP
) ||
428 mt
->array_layout
== ALL_SLICES_AT_EACH_LOD
) {
429 return ALIGN_NPOT(minify(mt
->physical_height0
, level
), mt
->valign
);
432 const unsigned h0
= ALIGN_NPOT(mt
->physical_height0
, mt
->valign
);
433 const unsigned h1
= ALIGN_NPOT(minify(mt
->physical_height0
, 1), mt
->valign
);
435 return h0
+ h1
+ (brw
->gen
>= 7 ? 12 : 11) * mt
->valign
;
440 align_cube(struct intel_mipmap_tree
*mt
)
442 /* The 965's sampler lays cachelines out according to how accesses
443 * in the texture surfaces run, so they may be "vertical" through
444 * memory. As a result, the docs say in Surface Padding Requirements:
445 * Sampling Engine Surfaces that two extra rows of padding are required.
447 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
448 mt
->total_height
+= 2;
452 gen9_use_linear_1d_layout(const struct brw_context
*brw
,
453 const struct intel_mipmap_tree
*mt
)
455 /* On Gen9+ the mipmap levels of a 1D surface are all laid out in a
456 * horizontal line. This isn't done for depth/stencil buffers however
457 * because those will be using a tiled layout
460 (mt
->target
== GL_TEXTURE_1D
||
461 mt
->target
== GL_TEXTURE_1D_ARRAY
)) {
462 GLenum base_format
= _mesa_get_format_base_format(mt
->format
);
464 if (base_format
!= GL_DEPTH_COMPONENT
&&
465 base_format
!= GL_DEPTH_STENCIL
&&
466 base_format
!= GL_STENCIL_INDEX
)
474 brw_miptree_layout_texture_array(struct brw_context
*brw
,
475 struct intel_mipmap_tree
*mt
)
477 unsigned height
= mt
->physical_height0
;
478 bool layout_1d
= gen9_use_linear_1d_layout(brw
, mt
);
482 gen9_miptree_layout_1d(mt
);
484 brw_miptree_layout_2d(mt
);
488 /* When using the horizontal layout the qpitch specifies the distance in
489 * pixels between array slices. The total_width is forced to be a
490 * multiple of the horizontal alignment in brw_miptree_layout_1d (in
491 * this case it's always 64). The vertical alignment is ignored.
493 mt
->qpitch
= mt
->total_width
;
495 mt
->qpitch
= brw_miptree_get_vertical_slice_pitch(brw
, mt
, 0);
496 /* Unlike previous generations the qpitch is a multiple of the
497 * compressed block size on Gen9 so physical_qpitch matches mt->qpitch.
499 physical_qpitch
= (mt
->compressed
&& brw
->gen
< 9 ? mt
->qpitch
/ 4 :
503 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; level
++) {
505 img_height
= ALIGN_NPOT(height
, mt
->valign
);
507 img_height
/= mt
->valign
;
509 for (unsigned q
= 0; q
< mt
->level
[level
].depth
; q
++) {
510 if (mt
->array_layout
== ALL_SLICES_AT_EACH_LOD
) {
511 intel_miptree_set_image_offset(mt
, level
, q
, 0, q
* img_height
);
513 intel_miptree_set_image_offset(mt
, level
, q
, 0, q
* physical_qpitch
);
516 height
= minify(height
, 1);
518 if (mt
->array_layout
== ALL_LOD_IN_EACH_SLICE
)
519 mt
->total_height
= physical_qpitch
* mt
->physical_depth0
;
525 brw_miptree_layout_texture_3d(struct brw_context
*brw
,
526 struct intel_mipmap_tree
*mt
)
529 mt
->total_height
= 0;
534 _mesa_get_format_block_size(mt
->format
, &bw
, &bh
);
536 for (unsigned level
= mt
->first_level
; level
<= mt
->last_level
; level
++) {
537 unsigned WL
= MAX2(mt
->physical_width0
>> level
, 1);
538 unsigned HL
= MAX2(mt
->physical_height0
>> level
, 1);
539 unsigned DL
= MAX2(mt
->physical_depth0
>> level
, 1);
540 unsigned wL
= ALIGN_NPOT(WL
, mt
->halign
);
541 unsigned hL
= ALIGN_NPOT(HL
, mt
->valign
);
543 if (mt
->target
== GL_TEXTURE_CUBE_MAP
)
546 intel_miptree_set_level_info(mt
, level
, 0, 0, DL
);
548 for (unsigned q
= 0; q
< DL
; q
++) {
549 unsigned x
= (q
% (1 << level
)) * wL
;
550 unsigned y
= ysum
+ (q
>> level
) * hL
;
552 intel_miptree_set_image_offset(mt
, level
, q
, x
/ bw
, y
/ bh
);
553 mt
->total_width
= MAX2(mt
->total_width
, (x
+ wL
) / bw
);
554 mt
->total_height
= MAX2(mt
->total_height
, (y
+ hL
) / bh
);
557 ysum
+= ALIGN(DL
, 1 << level
) / (1 << level
) * hL
;
564 * \brief Helper function for intel_miptree_create().
567 brw_miptree_choose_tiling(struct brw_context
*brw
,
568 const struct intel_mipmap_tree
*mt
,
569 uint32_t layout_flags
)
571 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
572 /* The stencil buffer is W tiled. However, we request from the kernel a
573 * non-tiled buffer because the GTT is incapable of W fencing.
575 return I915_TILING_NONE
;
578 /* Do not support changing the tiling for miptrees with pre-allocated BOs. */
579 assert((layout_flags
& MIPTREE_LAYOUT_FOR_BO
) == 0);
581 /* Some usages may want only one type of tiling, like depth miptrees (Y
582 * tiled), or temporary BOs for uploading data once (linear).
584 switch (layout_flags
& MIPTREE_LAYOUT_TILING_ANY
) {
585 case MIPTREE_LAYOUT_TILING_ANY
:
587 case MIPTREE_LAYOUT_TILING_Y
:
588 return I915_TILING_Y
;
589 case MIPTREE_LAYOUT_TILING_NONE
:
590 return I915_TILING_NONE
;
593 if (mt
->num_samples
> 1) {
594 /* From p82 of the Sandy Bridge PRM, dw3[1] of SURFACE_STATE ("Tiled
597 * [DevSNB+]: For multi-sample render targets, this field must be
598 * 1. MSRTs can only be tiled.
600 * Our usual reason for preferring X tiling (fast blits using the
601 * blitting engine) doesn't apply to MSAA, since we'll generally be
602 * downsampling or upsampling when blitting between the MSAA buffer
603 * and another buffer, and the blitting engine doesn't support that.
604 * So use Y tiling, since it makes better use of the cache.
606 return I915_TILING_Y
;
609 GLenum base_format
= _mesa_get_format_base_format(mt
->format
);
610 if (base_format
== GL_DEPTH_COMPONENT
||
611 base_format
== GL_DEPTH_STENCIL_EXT
)
612 return I915_TILING_Y
;
614 /* 1D textures (and 1D array textures) don't get any benefit from tiling,
615 * in fact it leads to a less efficient use of memory space and bandwidth
616 * due to tile alignment.
618 if (mt
->logical_height0
== 1)
619 return I915_TILING_NONE
;
621 int minimum_pitch
= mt
->total_width
* mt
->cpp
;
623 /* If the width is much smaller than a tile, don't bother tiling. */
624 if (minimum_pitch
< 64)
625 return I915_TILING_NONE
;
627 if (ALIGN(minimum_pitch
, 512) >= 32768 ||
628 mt
->total_width
>= 32768 || mt
->total_height
>= 32768) {
629 perf_debug("%dx%d miptree too large to blit, falling back to untiled",
630 mt
->total_width
, mt
->total_height
);
631 return I915_TILING_NONE
;
634 /* Pre-gen6 doesn't have BLORP to handle Y-tiling, so use X-tiling. */
636 return I915_TILING_X
;
638 /* From the Sandybridge PRM, Volume 1, Part 2, page 32:
639 * "NOTE: 128BPE Format Color Buffer ( render target ) MUST be either TileX
641 * 128 bits per pixel translates to 16 bytes per pixel. This is necessary
642 * all the way back to 965, but is permitted on Gen7+.
644 if (brw
->gen
< 7 && mt
->cpp
>= 16)
645 return I915_TILING_X
;
647 /* From the Ivy Bridge PRM, Vol4 Part1 2.12.2.1 (SURFACE_STATE for most
648 * messages), on p64, under the heading "Surface Vertical Alignment":
650 * This field must be set to VALIGN_4 for all tiled Y Render Target
653 * So if the surface is renderable and uses a vertical alignment of 2,
654 * force it to be X tiled. This is somewhat conservative (it's possible
655 * that the client won't ever render to this surface), but it's difficult
656 * to know that ahead of time. And besides, since we use a vertical
657 * alignment of 4 as often as we can, this shouldn't happen very often.
659 if (brw
->gen
== 7 && mt
->valign
== 2 &&
660 brw
->format_supported_as_render_target
[mt
->format
]) {
661 return I915_TILING_X
;
664 return I915_TILING_Y
| I915_TILING_X
;
668 intel_miptree_set_total_width_height(struct brw_context
*brw
,
669 struct intel_mipmap_tree
*mt
)
671 switch (mt
->target
) {
672 case GL_TEXTURE_CUBE_MAP
:
674 /* Gen4 stores cube maps as 3D textures. */
675 assert(mt
->physical_depth0
== 6);
676 brw_miptree_layout_texture_3d(brw
, mt
);
678 /* All other hardware stores cube maps as 2D arrays. */
679 brw_miptree_layout_texture_array(brw
, mt
);
685 brw_miptree_layout_texture_array(brw
, mt
);
687 brw_miptree_layout_texture_3d(brw
, mt
);
690 case GL_TEXTURE_1D_ARRAY
:
691 case GL_TEXTURE_2D_ARRAY
:
692 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
693 case GL_TEXTURE_CUBE_MAP_ARRAY
:
694 brw_miptree_layout_texture_array(brw
, mt
);
698 switch (mt
->msaa_layout
) {
699 case INTEL_MSAA_LAYOUT_UMS
:
700 case INTEL_MSAA_LAYOUT_CMS
:
701 brw_miptree_layout_texture_array(brw
, mt
);
703 case INTEL_MSAA_LAYOUT_NONE
:
704 case INTEL_MSAA_LAYOUT_IMS
:
705 if (gen9_use_linear_1d_layout(brw
, mt
))
706 gen9_miptree_layout_1d(mt
);
708 brw_miptree_layout_2d(mt
);
714 DBG("%s: %dx%dx%d\n", __func__
,
715 mt
->total_width
, mt
->total_height
, mt
->cpp
);
719 intel_miptree_set_alignment(struct brw_context
*brw
,
720 struct intel_mipmap_tree
*mt
,
721 uint32_t layout_flags
)
724 * From the "Alignment Unit Size" section of various specs, namely:
725 * - Gen3 Spec: "Memory Data Formats" Volume, Section 1.20.1.4
726 * - i965 and G45 PRMs: Volume 1, Section 6.17.3.4.
727 * - Ironlake and Sandybridge PRMs: Volume 1, Part 1, Section 7.18.3.4
728 * - BSpec (for Ivybridge and slight variations in separate stencil)
730 bool gen6_hiz_or_stencil
= false;
732 if (brw
->gen
== 6 && mt
->array_layout
== ALL_SLICES_AT_EACH_LOD
) {
733 const GLenum base_format
= _mesa_get_format_base_format(mt
->format
);
734 gen6_hiz_or_stencil
= _mesa_is_depth_or_stencil_format(base_format
);
737 if (gen6_hiz_or_stencil
) {
738 /* On gen6, we use ALL_SLICES_AT_EACH_LOD for stencil/hiz because the
739 * hardware doesn't support multiple mip levels on stencil/hiz.
741 * PRM Vol 2, Part 1, 7.5.3 Hierarchical Depth Buffer:
742 * "The hierarchical depth buffer does not support the LOD field"
744 * PRM Vol 2, Part 1, 7.5.4.1 Separate Stencil Buffer:
745 * "The stencil depth buffer does not support the LOD field"
747 if (mt
->format
== MESA_FORMAT_S_UINT8
) {
748 /* Stencil uses W tiling, so we force W tiling alignment for the
749 * ALL_SLICES_AT_EACH_LOD miptree layout.
753 assert((layout_flags
& MIPTREE_LAYOUT_FORCE_HALIGN16
) == 0);
755 /* Depth uses Y tiling, so we force need Y tiling alignment for the
756 * ALL_SLICES_AT_EACH_LOD miptree layout.
758 mt
->halign
= 128 / mt
->cpp
;
761 } else if (mt
->compressed
) {
762 /* The hardware alignment requirements for compressed textures
763 * happen to match the block boundaries.
765 _mesa_get_format_block_size(mt
->format
, &mt
->halign
, &mt
->valign
);
767 /* On Gen9+ we can pick our own alignment for compressed textures but it
768 * has to be a multiple of the block size. The minimum alignment we can
769 * pick is 4 so we effectively have to align to 4 times the block
776 } else if (mt
->format
== MESA_FORMAT_S_UINT8
) {
778 mt
->valign
= brw
->gen
>= 7 ? 8 : 4;
779 } else if (brw
->gen
>= 9 && mt
->tr_mode
!= INTEL_MIPTREE_TRMODE_NONE
) {
780 /* XY_FAST_COPY_BLT doesn't support horizontal alignment < 32 or
781 * vertical alignment < 64. */
782 mt
->halign
= MAX2(tr_mode_horizontal_texture_alignment(brw
, mt
), 32);
783 mt
->valign
= MAX2(tr_mode_vertical_texture_alignment(brw
, mt
), 64);
786 intel_horizontal_texture_alignment_unit(brw
, mt
, layout_flags
);
787 mt
->valign
= intel_vertical_texture_alignment_unit(brw
, mt
);
792 brw_miptree_layout(struct brw_context
*brw
,
793 struct intel_mipmap_tree
*mt
,
794 uint32_t layout_flags
)
796 mt
->tr_mode
= INTEL_MIPTREE_TRMODE_NONE
;
798 intel_miptree_set_alignment(brw
, mt
, layout_flags
);
799 intel_miptree_set_total_width_height(brw
, mt
);
801 if (!mt
->total_width
|| !mt
->total_height
) {
802 intel_miptree_release(&mt
);
806 /* On Gen9+ the alignment values are expressed in multiples of the block
811 _mesa_get_format_block_size(mt
->format
, &i
, &j
);
816 if ((layout_flags
& MIPTREE_LAYOUT_FOR_BO
) == 0)
817 mt
->tiling
= brw_miptree_choose_tiling(brw
, mt
, layout_flags
);