src/mesa/drivers/dri/i965/brw_tex_layout.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32 /* Code to layout images in a mipmap tree for i965.
  33  */
  34
  35 #include "intel_mipmap_tree.h"
  36 #include "intel_tex_layout.h"
  37 #include "intel_context.h"
  38 #include "main/macros.h"
  39
  40 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
  41
  42 GLboolean brw_miptree_layout(struct intel_context *intel,
  43                              struct intel_mipmap_tree *mt,
  44                              uint32_t tiling)
  45 {
  46    /* XXX: these vary depending on image format: */
  47    /* GLint align_w = 4; */
  48
  49    switch (mt->target) {
  50    case GL_TEXTURE_CUBE_MAP:
  51       if (intel->gen == 5) {
  52           GLuint align_h = 2;
  53           GLuint level;
  54           GLuint qpitch = 0;
  55           int h0, h1, q;
  56
  57           /* On Ironlake, cube maps are finally represented as just a series
  58            * of MIPLAYOUT_BELOW 2D textures (like 2D texture arrays), separated
  59            * by a pitch of qpitch rows, where qpitch is defined by the equation
  60            * given in Volume 1 of the BSpec.
  61            */
  62           h0 = ALIGN(mt->height0, align_h);
  63           h1 = ALIGN(minify(h0), align_h);
  64           qpitch = (h0 + h1 + 11 * align_h);
  65           if (mt->compressed)
  66              qpitch /= 4;
  67
  68           i945_miptree_layout_2d(intel, mt, tiling, 6);
  69
  70           for (level = mt->first_level; level <= mt->last_level; level++) {
  71              for (q = 0; q < 6; q++) {
  72                 intel_miptree_set_image_offset(mt, level, q, 0, q * qpitch);
  73              }
  74           }
  75           mt->total_height = qpitch * 6;
  76
  77           break;
  78       }
  79
  80    case GL_TEXTURE_3D: {
  81       GLuint width  = mt->width0;
  82       GLuint height = mt->height0;
  83       GLuint depth = mt->depth0;
  84       GLuint pack_x_pitch, pack_x_nr;
  85       GLuint pack_y_pitch;
  86       GLuint level;
  87       GLuint align_h = 2;
  88       GLuint align_w = 4;
  89
  90       mt->total_height = 0;
  91       intel_get_texture_alignment_unit(mt->internal_format, &align_w, &align_h);
  92
  93       if (mt->compressed) {
  94           mt->total_width = ALIGN(width, align_w);
  95           pack_y_pitch = (height + 3) / 4;
  96       } else {
  97          mt->total_width = mt->width0;
  98          pack_y_pitch = ALIGN(mt->height0, align_h);
  99       }
 100
 101       pack_x_pitch = width;
 102       pack_x_nr = 1;
 103
 104       for (level = mt->first_level ; level <= mt->last_level ; level++) {
 105          GLuint nr_images = mt->target == GL_TEXTURE_3D ? depth : 6;
 106          GLint x = 0;
 107          GLint y = 0;
 108          GLint q, j;
 109
 110          intel_miptree_set_level_info(mt, level, nr_images,
 111                                       0, mt->total_height,
 112                                       width, height, depth);
 113
 114          for (q = 0; q < nr_images;) {
 115             for (j = 0; j < pack_x_nr && q < nr_images; j++, q++) {
 116                intel_miptree_set_image_offset(mt, level, q, x, y);
 117                x += pack_x_pitch;
 118             }
 119
 120             x = 0;
 121             y += pack_y_pitch;
 122          }
 123
 124
 125          mt->total_height += y;
 126          width  = minify(width);
 127          height = minify(height);
 128          depth  = minify(depth);
 129
 130          if (mt->compressed) {
 131             pack_y_pitch = (height + 3) / 4;
 132
 133             if (pack_x_pitch > ALIGN(width, align_w)) {
 134                pack_x_pitch = ALIGN(width, align_w);
 135                pack_x_nr <<= 1;
 136             }
 137          } else {
 138             if (pack_x_pitch > 4) {
 139                pack_x_pitch >>= 1;
 140                pack_x_nr <<= 1;
 141                assert(pack_x_pitch * pack_x_nr <= mt->total_width);
 142             }
 143
 144             if (pack_y_pitch > 2) {
 145                pack_y_pitch >>= 1;
 146                pack_y_pitch = ALIGN(pack_y_pitch, align_h);
 147             }
 148          }
 149
 150       }
 151       /* The 965's sampler lays cachelines out according to how accesses
 152        * in the texture surfaces run, so they may be "vertical" through
 153        * memory.  As a result, the docs say in Surface Padding Requirements:
 154        * Sampling Engine Surfaces that two extra rows of padding are required.
 155        * We don't know of similar requirements for pre-965, but given that
 156        * those docs are silent on padding requirements in general, let's play
 157        * it safe.
 158        */
 159       if (mt->target == GL_TEXTURE_CUBE_MAP)
 160          mt->total_height += 2;
 161       break;
 162    }
 163
 164    default:
 165       i945_miptree_layout_2d(intel, mt, tiling, 1);
 166       break;
 167    }
 168    DBG("%s: %dx%dx%d\n", __FUNCTION__,
 169        mt->total_width, mt->total_height, mt->cpp);
 170
 171    return GL_TRUE;
 172 }
 173