2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "main/macros.h"
29 #include "main/shaderobj.h"
30 #include "program/prog_print.h"
31 #include "program/prog_parameter.h"
34 #define MAX_INSTRUCTION (1 << 30)
41 * Common helper for constructing swizzles. When only a subset of
42 * channels of a vec4 are used, we don't want to reference the other
43 * channels, as that will tell optimization passes that those other
47 swizzle_for_size(int size
)
49 static const unsigned size_swizzles
[4] = {
50 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
),
51 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Y
, SWIZZLE_Y
),
52 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_Z
),
53 BRW_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_W
),
56 assert((size
>= 1) && (size
<= 4));
57 return size_swizzles
[size
- 1];
63 memset(this, 0, sizeof(*this));
65 this->file
= BAD_FILE
;
68 src_reg::src_reg(register_file file
, int reg
, const glsl_type
*type
)
74 if (type
&& (type
->is_scalar() || type
->is_vector() || type
->is_matrix()))
75 this->swizzle
= swizzle_for_size(type
->vector_elements
);
77 this->swizzle
= SWIZZLE_XYZW
;
80 /** Generic unset register constructor. */
86 src_reg::src_reg(float f
)
91 this->type
= BRW_REGISTER_TYPE_F
;
95 src_reg::src_reg(uint32_t u
)
100 this->type
= BRW_REGISTER_TYPE_UD
;
104 src_reg::src_reg(int32_t i
)
109 this->type
= BRW_REGISTER_TYPE_D
;
113 src_reg::src_reg(dst_reg reg
)
117 this->file
= reg
.file
;
119 this->reg_offset
= reg
.reg_offset
;
120 this->type
= reg
.type
;
121 this->reladdr
= reg
.reladdr
;
122 this->fixed_hw_reg
= reg
.fixed_hw_reg
;
128 for (int i
= 0; i
< 4; i
++) {
129 if (!(reg
.writemask
& (1 << i
)))
132 swizzles
[next_chan
++] = last
= i
;
135 for (; next_chan
< 4; next_chan
++) {
136 swizzles
[next_chan
] = last
;
139 this->swizzle
= BRW_SWIZZLE4(swizzles
[0], swizzles
[1],
140 swizzles
[2], swizzles
[3]);
146 memset(this, 0, sizeof(*this));
147 this->file
= BAD_FILE
;
148 this->writemask
= WRITEMASK_XYZW
;
156 dst_reg::dst_reg(register_file file
, int reg
)
164 dst_reg::dst_reg(register_file file
, int reg
, const glsl_type
*type
,
171 this->type
= brw_type_for_base_type(type
);
172 this->writemask
= writemask
;
175 dst_reg::dst_reg(struct brw_reg reg
)
180 this->fixed_hw_reg
= reg
;
183 dst_reg::dst_reg(src_reg reg
)
187 this->file
= reg
.file
;
189 this->reg_offset
= reg
.reg_offset
;
190 this->type
= reg
.type
;
191 /* How should we do writemasking when converting from a src_reg? It seems
192 * pretty obvious that for src.xxxx the caller wants to write to src.x, but
193 * what about for src.wx? Just special-case src.xxxx for now.
195 if (reg
.swizzle
== BRW_SWIZZLE_XXXX
)
196 this->writemask
= WRITEMASK_X
;
198 this->writemask
= WRITEMASK_XYZW
;
199 this->reladdr
= reg
.reladdr
;
200 this->fixed_hw_reg
= reg
.fixed_hw_reg
;
204 vec4_instruction::is_send_from_grf()
207 case SHADER_OPCODE_SHADER_TIME_ADD
:
208 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
216 vec4_visitor::can_do_source_mods(vec4_instruction
*inst
)
218 if (intel
->gen
== 6 && inst
->is_math())
221 if (inst
->is_send_from_grf())
228 * Returns how many MRFs an opcode will write over.
230 * Note that this is not the 0 or 1 implied writes in an actual gen
231 * instruction -- the generate_* functions generate additional MOVs
235 vec4_visitor::implied_mrf_writes(vec4_instruction
*inst
)
240 switch (inst
->opcode
) {
241 case SHADER_OPCODE_RCP
:
242 case SHADER_OPCODE_RSQ
:
243 case SHADER_OPCODE_SQRT
:
244 case SHADER_OPCODE_EXP2
:
245 case SHADER_OPCODE_LOG2
:
246 case SHADER_OPCODE_SIN
:
247 case SHADER_OPCODE_COS
:
249 case SHADER_OPCODE_INT_QUOTIENT
:
250 case SHADER_OPCODE_INT_REMAINDER
:
251 case SHADER_OPCODE_POW
:
253 case VS_OPCODE_URB_WRITE
:
255 case VS_OPCODE_PULL_CONSTANT_LOAD
:
257 case VS_OPCODE_SCRATCH_READ
:
259 case VS_OPCODE_SCRATCH_WRITE
:
261 case SHADER_OPCODE_SHADER_TIME_ADD
:
263 case SHADER_OPCODE_TEX
:
264 case SHADER_OPCODE_TXL
:
265 case SHADER_OPCODE_TXD
:
266 case SHADER_OPCODE_TXF
:
267 case SHADER_OPCODE_TXF_MS
:
268 case SHADER_OPCODE_TXS
:
269 return inst
->header_present
? 1 : 0;
271 assert(!"not reached");
277 src_reg::equals(src_reg
*r
)
279 return (file
== r
->file
&&
281 reg_offset
== r
->reg_offset
&&
283 negate
== r
->negate
&&
285 swizzle
== r
->swizzle
&&
286 !reladdr
&& !r
->reladdr
&&
287 memcmp(&fixed_hw_reg
, &r
->fixed_hw_reg
,
288 sizeof(fixed_hw_reg
)) == 0 &&
293 * Must be called after calculate_live_intervales() to remove unused
294 * writes to registers -- register allocation will fail otherwise
295 * because something deffed but not used won't be considered to
296 * interfere with other regs.
299 vec4_visitor::dead_code_eliminate()
301 bool progress
= false;
304 calculate_live_intervals();
306 foreach_list_safe(node
, &this->instructions
) {
307 vec4_instruction
*inst
= (vec4_instruction
*)node
;
309 if (inst
->dst
.file
== GRF
) {
310 assert(this->virtual_grf_end
[inst
->dst
.reg
] >= pc
);
311 if (this->virtual_grf_end
[inst
->dst
.reg
] == pc
) {
321 live_intervals_valid
= false;
327 vec4_visitor::split_uniform_registers()
329 /* Prior to this, uniforms have been in an array sized according to
330 * the number of vector uniforms present, sparsely filled (so an
331 * aggregate results in reg indices being skipped over). Now we're
332 * going to cut those aggregates up so each .reg index is one
333 * vector. The goal is to make elimination of unused uniform
334 * components easier later.
336 foreach_list(node
, &this->instructions
) {
337 vec4_instruction
*inst
= (vec4_instruction
*)node
;
339 for (int i
= 0 ; i
< 3; i
++) {
340 if (inst
->src
[i
].file
!= UNIFORM
)
343 assert(!inst
->src
[i
].reladdr
);
345 inst
->src
[i
].reg
+= inst
->src
[i
].reg_offset
;
346 inst
->src
[i
].reg_offset
= 0;
350 /* Update that everything is now vector-sized. */
351 for (int i
= 0; i
< this->uniforms
; i
++) {
352 this->uniform_size
[i
] = 1;
357 vec4_visitor::pack_uniform_registers()
359 bool uniform_used
[this->uniforms
];
360 int new_loc
[this->uniforms
];
361 int new_chan
[this->uniforms
];
363 memset(uniform_used
, 0, sizeof(uniform_used
));
364 memset(new_loc
, 0, sizeof(new_loc
));
365 memset(new_chan
, 0, sizeof(new_chan
));
367 /* Find which uniform vectors are actually used by the program. We
368 * expect unused vector elements when we've moved array access out
369 * to pull constants, and from some GLSL code generators like wine.
371 foreach_list(node
, &this->instructions
) {
372 vec4_instruction
*inst
= (vec4_instruction
*)node
;
374 for (int i
= 0 ; i
< 3; i
++) {
375 if (inst
->src
[i
].file
!= UNIFORM
)
378 uniform_used
[inst
->src
[i
].reg
] = true;
382 int new_uniform_count
= 0;
384 /* Now, figure out a packing of the live uniform vectors into our
387 for (int src
= 0; src
< uniforms
; src
++) {
388 int size
= this->uniform_vector_size
[src
];
390 if (!uniform_used
[src
]) {
391 this->uniform_vector_size
[src
] = 0;
396 /* Find the lowest place we can slot this uniform in. */
397 for (dst
= 0; dst
< src
; dst
++) {
398 if (this->uniform_vector_size
[dst
] + size
<= 4)
407 new_chan
[src
] = this->uniform_vector_size
[dst
];
409 /* Move the references to the data */
410 for (int j
= 0; j
< size
; j
++) {
411 prog_data
->param
[dst
* 4 + new_chan
[src
] + j
] =
412 prog_data
->param
[src
* 4 + j
];
415 this->uniform_vector_size
[dst
] += size
;
416 this->uniform_vector_size
[src
] = 0;
419 new_uniform_count
= MAX2(new_uniform_count
, dst
+ 1);
422 this->uniforms
= new_uniform_count
;
424 /* Now, update the instructions for our repacked uniforms. */
425 foreach_list(node
, &this->instructions
) {
426 vec4_instruction
*inst
= (vec4_instruction
*)node
;
428 for (int i
= 0 ; i
< 3; i
++) {
429 int src
= inst
->src
[i
].reg
;
431 if (inst
->src
[i
].file
!= UNIFORM
)
434 inst
->src
[i
].reg
= new_loc
[src
];
436 int sx
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, 0) + new_chan
[src
];
437 int sy
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, 1) + new_chan
[src
];
438 int sz
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, 2) + new_chan
[src
];
439 int sw
= BRW_GET_SWZ(inst
->src
[i
].swizzle
, 3) + new_chan
[src
];
440 inst
->src
[i
].swizzle
= BRW_SWIZZLE4(sx
, sy
, sz
, sw
);
446 src_reg::is_zero() const
451 if (type
== BRW_REGISTER_TYPE_F
) {
459 src_reg::is_one() const
464 if (type
== BRW_REGISTER_TYPE_F
) {
472 * Does algebraic optimizations (0 * a = 0, 1 * a = a, a + 0 = a).
474 * While GLSL IR also performs this optimization, we end up with it in
475 * our instruction stream for a couple of reasons. One is that we
476 * sometimes generate silly instructions, for example in array access
477 * where we'll generate "ADD offset, index, base" even if base is 0.
478 * The other is that GLSL IR's constant propagation doesn't track the
479 * components of aggregates, so some VS patterns (initialize matrix to
480 * 0, accumulate in vertex blending factors) end up breaking down to
481 * instructions involving 0.
484 vec4_visitor::opt_algebraic()
486 bool progress
= false;
488 foreach_list(node
, &this->instructions
) {
489 vec4_instruction
*inst
= (vec4_instruction
*)node
;
491 switch (inst
->opcode
) {
493 if (inst
->src
[1].is_zero()) {
494 inst
->opcode
= BRW_OPCODE_MOV
;
495 inst
->src
[1] = src_reg();
501 if (inst
->src
[1].is_zero()) {
502 inst
->opcode
= BRW_OPCODE_MOV
;
503 switch (inst
->src
[0].type
) {
504 case BRW_REGISTER_TYPE_F
:
505 inst
->src
[0] = src_reg(0.0f
);
507 case BRW_REGISTER_TYPE_D
:
508 inst
->src
[0] = src_reg(0);
510 case BRW_REGISTER_TYPE_UD
:
511 inst
->src
[0] = src_reg(0u);
514 assert(!"not reached");
515 inst
->src
[0] = src_reg(0.0f
);
518 inst
->src
[1] = src_reg();
520 } else if (inst
->src
[1].is_one()) {
521 inst
->opcode
= BRW_OPCODE_MOV
;
522 inst
->src
[1] = src_reg();
532 this->live_intervals_valid
= false;
538 * Only a limited number of hardware registers may be used for push
539 * constants, so this turns access to the overflowed constants into
543 vec4_visitor::move_push_constants_to_pull_constants()
545 int pull_constant_loc
[this->uniforms
];
547 /* Only allow 32 registers (256 uniform components) as push constants,
548 * which is the limit on gen6.
550 int max_uniform_components
= 32 * 8;
551 if (this->uniforms
* 4 <= max_uniform_components
)
554 /* Make some sort of choice as to which uniforms get sent to pull
555 * constants. We could potentially do something clever here like
556 * look for the most infrequently used uniform vec4s, but leave
559 for (int i
= 0; i
< this->uniforms
* 4; i
+= 4) {
560 pull_constant_loc
[i
/ 4] = -1;
562 if (i
>= max_uniform_components
) {
563 const float **values
= &prog_data
->param
[i
];
565 /* Try to find an existing copy of this uniform in the pull
566 * constants if it was part of an array access already.
568 for (unsigned int j
= 0; j
< prog_data
->nr_pull_params
; j
+= 4) {
571 for (matches
= 0; matches
< 4; matches
++) {
572 if (prog_data
->pull_param
[j
+ matches
] != values
[matches
])
577 pull_constant_loc
[i
/ 4] = j
/ 4;
582 if (pull_constant_loc
[i
/ 4] == -1) {
583 assert(prog_data
->nr_pull_params
% 4 == 0);
584 pull_constant_loc
[i
/ 4] = prog_data
->nr_pull_params
/ 4;
586 for (int j
= 0; j
< 4; j
++) {
587 prog_data
->pull_param
[prog_data
->nr_pull_params
++] = values
[j
];
593 /* Now actually rewrite usage of the things we've moved to pull
596 foreach_list_safe(node
, &this->instructions
) {
597 vec4_instruction
*inst
= (vec4_instruction
*)node
;
599 for (int i
= 0 ; i
< 3; i
++) {
600 if (inst
->src
[i
].file
!= UNIFORM
||
601 pull_constant_loc
[inst
->src
[i
].reg
] == -1)
604 int uniform
= inst
->src
[i
].reg
;
606 dst_reg temp
= dst_reg(this, glsl_type::vec4_type
);
608 emit_pull_constant_load(inst
, temp
, inst
->src
[i
],
609 pull_constant_loc
[uniform
]);
611 inst
->src
[i
].file
= temp
.file
;
612 inst
->src
[i
].reg
= temp
.reg
;
613 inst
->src
[i
].reg_offset
= temp
.reg_offset
;
614 inst
->src
[i
].reladdr
= NULL
;
618 /* Repack push constants to remove the now-unused ones. */
619 pack_uniform_registers();
623 * Sets the dependency control fields on instructions after register
624 * allocation and before the generator is run.
626 * When you have a sequence of instructions like:
628 * DP4 temp.x vertex uniform[0]
629 * DP4 temp.y vertex uniform[0]
630 * DP4 temp.z vertex uniform[0]
631 * DP4 temp.w vertex uniform[0]
633 * The hardware doesn't know that it can actually run the later instructions
634 * while the previous ones are in flight, producing stalls. However, we have
635 * manual fields we can set in the instructions that let it do so.
638 vec4_visitor::opt_set_dependency_control()
640 vec4_instruction
*last_grf_write
[BRW_MAX_GRF
];
641 uint8_t grf_channels_written
[BRW_MAX_GRF
];
642 vec4_instruction
*last_mrf_write
[BRW_MAX_GRF
];
643 uint8_t mrf_channels_written
[BRW_MAX_GRF
];
647 assert(prog_data
->total_grf
||
648 !"Must be called after register allocation");
650 for (int i
= 0; i
< cfg
.num_blocks
; i
++) {
651 bblock_t
*bblock
= cfg
.blocks
[i
];
652 vec4_instruction
*inst
;
654 memset(last_grf_write
, 0, sizeof(last_grf_write
));
655 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
657 for (inst
= (vec4_instruction
*)bblock
->start
;
658 inst
!= (vec4_instruction
*)bblock
->end
->next
;
659 inst
= (vec4_instruction
*)inst
->next
) {
660 /* If we read from a register that we were doing dependency control
661 * on, don't do dependency control across the read.
663 for (int i
= 0; i
< 3; i
++) {
664 int reg
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
665 if (inst
->src
[i
].file
== GRF
) {
666 last_grf_write
[reg
] = NULL
;
667 } else if (inst
->src
[i
].file
== HW_REG
) {
668 memset(last_grf_write
, 0, sizeof(last_grf_write
));
671 assert(inst
->src
[i
].file
!= MRF
);
674 /* In the presence of send messages, totally interrupt dependency
675 * control. They're long enough that the chance of dependency
676 * control around them just doesn't matter.
679 memset(last_grf_write
, 0, sizeof(last_grf_write
));
680 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
684 /* It looks like setting dependency control on a predicated
685 * instruction hangs the GPU.
687 if (inst
->predicate
) {
688 memset(last_grf_write
, 0, sizeof(last_grf_write
));
689 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
693 /* Now, see if we can do dependency control for this instruction
694 * against a previous one writing to its destination.
696 int reg
= inst
->dst
.reg
+ inst
->dst
.reg_offset
;
697 if (inst
->dst
.file
== GRF
) {
698 if (last_grf_write
[reg
] &&
699 !(inst
->dst
.writemask
& grf_channels_written
[reg
])) {
700 last_grf_write
[reg
]->no_dd_clear
= true;
701 inst
->no_dd_check
= true;
703 grf_channels_written
[reg
] = 0;
706 last_grf_write
[reg
] = inst
;
707 grf_channels_written
[reg
] |= inst
->dst
.writemask
;
708 } else if (inst
->dst
.file
== MRF
) {
709 if (last_mrf_write
[reg
] &&
710 !(inst
->dst
.writemask
& mrf_channels_written
[reg
])) {
711 last_mrf_write
[reg
]->no_dd_clear
= true;
712 inst
->no_dd_check
= true;
714 mrf_channels_written
[reg
] = 0;
717 last_mrf_write
[reg
] = inst
;
718 mrf_channels_written
[reg
] |= inst
->dst
.writemask
;
719 } else if (inst
->dst
.reg
== HW_REG
) {
720 if (inst
->dst
.fixed_hw_reg
.file
== BRW_GENERAL_REGISTER_FILE
)
721 memset(last_grf_write
, 0, sizeof(last_grf_write
));
722 if (inst
->dst
.fixed_hw_reg
.file
== BRW_MESSAGE_REGISTER_FILE
)
723 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
730 vec4_instruction::can_reswizzle_dst(int dst_writemask
,
734 /* If this instruction sets anything not referenced by swizzle, then we'd
735 * totally break it when we reswizzle.
737 if (dst
.writemask
& ~swizzle_mask
)
746 /* Check if there happens to be no reswizzling required. */
747 for (int c
= 0; c
< 4; c
++) {
748 int bit
= 1 << BRW_GET_SWZ(swizzle
, c
);
749 /* Skip components of the swizzle not used by the dst. */
750 if (!(dst_writemask
& (1 << c
)))
753 /* We don't do the reswizzling yet, so just sanity check that we
764 * For any channels in the swizzle's source that were populated by this
765 * instruction, rewrite the instruction to put the appropriate result directly
768 * e.g. for swizzle=yywx, MUL a.xy b c -> MUL a.yy_x b.yy z.yy_x
771 vec4_instruction::reswizzle_dst(int dst_writemask
, int swizzle
)
773 int new_writemask
= 0;
779 for (int c
= 0; c
< 4; c
++) {
780 int bit
= 1 << BRW_GET_SWZ(swizzle
, c
);
781 /* Skip components of the swizzle not used by the dst. */
782 if (!(dst_writemask
& (1 << c
)))
784 /* If we were populating this component, then populate the
785 * corresponding channel of the new dst.
787 if (dst
.writemask
& bit
)
788 new_writemask
|= (1 << c
);
790 dst
.writemask
= new_writemask
;
793 for (int c
= 0; c
< 4; c
++) {
794 /* Skip components of the swizzle not used by the dst. */
795 if (!(dst_writemask
& (1 << c
)))
798 /* We don't do the reswizzling yet, so just sanity check that we
801 assert((1 << BRW_GET_SWZ(swizzle
, c
)) == (1 << c
));
808 * Tries to reduce extra MOV instructions by taking temporary GRFs that get
809 * just written and then MOVed into another reg and making the original write
810 * of the GRF write directly to the final destination instead.
813 vec4_visitor::opt_register_coalesce()
815 bool progress
= false;
818 calculate_live_intervals();
820 foreach_list_safe(node
, &this->instructions
) {
821 vec4_instruction
*inst
= (vec4_instruction
*)node
;
826 if (inst
->opcode
!= BRW_OPCODE_MOV
||
827 (inst
->dst
.file
!= GRF
&& inst
->dst
.file
!= MRF
) ||
829 inst
->src
[0].file
!= GRF
||
830 inst
->dst
.type
!= inst
->src
[0].type
||
831 inst
->src
[0].abs
|| inst
->src
[0].negate
|| inst
->src
[0].reladdr
)
834 bool to_mrf
= (inst
->dst
.file
== MRF
);
836 /* Can't coalesce this GRF if someone else was going to
839 if (this->virtual_grf_end
[inst
->src
[0].reg
] > ip
)
842 /* We need to check interference with the final destination between this
843 * instruction and the earliest instruction involved in writing the GRF
844 * we're eliminating. To do that, keep track of which of our source
845 * channels we've seen initialized.
847 bool chans_needed
[4] = {false, false, false, false};
848 int chans_remaining
= 0;
849 int swizzle_mask
= 0;
850 for (int i
= 0; i
< 4; i
++) {
851 int chan
= BRW_GET_SWZ(inst
->src
[0].swizzle
, i
);
853 if (!(inst
->dst
.writemask
& (1 << i
)))
856 swizzle_mask
|= (1 << chan
);
858 if (!chans_needed
[chan
]) {
859 chans_needed
[chan
] = true;
864 /* Now walk up the instruction stream trying to see if we can rewrite
865 * everything writing to the temporary to write into the destination
868 vec4_instruction
*scan_inst
;
869 for (scan_inst
= (vec4_instruction
*)inst
->prev
;
870 scan_inst
->prev
!= NULL
;
871 scan_inst
= (vec4_instruction
*)scan_inst
->prev
) {
872 if (scan_inst
->dst
.file
== GRF
&&
873 scan_inst
->dst
.reg
== inst
->src
[0].reg
&&
874 scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
875 /* Found something writing to the reg we want to coalesce away. */
877 /* SEND instructions can't have MRF as a destination. */
881 if (intel
->gen
== 6) {
882 /* gen6 math instructions must have the destination be
883 * GRF, so no compute-to-MRF for them.
885 if (scan_inst
->is_math()) {
891 /* If we can't handle the swizzle, bail. */
892 if (!scan_inst
->can_reswizzle_dst(inst
->dst
.writemask
,
893 inst
->src
[0].swizzle
,
898 /* Mark which channels we found unconditional writes for. */
899 if (!scan_inst
->predicate
) {
900 for (int i
= 0; i
< 4; i
++) {
901 if (scan_inst
->dst
.writemask
& (1 << i
) &&
903 chans_needed
[i
] = false;
909 if (chans_remaining
== 0)
913 /* We don't handle flow control here. Most computation of values
914 * that could be coalesced happens just before their use.
916 if (scan_inst
->opcode
== BRW_OPCODE_DO
||
917 scan_inst
->opcode
== BRW_OPCODE_WHILE
||
918 scan_inst
->opcode
== BRW_OPCODE_ELSE
||
919 scan_inst
->opcode
== BRW_OPCODE_ENDIF
) {
923 /* You can't read from an MRF, so if someone else reads our MRF's
924 * source GRF that we wanted to rewrite, that stops us. If it's a
925 * GRF we're trying to coalesce to, we don't actually handle
926 * rewriting sources so bail in that case as well.
928 bool interfered
= false;
929 for (int i
= 0; i
< 3; i
++) {
930 if (scan_inst
->src
[i
].file
== GRF
&&
931 scan_inst
->src
[i
].reg
== inst
->src
[0].reg
&&
932 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
939 /* If somebody else writes our destination here, we can't coalesce
942 if (scan_inst
->dst
.file
== inst
->dst
.file
&&
943 scan_inst
->dst
.reg
== inst
->dst
.reg
) {
947 /* Check for reads of the register we're trying to coalesce into. We
948 * can't go rewriting instructions above that to put some other value
949 * in the register instead.
951 if (to_mrf
&& scan_inst
->mlen
> 0) {
952 if (inst
->dst
.reg
>= scan_inst
->base_mrf
&&
953 inst
->dst
.reg
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
957 for (int i
= 0; i
< 3; i
++) {
958 if (scan_inst
->src
[i
].file
== inst
->dst
.file
&&
959 scan_inst
->src
[i
].reg
== inst
->dst
.reg
&&
960 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
969 if (chans_remaining
== 0) {
970 /* If we've made it here, we have an MOV we want to coalesce out, and
971 * a scan_inst pointing to the earliest instruction involved in
972 * computing the value. Now go rewrite the instruction stream
976 while (scan_inst
!= inst
) {
977 if (scan_inst
->dst
.file
== GRF
&&
978 scan_inst
->dst
.reg
== inst
->src
[0].reg
&&
979 scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
980 scan_inst
->reswizzle_dst(inst
->dst
.writemask
,
981 inst
->src
[0].swizzle
);
982 scan_inst
->dst
.file
= inst
->dst
.file
;
983 scan_inst
->dst
.reg
= inst
->dst
.reg
;
984 scan_inst
->dst
.reg_offset
= inst
->dst
.reg_offset
;
985 scan_inst
->saturate
|= inst
->saturate
;
987 scan_inst
= (vec4_instruction
*)scan_inst
->next
;
995 live_intervals_valid
= false;
1001 * Splits virtual GRFs requesting more than one contiguous physical register.
1003 * We initially create large virtual GRFs for temporary structures, arrays,
1004 * and matrices, so that the dereference visitor functions can add reg_offsets
1005 * to work their way down to the actual member being accessed. But when it
1006 * comes to optimization, we'd like to treat each register as individual
1007 * storage if possible.
1009 * So far, the only thing that might prevent splitting is a send message from
1013 vec4_visitor::split_virtual_grfs()
1015 int num_vars
= this->virtual_grf_count
;
1016 int new_virtual_grf
[num_vars
];
1017 bool split_grf
[num_vars
];
1019 memset(new_virtual_grf
, 0, sizeof(new_virtual_grf
));
1021 /* Try to split anything > 0 sized. */
1022 for (int i
= 0; i
< num_vars
; i
++) {
1023 split_grf
[i
] = this->virtual_grf_sizes
[i
] != 1;
1026 /* Check that the instructions are compatible with the registers we're trying
1029 foreach_list(node
, &this->instructions
) {
1030 vec4_instruction
*inst
= (vec4_instruction
*)node
;
1032 /* If there's a SEND message loading from a GRF on gen7+, it needs to be
1033 * contiguous. Assume that the GRF for the SEND is always in src[0].
1035 if (inst
->is_send_from_grf()) {
1036 split_grf
[inst
->src
[0].reg
] = false;
1040 /* Allocate new space for split regs. Note that the virtual
1041 * numbers will be contiguous.
1043 for (int i
= 0; i
< num_vars
; i
++) {
1047 new_virtual_grf
[i
] = virtual_grf_alloc(1);
1048 for (int j
= 2; j
< this->virtual_grf_sizes
[i
]; j
++) {
1049 int reg
= virtual_grf_alloc(1);
1050 assert(reg
== new_virtual_grf
[i
] + j
- 1);
1053 this->virtual_grf_sizes
[i
] = 1;
1056 foreach_list(node
, &this->instructions
) {
1057 vec4_instruction
*inst
= (vec4_instruction
*)node
;
1059 if (inst
->dst
.file
== GRF
&& split_grf
[inst
->dst
.reg
] &&
1060 inst
->dst
.reg_offset
!= 0) {
1061 inst
->dst
.reg
= (new_virtual_grf
[inst
->dst
.reg
] +
1062 inst
->dst
.reg_offset
- 1);
1063 inst
->dst
.reg_offset
= 0;
1065 for (int i
= 0; i
< 3; i
++) {
1066 if (inst
->src
[i
].file
== GRF
&& split_grf
[inst
->src
[i
].reg
] &&
1067 inst
->src
[i
].reg_offset
!= 0) {
1068 inst
->src
[i
].reg
= (new_virtual_grf
[inst
->src
[i
].reg
] +
1069 inst
->src
[i
].reg_offset
- 1);
1070 inst
->src
[i
].reg_offset
= 0;
1074 this->live_intervals_valid
= false;
1078 vec4_visitor::dump_instruction(backend_instruction
*be_inst
)
1080 vec4_instruction
*inst
= (vec4_instruction
*)be_inst
;
1082 printf("%s ", brw_instruction_name(inst
->opcode
));
1084 switch (inst
->dst
.file
) {
1086 printf("vgrf%d.%d", inst
->dst
.reg
, inst
->dst
.reg_offset
);
1089 printf("m%d", inst
->dst
.reg
);
1098 if (inst
->dst
.writemask
!= WRITEMASK_XYZW
) {
1100 if (inst
->dst
.writemask
& 1)
1102 if (inst
->dst
.writemask
& 2)
1104 if (inst
->dst
.writemask
& 4)
1106 if (inst
->dst
.writemask
& 8)
1111 for (int i
= 0; i
< 3; i
++) {
1112 switch (inst
->src
[i
].file
) {
1114 printf("vgrf%d", inst
->src
[i
].reg
);
1117 printf("attr%d", inst
->src
[i
].reg
);
1120 printf("u%d", inst
->src
[i
].reg
);
1123 switch (inst
->src
[i
].type
) {
1124 case BRW_REGISTER_TYPE_F
:
1125 printf("%fF", inst
->src
[i
].imm
.f
);
1127 case BRW_REGISTER_TYPE_D
:
1128 printf("%dD", inst
->src
[i
].imm
.i
);
1130 case BRW_REGISTER_TYPE_UD
:
1131 printf("%uU", inst
->src
[i
].imm
.u
);
1146 if (inst
->src
[i
].reg_offset
)
1147 printf(".%d", inst
->src
[i
].reg_offset
);
1149 static const char *chans
[4] = {"x", "y", "z", "w"};
1151 for (int c
= 0; c
< 4; c
++) {
1152 printf("%s", chans
[BRW_GET_SWZ(inst
->src
[i
].swizzle
, c
)]);
1163 * Replace each register of type ATTR in this->instructions with a reference
1164 * to a fixed HW register.
1167 vec4_visitor::lower_attributes_to_hw_regs(const int *attribute_map
)
1169 foreach_list(node
, &this->instructions
) {
1170 vec4_instruction
*inst
= (vec4_instruction
*)node
;
1172 /* We have to support ATTR as a destination for GL_FIXED fixup. */
1173 if (inst
->dst
.file
== ATTR
) {
1174 int grf
= attribute_map
[inst
->dst
.reg
+ inst
->dst
.reg_offset
];
1176 /* All attributes used in the shader need to have been assigned a
1177 * hardware register by the caller
1181 struct brw_reg reg
= brw_vec8_grf(grf
, 0);
1182 reg
.type
= inst
->dst
.type
;
1183 reg
.dw1
.bits
.writemask
= inst
->dst
.writemask
;
1185 inst
->dst
.file
= HW_REG
;
1186 inst
->dst
.fixed_hw_reg
= reg
;
1189 for (int i
= 0; i
< 3; i
++) {
1190 if (inst
->src
[i
].file
!= ATTR
)
1193 int grf
= attribute_map
[inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
];
1195 /* All attributes used in the shader need to have been assigned a
1196 * hardware register by the caller
1200 struct brw_reg reg
= brw_vec8_grf(grf
, 0);
1201 reg
.dw1
.bits
.swizzle
= inst
->src
[i
].swizzle
;
1202 reg
.type
= inst
->src
[i
].type
;
1203 if (inst
->src
[i
].abs
)
1205 if (inst
->src
[i
].negate
)
1208 inst
->src
[i
].file
= HW_REG
;
1209 inst
->src
[i
].fixed_hw_reg
= reg
;
1215 vec4_vs_visitor::setup_attributes(int payload_reg
)
1218 int attribute_map
[VERT_ATTRIB_MAX
+ 1];
1219 memset(attribute_map
, 0, sizeof(attribute_map
));
1222 for (int i
= 0; i
< VERT_ATTRIB_MAX
; i
++) {
1223 if (vs_prog_data
->inputs_read
& BITFIELD64_BIT(i
)) {
1224 attribute_map
[i
] = payload_reg
+ nr_attributes
;
1229 /* VertexID is stored by the VF as the last vertex element, but we
1230 * don't represent it with a flag in inputs_read, so we call it
1233 if (vs_prog_data
->uses_vertexid
) {
1234 attribute_map
[VERT_ATTRIB_MAX
] = payload_reg
+ nr_attributes
;
1238 lower_attributes_to_hw_regs(attribute_map
);
1240 /* The BSpec says we always have to read at least one thing from
1241 * the VF, and it appears that the hardware wedges otherwise.
1243 if (nr_attributes
== 0)
1246 prog_data
->urb_read_length
= (nr_attributes
+ 1) / 2;
1248 unsigned vue_entries
=
1249 MAX2(nr_attributes
, prog_data
->vue_map
.num_slots
);
1251 if (intel
->gen
== 6)
1252 prog_data
->urb_entry_size
= ALIGN(vue_entries
, 8) / 8;
1254 prog_data
->urb_entry_size
= ALIGN(vue_entries
, 4) / 4;
1256 return payload_reg
+ nr_attributes
;
1260 vec4_visitor::setup_uniforms(int reg
)
1262 /* The pre-gen6 VS requires that some push constants get loaded no
1263 * matter what, or the GPU would hang.
1265 if (intel
->gen
< 6 && this->uniforms
== 0) {
1266 this->uniform_vector_size
[this->uniforms
] = 1;
1268 for (unsigned int i
= 0; i
< 4; i
++) {
1269 unsigned int slot
= this->uniforms
* 4 + i
;
1270 static float zero
= 0.0;
1271 prog_data
->param
[slot
] = &zero
;
1277 reg
+= ALIGN(uniforms
, 2) / 2;
1280 prog_data
->nr_params
= this->uniforms
* 4;
1282 prog_data
->curb_read_length
= reg
- 1;
1288 vec4_visitor::setup_payload(void)
1292 /* The payload always contains important data in g0, which contains
1293 * the URB handles that are passed on to the URB write at the end
1294 * of the thread. So, we always start push constants at g1.
1298 reg
= setup_uniforms(reg
);
1300 reg
= setup_attributes(reg
);
1302 this->first_non_payload_grf
= reg
;
1306 vec4_visitor::get_timestamp()
1308 assert(intel
->gen
>= 7);
1310 src_reg ts
= src_reg(brw_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
1313 BRW_REGISTER_TYPE_UD
,
1314 BRW_VERTICAL_STRIDE_0
,
1316 BRW_HORIZONTAL_STRIDE_4
,
1320 dst_reg dst
= dst_reg(this, glsl_type::uvec4_type
);
1322 vec4_instruction
*mov
= emit(MOV(dst
, ts
));
1323 /* We want to read the 3 fields we care about (mostly field 0, but also 2)
1324 * even if it's not enabled in the dispatch.
1326 mov
->force_writemask_all
= true;
1328 return src_reg(dst
);
1332 vec4_visitor::emit_shader_time_begin()
1334 current_annotation
= "shader time start";
1335 shader_start_time
= get_timestamp();
1339 vec4_visitor::emit_shader_time_end()
1341 current_annotation
= "shader time end";
1342 src_reg shader_end_time
= get_timestamp();
1345 /* Check that there weren't any timestamp reset events (assuming these
1346 * were the only two timestamp reads that happened).
1348 src_reg reset_end
= shader_end_time
;
1349 reset_end
.swizzle
= BRW_SWIZZLE_ZZZZ
;
1350 vec4_instruction
*test
= emit(AND(dst_null_d(), reset_end
, src_reg(1u)));
1351 test
->conditional_mod
= BRW_CONDITIONAL_Z
;
1353 emit(IF(BRW_PREDICATE_NORMAL
));
1355 /* Take the current timestamp and get the delta. */
1356 shader_start_time
.negate
= true;
1357 dst_reg diff
= dst_reg(this, glsl_type::uint_type
);
1358 emit(ADD(diff
, shader_start_time
, shader_end_time
));
1360 /* If there were no instructions between the two timestamp gets, the diff
1361 * is 2 cycles. Remove that overhead, so I can forget about that when
1362 * trying to determine the time taken for single instructions.
1364 emit(ADD(diff
, src_reg(diff
), src_reg(-2u)));
1366 emit_shader_time_write(ST_VS
, src_reg(diff
));
1367 emit_shader_time_write(ST_VS_WRITTEN
, src_reg(1u));
1368 emit(BRW_OPCODE_ELSE
);
1369 emit_shader_time_write(ST_VS_RESET
, src_reg(1u));
1370 emit(BRW_OPCODE_ENDIF
);
1374 vec4_visitor::emit_shader_time_write(enum shader_time_shader_type type
,
1377 int shader_time_index
=
1378 brw_get_shader_time_index(brw
, shader_prog
, prog
, type
);
1381 dst_reg(this, glsl_type::get_array_instance(glsl_type::vec4_type
, 2));
1383 dst_reg offset
= dst
;
1387 offset
.type
= BRW_REGISTER_TYPE_UD
;
1388 emit(MOV(offset
, src_reg(shader_time_index
* SHADER_TIME_STRIDE
)));
1390 time
.type
= BRW_REGISTER_TYPE_UD
;
1391 emit(MOV(time
, src_reg(value
)));
1393 emit(SHADER_OPCODE_SHADER_TIME_ADD
, dst_reg(), src_reg(dst
));
1399 sanity_param_count
= prog
->Parameters
->NumParameters
;
1401 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
1402 emit_shader_time_begin();
1406 /* Generate VS IR for main(). (the visitor only descends into
1407 * functions called "main").
1410 visit_instructions(shader
->ir
);
1412 emit_program_code();
1416 if (key
->userclip_active
&& !key
->uses_clip_distance
)
1417 setup_uniform_clipplane_values();
1421 /* Before any optimization, push array accesses out to scratch
1422 * space where we need them to be. This pass may allocate new
1423 * virtual GRFs, so we want to do it early. It also makes sure
1424 * that we have reladdr computations available for CSE, since we'll
1425 * often do repeated subexpressions for those.
1428 move_grf_array_access_to_scratch();
1429 move_uniform_array_access_to_pull_constants();
1431 /* The ARB_vertex_program frontend emits pull constant loads directly
1432 * rather than using reladdr, so we don't need to walk through all the
1433 * instructions looking for things to move. There isn't anything.
1435 * We do still need to split things to vec4 size.
1437 split_uniform_registers();
1439 pack_uniform_registers();
1440 move_push_constants_to_pull_constants();
1441 split_virtual_grfs();
1446 progress
= dead_code_eliminate() || progress
;
1447 progress
= opt_copy_propagation() || progress
;
1448 progress
= opt_algebraic() || progress
;
1449 progress
= opt_register_coalesce() || progress
;
1459 /* Debug of register spilling: Go spill everything. */
1460 const int grf_count
= virtual_grf_count
;
1461 float spill_costs
[virtual_grf_count
];
1462 bool no_spill
[virtual_grf_count
];
1463 evaluate_spill_costs(spill_costs
, no_spill
);
1464 for (int i
= 0; i
< grf_count
; i
++) {
1471 while (!reg_allocate()) {
1476 opt_schedule_instructions();
1478 opt_set_dependency_control();
1480 /* If any state parameters were appended, then ParameterValues could have
1481 * been realloced, in which case the driver uniform storage set up by
1482 * _mesa_associate_uniform_storage() would point to freed memory. Make
1483 * sure that didn't happen.
1485 assert(sanity_param_count
== prog
->Parameters
->NumParameters
);
1490 } /* namespace brw */
1495 * Compile a vertex shader.
1497 * Returns the final assembly and the program's size.
1500 brw_vs_emit(struct brw_context
*brw
,
1501 struct gl_shader_program
*prog
,
1502 struct brw_vs_compile
*c
,
1503 struct brw_vs_prog_data
*prog_data
,
1505 unsigned *final_assembly_size
)
1507 bool start_busy
= false;
1508 float start_time
= 0;
1510 if (unlikely(brw
->perf_debug
)) {
1511 start_busy
= (brw
->batch
.last_bo
&&
1512 drm_intel_bo_busy(brw
->batch
.last_bo
));
1513 start_time
= get_time();
1516 struct brw_shader
*shader
= NULL
;
1518 shader
= (brw_shader
*) prog
->_LinkedShaders
[MESA_SHADER_VERTEX
];
1520 if (unlikely(INTEL_DEBUG
& DEBUG_VS
)) {
1522 printf("GLSL IR for native vertex shader %d:\n", prog
->Name
);
1523 _mesa_print_ir(shader
->ir
, NULL
);
1526 printf("ARB_vertex_program %d for native vertex shader\n",
1527 c
->vp
->program
.Base
.Id
);
1528 _mesa_print_program(&c
->vp
->program
.Base
);
1532 vec4_vs_visitor
v(brw
, c
, prog_data
, prog
, shader
, mem_ctx
);
1535 prog
->LinkStatus
= false;
1536 ralloc_strcat(&prog
->InfoLog
, v
.fail_msg
);
1539 _mesa_problem(NULL
, "Failed to compile vertex shader: %s\n",
1545 vec4_generator
g(brw
, prog
, &c
->vp
->program
.Base
, mem_ctx
,
1546 INTEL_DEBUG
& DEBUG_VS
);
1547 const unsigned *generated
=g
.generate_assembly(&v
.instructions
,
1548 final_assembly_size
);
1550 if (unlikely(brw
->perf_debug
) && shader
) {
1551 if (shader
->compiled_once
) {
1552 brw_vs_debug_recompile(brw
, prog
, &c
->key
);
1554 if (start_busy
&& !drm_intel_bo_busy(brw
->batch
.last_bo
)) {
1555 perf_debug("VS compile took %.03f ms and stalled the GPU\n",
1556 (get_time() - start_time
) * 1000);
1558 shader
->compiled_once
= true;