2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
29 #include "brw_vec4_builder.h"
30 #include "brw_vec4_live_variables.h"
31 #include "brw_dead_control_flow.h"
32 #include "program/prog_parameter.h"
34 #define MAX_INSTRUCTION (1 << 30)
43 memset(this, 0, sizeof(*this));
45 this->file
= BAD_FILE
;
48 src_reg::src_reg(enum brw_reg_file file
, int nr
, const glsl_type
*type
)
54 if (type
&& (type
->is_scalar() || type
->is_vector() || type
->is_matrix()))
55 this->swizzle
= brw_swizzle_for_size(type
->vector_elements
);
57 this->swizzle
= BRW_SWIZZLE_XYZW
;
59 this->type
= brw_type_for_base_type(type
);
62 /** Generic unset register constructor. */
68 src_reg::src_reg(struct ::brw_reg reg
) :
75 src_reg::src_reg(const dst_reg
®
) :
78 this->reladdr
= reg
.reladdr
;
79 this->swizzle
= brw_swizzle_for_mask(reg
.writemask
);
85 memset(this, 0, sizeof(*this));
86 this->file
= BAD_FILE
;
87 this->writemask
= WRITEMASK_XYZW
;
95 dst_reg::dst_reg(enum brw_reg_file file
, int nr
)
103 dst_reg::dst_reg(enum brw_reg_file file
, int nr
, const glsl_type
*type
,
110 this->type
= brw_type_for_base_type(type
);
111 this->writemask
= writemask
;
114 dst_reg::dst_reg(enum brw_reg_file file
, int nr
, brw_reg_type type
,
122 this->writemask
= writemask
;
125 dst_reg::dst_reg(struct ::brw_reg reg
) :
129 this->reladdr
= NULL
;
132 dst_reg::dst_reg(const src_reg
®
) :
135 this->writemask
= brw_mask_for_swizzle(reg
.swizzle
);
136 this->reladdr
= reg
.reladdr
;
140 dst_reg::equals(const dst_reg
&r
) const
142 return (this->backend_reg::equals(r
) &&
143 (reladdr
== r
.reladdr
||
144 (reladdr
&& r
.reladdr
&& reladdr
->equals(*r
.reladdr
))));
148 vec4_instruction::is_send_from_grf()
151 case SHADER_OPCODE_SHADER_TIME_ADD
:
152 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
153 case SHADER_OPCODE_UNTYPED_ATOMIC
:
154 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
155 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
156 case SHADER_OPCODE_TYPED_ATOMIC
:
157 case SHADER_OPCODE_TYPED_SURFACE_READ
:
158 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
159 case VEC4_OPCODE_URB_READ
:
160 case TCS_OPCODE_URB_WRITE
:
161 case TCS_OPCODE_RELEASE_INPUT
:
162 case SHADER_OPCODE_BARRIER
:
170 * Returns true if this instruction's sources and destinations cannot
171 * safely be the same register.
173 * In most cases, a register can be written over safely by the same
174 * instruction that is its last use. For a single instruction, the
175 * sources are dereferenced before writing of the destination starts
178 * However, there are a few cases where this can be problematic:
180 * - Virtual opcodes that translate to multiple instructions in the
181 * code generator: if src == dst and one instruction writes the
182 * destination before a later instruction reads the source, then
183 * src will have been clobbered.
185 * The register allocator uses this information to set up conflicts between
186 * GRF sources and the destination.
189 vec4_instruction::has_source_and_destination_hazard() const
192 case TCS_OPCODE_SET_INPUT_URB_OFFSETS
:
193 case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS
:
194 case TES_OPCODE_ADD_INDIRECT_URB_OFFSET
:
202 vec4_instruction::regs_read(unsigned arg
) const
204 if (src
[arg
].file
== BAD_FILE
)
208 case SHADER_OPCODE_SHADER_TIME_ADD
:
209 case SHADER_OPCODE_UNTYPED_ATOMIC
:
210 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
211 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
212 case SHADER_OPCODE_TYPED_ATOMIC
:
213 case SHADER_OPCODE_TYPED_SURFACE_READ
:
214 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
215 case TCS_OPCODE_URB_WRITE
:
216 return arg
== 0 ? mlen
: 1;
218 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
219 return arg
== 1 ? mlen
: 1;
227 vec4_instruction::can_do_source_mods(const struct gen_device_info
*devinfo
)
229 if (devinfo
->gen
== 6 && is_math())
232 if (is_send_from_grf())
235 if (!backend_instruction::can_do_source_mods())
242 vec4_instruction::can_do_writemask(const struct gen_device_info
*devinfo
)
245 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
246 case VS_OPCODE_PULL_CONSTANT_LOAD
:
247 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7
:
248 case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9
:
249 case TCS_OPCODE_SET_INPUT_URB_OFFSETS
:
250 case TCS_OPCODE_SET_OUTPUT_URB_OFFSETS
:
251 case TES_OPCODE_CREATE_INPUT_READ_HEADER
:
252 case TES_OPCODE_ADD_INDIRECT_URB_OFFSET
:
253 case VEC4_OPCODE_URB_READ
:
254 case SHADER_OPCODE_MOV_INDIRECT
:
257 /* The MATH instruction on Gen6 only executes in align1 mode, which does
258 * not support writemasking.
260 if (devinfo
->gen
== 6 && is_math())
271 vec4_instruction::can_change_types() const
273 return dst
.type
== src
[0].type
&&
274 !src
[0].abs
&& !src
[0].negate
&& !saturate
&&
275 (opcode
== BRW_OPCODE_MOV
||
276 (opcode
== BRW_OPCODE_SEL
&&
277 dst
.type
== src
[1].type
&&
278 predicate
!= BRW_PREDICATE_NONE
&&
279 !src
[1].abs
&& !src
[1].negate
));
283 * Returns how many MRFs an opcode will write over.
285 * Note that this is not the 0 or 1 implied writes in an actual gen
286 * instruction -- the generate_* functions generate additional MOVs
290 vec4_visitor::implied_mrf_writes(vec4_instruction
*inst
)
292 if (inst
->mlen
== 0 || inst
->is_send_from_grf())
295 switch (inst
->opcode
) {
296 case SHADER_OPCODE_RCP
:
297 case SHADER_OPCODE_RSQ
:
298 case SHADER_OPCODE_SQRT
:
299 case SHADER_OPCODE_EXP2
:
300 case SHADER_OPCODE_LOG2
:
301 case SHADER_OPCODE_SIN
:
302 case SHADER_OPCODE_COS
:
304 case SHADER_OPCODE_INT_QUOTIENT
:
305 case SHADER_OPCODE_INT_REMAINDER
:
306 case SHADER_OPCODE_POW
:
307 case TCS_OPCODE_THREAD_END
:
309 case VS_OPCODE_URB_WRITE
:
311 case VS_OPCODE_PULL_CONSTANT_LOAD
:
313 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
315 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
317 case GS_OPCODE_URB_WRITE
:
318 case GS_OPCODE_URB_WRITE_ALLOCATE
:
319 case GS_OPCODE_THREAD_END
:
321 case GS_OPCODE_FF_SYNC
:
323 case TCS_OPCODE_URB_WRITE
:
325 case SHADER_OPCODE_SHADER_TIME_ADD
:
327 case SHADER_OPCODE_TEX
:
328 case SHADER_OPCODE_TXL
:
329 case SHADER_OPCODE_TXD
:
330 case SHADER_OPCODE_TXF
:
331 case SHADER_OPCODE_TXF_CMS
:
332 case SHADER_OPCODE_TXF_CMS_W
:
333 case SHADER_OPCODE_TXF_MCS
:
334 case SHADER_OPCODE_TXS
:
335 case SHADER_OPCODE_TG4
:
336 case SHADER_OPCODE_TG4_OFFSET
:
337 case SHADER_OPCODE_SAMPLEINFO
:
338 case VS_OPCODE_GET_BUFFER_SIZE
:
339 return inst
->header_size
;
341 unreachable("not reached");
346 src_reg::equals(const src_reg
&r
) const
348 return (this->backend_reg::equals(r
) &&
349 !reladdr
&& !r
.reladdr
);
353 vec4_visitor::opt_vector_float()
355 bool progress
= false;
357 foreach_block(block
, cfg
) {
358 int last_reg
= -1, last_reg_offset
= -1;
359 enum brw_reg_file last_reg_file
= BAD_FILE
;
361 uint8_t imm
[4] = { 0 };
363 vec4_instruction
*imm_inst
[4];
364 unsigned writemask
= 0;
365 enum brw_reg_type dest_type
= BRW_REGISTER_TYPE_F
;
367 foreach_inst_in_block_safe(vec4_instruction
, inst
, block
) {
369 enum brw_reg_type need_type
;
371 /* Look for unconditional MOVs from an immediate with a partial
372 * writemask. Skip type-conversion MOVs other than integer 0,
373 * where the type doesn't matter. See if the immediate can be
374 * represented as a VF.
376 if (inst
->opcode
== BRW_OPCODE_MOV
&&
377 inst
->src
[0].file
== IMM
&&
378 inst
->predicate
== BRW_PREDICATE_NONE
&&
379 inst
->dst
.writemask
!= WRITEMASK_XYZW
&&
380 (inst
->src
[0].type
== inst
->dst
.type
|| inst
->src
[0].d
== 0)) {
382 vf
= brw_float_to_vf(inst
->src
[0].d
);
383 need_type
= BRW_REGISTER_TYPE_D
;
386 vf
= brw_float_to_vf(inst
->src
[0].f
);
387 need_type
= BRW_REGISTER_TYPE_F
;
393 /* If this wasn't a MOV, or the destination register doesn't match,
394 * or we have to switch destination types, then this breaks our
395 * sequence. Combine anything we've accumulated so far.
397 if (last_reg
!= inst
->dst
.nr
||
398 last_reg_offset
!= inst
->dst
.offset
/ REG_SIZE
||
399 last_reg_file
!= inst
->dst
.file
||
400 (vf
> 0 && dest_type
!= need_type
)) {
402 if (inst_count
> 1) {
404 memcpy(&vf
, imm
, sizeof(vf
));
405 vec4_instruction
*mov
= MOV(imm_inst
[0]->dst
, brw_imm_vf(vf
));
406 mov
->dst
.type
= dest_type
;
407 mov
->dst
.writemask
= writemask
;
408 inst
->insert_before(block
, mov
);
410 for (int i
= 0; i
< inst_count
; i
++) {
411 imm_inst
[i
]->remove(block
);
420 dest_type
= BRW_REGISTER_TYPE_F
;
422 for (int i
= 0; i
< 4; i
++) {
427 /* Record this instruction's value (if it was representable). */
429 if ((inst
->dst
.writemask
& WRITEMASK_X
) != 0)
431 if ((inst
->dst
.writemask
& WRITEMASK_Y
) != 0)
433 if ((inst
->dst
.writemask
& WRITEMASK_Z
) != 0)
435 if ((inst
->dst
.writemask
& WRITEMASK_W
) != 0)
438 writemask
|= inst
->dst
.writemask
;
439 imm_inst
[inst_count
++] = inst
;
441 last_reg
= inst
->dst
.nr
;
442 last_reg_offset
= inst
->dst
.offset
/ REG_SIZE
;
443 last_reg_file
= inst
->dst
.file
;
445 dest_type
= need_type
;
451 invalidate_live_intervals();
456 /* Replaces unused channels of a swizzle with channels that are used.
458 * For instance, this pass transforms
460 * mov vgrf4.yz, vgrf5.wxzy
464 * mov vgrf4.yz, vgrf5.xxzx
466 * This eliminates false uses of some channels, letting dead code elimination
467 * remove the instructions that wrote them.
470 vec4_visitor::opt_reduce_swizzle()
472 bool progress
= false;
474 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
475 if (inst
->dst
.file
== BAD_FILE
||
476 inst
->dst
.file
== ARF
||
477 inst
->dst
.file
== FIXED_GRF
||
478 inst
->is_send_from_grf())
483 /* Determine which channels of the sources are read. */
484 switch (inst
->opcode
) {
485 case VEC4_OPCODE_PACK_BYTES
:
487 case BRW_OPCODE_DPH
: /* FINISHME: DPH reads only three channels of src0,
488 * but all four of src1.
490 swizzle
= brw_swizzle_for_size(4);
493 swizzle
= brw_swizzle_for_size(3);
496 swizzle
= brw_swizzle_for_size(2);
499 swizzle
= brw_swizzle_for_mask(inst
->dst
.writemask
);
503 /* Update sources' swizzles. */
504 for (int i
= 0; i
< 3; i
++) {
505 if (inst
->src
[i
].file
!= VGRF
&&
506 inst
->src
[i
].file
!= ATTR
&&
507 inst
->src
[i
].file
!= UNIFORM
)
510 const unsigned new_swizzle
=
511 brw_compose_swizzle(swizzle
, inst
->src
[i
].swizzle
);
512 if (inst
->src
[i
].swizzle
!= new_swizzle
) {
513 inst
->src
[i
].swizzle
= new_swizzle
;
520 invalidate_live_intervals();
526 vec4_visitor::split_uniform_registers()
528 /* Prior to this, uniforms have been in an array sized according to
529 * the number of vector uniforms present, sparsely filled (so an
530 * aggregate results in reg indices being skipped over). Now we're
531 * going to cut those aggregates up so each .nr index is one
532 * vector. The goal is to make elimination of unused uniform
533 * components easier later.
535 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
536 for (int i
= 0 ; i
< 3; i
++) {
537 if (inst
->src
[i
].file
!= UNIFORM
)
540 assert(!inst
->src
[i
].reladdr
);
542 inst
->src
[i
].nr
+= inst
->src
[i
].offset
/ 16;
543 inst
->src
[i
].offset
%= 16;
549 vec4_visitor::pack_uniform_registers()
551 uint8_t chans_used
[this->uniforms
];
552 int new_loc
[this->uniforms
];
553 int new_chan
[this->uniforms
];
555 memset(chans_used
, 0, sizeof(chans_used
));
556 memset(new_loc
, 0, sizeof(new_loc
));
557 memset(new_chan
, 0, sizeof(new_chan
));
559 /* Find which uniform vectors are actually used by the program. We
560 * expect unused vector elements when we've moved array access out
561 * to pull constants, and from some GLSL code generators like wine.
563 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
565 switch (inst
->opcode
) {
566 case VEC4_OPCODE_PACK_BYTES
:
578 readmask
= inst
->dst
.writemask
;
582 for (int i
= 0 ; i
< 3; i
++) {
583 if (inst
->src
[i
].file
!= UNIFORM
)
586 int reg
= inst
->src
[i
].nr
;
587 for (int c
= 0; c
< 4; c
++) {
588 if (!(readmask
& (1 << c
)))
591 chans_used
[reg
] = MAX2(chans_used
[reg
],
592 BRW_GET_SWZ(inst
->src
[i
].swizzle
, c
) + 1);
596 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&&
597 inst
->src
[0].file
== UNIFORM
) {
598 assert(inst
->src
[2].file
== BRW_IMMEDIATE_VALUE
);
599 assert(inst
->src
[0].subnr
== 0);
601 unsigned bytes_read
= inst
->src
[2].ud
;
602 assert(bytes_read
% 4 == 0);
603 unsigned vec4s_read
= DIV_ROUND_UP(bytes_read
, 16);
605 /* We just mark every register touched by a MOV_INDIRECT as being
606 * fully used. This ensures that it doesn't broken up piecewise by
607 * the next part of our packing algorithm.
609 int reg
= inst
->src
[0].nr
;
610 for (unsigned i
= 0; i
< vec4s_read
; i
++)
611 chans_used
[reg
+ i
] = 4;
615 int new_uniform_count
= 0;
617 /* Now, figure out a packing of the live uniform vectors into our
620 for (int src
= 0; src
< uniforms
; src
++) {
621 int size
= chans_used
[src
];
627 /* Find the lowest place we can slot this uniform in. */
628 for (dst
= 0; dst
< src
; dst
++) {
629 if (chans_used
[dst
] + size
<= 4)
638 new_chan
[src
] = chans_used
[dst
];
640 /* Move the references to the data */
641 for (int j
= 0; j
< size
; j
++) {
642 stage_prog_data
->param
[dst
* 4 + new_chan
[src
] + j
] =
643 stage_prog_data
->param
[src
* 4 + j
];
646 chans_used
[dst
] += size
;
650 new_uniform_count
= MAX2(new_uniform_count
, dst
+ 1);
653 this->uniforms
= new_uniform_count
;
655 /* Now, update the instructions for our repacked uniforms. */
656 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
657 for (int i
= 0 ; i
< 3; i
++) {
658 int src
= inst
->src
[i
].nr
;
660 if (inst
->src
[i
].file
!= UNIFORM
)
663 inst
->src
[i
].nr
= new_loc
[src
];
664 inst
->src
[i
].swizzle
+= BRW_SWIZZLE4(new_chan
[src
], new_chan
[src
],
665 new_chan
[src
], new_chan
[src
]);
671 * Does algebraic optimizations (0 * a = 0, 1 * a = a, a + 0 = a).
673 * While GLSL IR also performs this optimization, we end up with it in
674 * our instruction stream for a couple of reasons. One is that we
675 * sometimes generate silly instructions, for example in array access
676 * where we'll generate "ADD offset, index, base" even if base is 0.
677 * The other is that GLSL IR's constant propagation doesn't track the
678 * components of aggregates, so some VS patterns (initialize matrix to
679 * 0, accumulate in vertex blending factors) end up breaking down to
680 * instructions involving 0.
683 vec4_visitor::opt_algebraic()
685 bool progress
= false;
687 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
688 switch (inst
->opcode
) {
690 if (inst
->src
[0].file
!= IMM
)
693 if (inst
->saturate
) {
694 if (inst
->dst
.type
!= inst
->src
[0].type
)
695 assert(!"unimplemented: saturate mixed types");
697 if (brw_saturate_immediate(inst
->dst
.type
,
698 &inst
->src
[0].as_brw_reg())) {
699 inst
->saturate
= false;
705 case VEC4_OPCODE_UNPACK_UNIFORM
:
706 if (inst
->src
[0].file
!= UNIFORM
) {
707 inst
->opcode
= BRW_OPCODE_MOV
;
713 if (inst
->src
[1].is_zero()) {
714 inst
->opcode
= BRW_OPCODE_MOV
;
715 inst
->src
[1] = src_reg();
721 if (inst
->src
[1].is_zero()) {
722 inst
->opcode
= BRW_OPCODE_MOV
;
723 switch (inst
->src
[0].type
) {
724 case BRW_REGISTER_TYPE_F
:
725 inst
->src
[0] = brw_imm_f(0.0f
);
727 case BRW_REGISTER_TYPE_D
:
728 inst
->src
[0] = brw_imm_d(0);
730 case BRW_REGISTER_TYPE_UD
:
731 inst
->src
[0] = brw_imm_ud(0u);
734 unreachable("not reached");
736 inst
->src
[1] = src_reg();
738 } else if (inst
->src
[1].is_one()) {
739 inst
->opcode
= BRW_OPCODE_MOV
;
740 inst
->src
[1] = src_reg();
742 } else if (inst
->src
[1].is_negative_one()) {
743 inst
->opcode
= BRW_OPCODE_MOV
;
744 inst
->src
[0].negate
= !inst
->src
[0].negate
;
745 inst
->src
[1] = src_reg();
750 if (inst
->conditional_mod
== BRW_CONDITIONAL_GE
&&
752 inst
->src
[0].negate
&&
753 inst
->src
[1].is_zero()) {
754 inst
->src
[0].abs
= false;
755 inst
->src
[0].negate
= false;
756 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
761 case SHADER_OPCODE_BROADCAST
:
762 if (is_uniform(inst
->src
[0]) ||
763 inst
->src
[1].is_zero()) {
764 inst
->opcode
= BRW_OPCODE_MOV
;
765 inst
->src
[1] = src_reg();
766 inst
->force_writemask_all
= true;
777 invalidate_live_intervals();
783 * Only a limited number of hardware registers may be used for push
784 * constants, so this turns access to the overflowed constants into
788 vec4_visitor::move_push_constants_to_pull_constants()
790 int pull_constant_loc
[this->uniforms
];
792 /* Only allow 32 registers (256 uniform components) as push constants,
793 * which is the limit on gen6.
795 * If changing this value, note the limitation about total_regs in
798 int max_uniform_components
= 32 * 8;
799 if (this->uniforms
* 4 <= max_uniform_components
)
802 /* Make some sort of choice as to which uniforms get sent to pull
803 * constants. We could potentially do something clever here like
804 * look for the most infrequently used uniform vec4s, but leave
807 for (int i
= 0; i
< this->uniforms
* 4; i
+= 4) {
808 pull_constant_loc
[i
/ 4] = -1;
810 if (i
>= max_uniform_components
) {
811 const gl_constant_value
**values
= &stage_prog_data
->param
[i
];
813 /* Try to find an existing copy of this uniform in the pull
814 * constants if it was part of an array access already.
816 for (unsigned int j
= 0; j
< stage_prog_data
->nr_pull_params
; j
+= 4) {
819 for (matches
= 0; matches
< 4; matches
++) {
820 if (stage_prog_data
->pull_param
[j
+ matches
] != values
[matches
])
825 pull_constant_loc
[i
/ 4] = j
/ 4;
830 if (pull_constant_loc
[i
/ 4] == -1) {
831 assert(stage_prog_data
->nr_pull_params
% 4 == 0);
832 pull_constant_loc
[i
/ 4] = stage_prog_data
->nr_pull_params
/ 4;
834 for (int j
= 0; j
< 4; j
++) {
835 stage_prog_data
->pull_param
[stage_prog_data
->nr_pull_params
++] =
842 /* Now actually rewrite usage of the things we've moved to pull
845 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
846 for (int i
= 0 ; i
< 3; i
++) {
847 if (inst
->src
[i
].file
!= UNIFORM
||
848 pull_constant_loc
[inst
->src
[i
].nr
] == -1)
851 int uniform
= inst
->src
[i
].nr
;
853 dst_reg temp
= dst_reg(this, glsl_type::vec4_type
);
855 emit_pull_constant_load(block
, inst
, temp
, inst
->src
[i
],
856 pull_constant_loc
[uniform
], src_reg());
858 inst
->src
[i
].file
= temp
.file
;
859 inst
->src
[i
].nr
= temp
.nr
;
860 inst
->src
[i
].offset
%= 16;
861 inst
->src
[i
].reladdr
= NULL
;
865 /* Repack push constants to remove the now-unused ones. */
866 pack_uniform_registers();
869 /* Conditions for which we want to avoid setting the dependency control bits */
871 vec4_visitor::is_dep_ctrl_unsafe(const vec4_instruction
*inst
)
873 #define IS_DWORD(reg) \
874 (reg.type == BRW_REGISTER_TYPE_UD || \
875 reg.type == BRW_REGISTER_TYPE_D)
877 /* "When source or destination datatype is 64b or operation is integer DWord
878 * multiply, DepCtrl must not be used."
879 * May apply to future SoCs as well.
881 if (devinfo
->is_cherryview
) {
882 if (inst
->opcode
== BRW_OPCODE_MUL
&&
883 IS_DWORD(inst
->src
[0]) &&
884 IS_DWORD(inst
->src
[1]))
889 if (devinfo
->gen
>= 8) {
890 if (inst
->opcode
== BRW_OPCODE_F32TO16
)
896 * In the presence of send messages, totally interrupt dependency
897 * control. They're long enough that the chance of dependency
898 * control around them just doesn't matter.
901 * From the Ivy Bridge PRM, volume 4 part 3.7, page 80:
902 * When a sequence of NoDDChk and NoDDClr are used, the last instruction that
903 * completes the scoreboard clear must have a non-zero execution mask. This
904 * means, if any kind of predication can change the execution mask or channel
905 * enable of the last instruction, the optimization must be avoided. This is
906 * to avoid instructions being shot down the pipeline when no writes are
910 * Dependency control does not work well over math instructions.
911 * NB: Discovered empirically
913 return (inst
->mlen
|| inst
->predicate
|| inst
->is_math());
917 * Sets the dependency control fields on instructions after register
918 * allocation and before the generator is run.
920 * When you have a sequence of instructions like:
922 * DP4 temp.x vertex uniform[0]
923 * DP4 temp.y vertex uniform[0]
924 * DP4 temp.z vertex uniform[0]
925 * DP4 temp.w vertex uniform[0]
927 * The hardware doesn't know that it can actually run the later instructions
928 * while the previous ones are in flight, producing stalls. However, we have
929 * manual fields we can set in the instructions that let it do so.
932 vec4_visitor::opt_set_dependency_control()
934 vec4_instruction
*last_grf_write
[BRW_MAX_GRF
];
935 uint8_t grf_channels_written
[BRW_MAX_GRF
];
936 vec4_instruction
*last_mrf_write
[BRW_MAX_GRF
];
937 uint8_t mrf_channels_written
[BRW_MAX_GRF
];
939 assert(prog_data
->total_grf
||
940 !"Must be called after register allocation");
942 foreach_block (block
, cfg
) {
943 memset(last_grf_write
, 0, sizeof(last_grf_write
));
944 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
946 foreach_inst_in_block (vec4_instruction
, inst
, block
) {
947 /* If we read from a register that we were doing dependency control
948 * on, don't do dependency control across the read.
950 for (int i
= 0; i
< 3; i
++) {
951 int reg
= inst
->src
[i
].nr
+ inst
->src
[i
].offset
/ REG_SIZE
;
952 if (inst
->src
[i
].file
== VGRF
) {
953 last_grf_write
[reg
] = NULL
;
954 } else if (inst
->src
[i
].file
== FIXED_GRF
) {
955 memset(last_grf_write
, 0, sizeof(last_grf_write
));
958 assert(inst
->src
[i
].file
!= MRF
);
961 if (is_dep_ctrl_unsafe(inst
)) {
962 memset(last_grf_write
, 0, sizeof(last_grf_write
));
963 memset(last_mrf_write
, 0, sizeof(last_mrf_write
));
967 /* Now, see if we can do dependency control for this instruction
968 * against a previous one writing to its destination.
970 int reg
= inst
->dst
.nr
+ inst
->dst
.offset
/ REG_SIZE
;
971 if (inst
->dst
.file
== VGRF
|| inst
->dst
.file
== FIXED_GRF
) {
972 if (last_grf_write
[reg
] &&
973 !(inst
->dst
.writemask
& grf_channels_written
[reg
])) {
974 last_grf_write
[reg
]->no_dd_clear
= true;
975 inst
->no_dd_check
= true;
977 grf_channels_written
[reg
] = 0;
980 last_grf_write
[reg
] = inst
;
981 grf_channels_written
[reg
] |= inst
->dst
.writemask
;
982 } else if (inst
->dst
.file
== MRF
) {
983 if (last_mrf_write
[reg
] &&
984 !(inst
->dst
.writemask
& mrf_channels_written
[reg
])) {
985 last_mrf_write
[reg
]->no_dd_clear
= true;
986 inst
->no_dd_check
= true;
988 mrf_channels_written
[reg
] = 0;
991 last_mrf_write
[reg
] = inst
;
992 mrf_channels_written
[reg
] |= inst
->dst
.writemask
;
999 vec4_instruction::can_reswizzle(const struct gen_device_info
*devinfo
,
1004 /* Gen6 MATH instructions can not execute in align16 mode, so swizzles
1007 if (devinfo
->gen
== 6 && is_math() && swizzle
!= BRW_SWIZZLE_XYZW
)
1010 if (!can_do_writemask(devinfo
) && dst_writemask
!= WRITEMASK_XYZW
)
1013 /* If this instruction sets anything not referenced by swizzle, then we'd
1014 * totally break it when we reswizzle.
1016 if (dst
.writemask
& ~swizzle_mask
)
1022 for (int i
= 0; i
< 3; i
++) {
1023 if (src
[i
].is_accumulator())
1031 * For any channels in the swizzle's source that were populated by this
1032 * instruction, rewrite the instruction to put the appropriate result directly
1033 * in those channels.
1035 * e.g. for swizzle=yywx, MUL a.xy b c -> MUL a.yy_x b.yy z.yy_x
1038 vec4_instruction::reswizzle(int dst_writemask
, int swizzle
)
1040 /* Destination write mask doesn't correspond to source swizzle for the dot
1041 * product and pack_bytes instructions.
1043 if (opcode
!= BRW_OPCODE_DP4
&& opcode
!= BRW_OPCODE_DPH
&&
1044 opcode
!= BRW_OPCODE_DP3
&& opcode
!= BRW_OPCODE_DP2
&&
1045 opcode
!= VEC4_OPCODE_PACK_BYTES
) {
1046 for (int i
= 0; i
< 3; i
++) {
1047 if (src
[i
].file
== BAD_FILE
|| src
[i
].file
== IMM
)
1050 src
[i
].swizzle
= brw_compose_swizzle(swizzle
, src
[i
].swizzle
);
1054 /* Apply the specified swizzle and writemask to the original mask of
1055 * written components.
1057 dst
.writemask
= dst_writemask
&
1058 brw_apply_swizzle_to_mask(swizzle
, dst
.writemask
);
1062 * Tries to reduce extra MOV instructions by taking temporary GRFs that get
1063 * just written and then MOVed into another reg and making the original write
1064 * of the GRF write directly to the final destination instead.
1067 vec4_visitor::opt_register_coalesce()
1069 bool progress
= false;
1072 calculate_live_intervals();
1074 foreach_block_and_inst_safe (block
, vec4_instruction
, inst
, cfg
) {
1078 if (inst
->opcode
!= BRW_OPCODE_MOV
||
1079 (inst
->dst
.file
!= VGRF
&& inst
->dst
.file
!= MRF
) ||
1081 inst
->src
[0].file
!= VGRF
||
1082 inst
->dst
.type
!= inst
->src
[0].type
||
1083 inst
->src
[0].abs
|| inst
->src
[0].negate
|| inst
->src
[0].reladdr
)
1086 /* Remove no-op MOVs */
1087 if (inst
->dst
.file
== inst
->src
[0].file
&&
1088 inst
->dst
.nr
== inst
->src
[0].nr
&&
1089 inst
->dst
.offset
/ REG_SIZE
== inst
->src
[0].offset
/ REG_SIZE
) {
1090 bool is_nop_mov
= true;
1092 for (unsigned c
= 0; c
< 4; c
++) {
1093 if ((inst
->dst
.writemask
& (1 << c
)) == 0)
1096 if (BRW_GET_SWZ(inst
->src
[0].swizzle
, c
) != c
) {
1103 inst
->remove(block
);
1109 bool to_mrf
= (inst
->dst
.file
== MRF
);
1111 /* Can't coalesce this GRF if someone else was going to
1114 if (var_range_end(var_from_reg(alloc
, dst_reg(inst
->src
[0])), 4) > ip
)
1117 /* We need to check interference with the final destination between this
1118 * instruction and the earliest instruction involved in writing the GRF
1119 * we're eliminating. To do that, keep track of which of our source
1120 * channels we've seen initialized.
1122 const unsigned chans_needed
=
1123 brw_apply_inv_swizzle_to_mask(inst
->src
[0].swizzle
,
1124 inst
->dst
.writemask
);
1125 unsigned chans_remaining
= chans_needed
;
1127 /* Now walk up the instruction stream trying to see if we can rewrite
1128 * everything writing to the temporary to write into the destination
1131 vec4_instruction
*_scan_inst
= (vec4_instruction
*)inst
->prev
;
1132 foreach_inst_in_block_reverse_starting_from(vec4_instruction
, scan_inst
,
1134 _scan_inst
= scan_inst
;
1136 if (inst
->src
[0].in_range(scan_inst
->dst
, DIV_ROUND_UP(scan_inst
->size_written
, REG_SIZE
))) {
1137 /* Found something writing to the reg we want to coalesce away. */
1139 /* SEND instructions can't have MRF as a destination. */
1140 if (scan_inst
->mlen
)
1143 if (devinfo
->gen
== 6) {
1144 /* gen6 math instructions must have the destination be
1145 * VGRF, so no compute-to-MRF for them.
1147 if (scan_inst
->is_math()) {
1153 /* This doesn't handle saturation on the instruction we
1154 * want to coalesce away if the register types do not match.
1155 * But if scan_inst is a non type-converting 'mov', we can fix
1158 if (inst
->saturate
&&
1159 inst
->dst
.type
!= scan_inst
->dst
.type
&&
1160 !(scan_inst
->opcode
== BRW_OPCODE_MOV
&&
1161 scan_inst
->dst
.type
== scan_inst
->src
[0].type
))
1164 /* If we can't handle the swizzle, bail. */
1165 if (!scan_inst
->can_reswizzle(devinfo
, inst
->dst
.writemask
,
1166 inst
->src
[0].swizzle
,
1171 /* This doesn't handle coalescing of multiple registers. */
1172 if (scan_inst
->size_written
> REG_SIZE
)
1175 /* Mark which channels we found unconditional writes for. */
1176 if (!scan_inst
->predicate
)
1177 chans_remaining
&= ~scan_inst
->dst
.writemask
;
1179 if (chans_remaining
== 0)
1183 /* You can't read from an MRF, so if someone else reads our MRF's
1184 * source GRF that we wanted to rewrite, that stops us. If it's a
1185 * GRF we're trying to coalesce to, we don't actually handle
1186 * rewriting sources so bail in that case as well.
1188 bool interfered
= false;
1189 for (int i
= 0; i
< 3; i
++) {
1190 if (inst
->src
[0].in_range(scan_inst
->src
[i
],
1191 scan_inst
->regs_read(i
)))
1197 /* If somebody else writes the same channels of our destination here,
1198 * we can't coalesce before that.
1200 if (inst
->dst
.in_range(scan_inst
->dst
, DIV_ROUND_UP(scan_inst
->size_written
, REG_SIZE
)) &&
1201 (inst
->dst
.writemask
& scan_inst
->dst
.writemask
) != 0) {
1205 /* Check for reads of the register we're trying to coalesce into. We
1206 * can't go rewriting instructions above that to put some other value
1207 * in the register instead.
1209 if (to_mrf
&& scan_inst
->mlen
> 0) {
1210 if (inst
->dst
.nr
>= scan_inst
->base_mrf
&&
1211 inst
->dst
.nr
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
1215 for (int i
= 0; i
< 3; i
++) {
1216 if (inst
->dst
.in_range(scan_inst
->src
[i
],
1217 scan_inst
->regs_read(i
)))
1225 if (chans_remaining
== 0) {
1226 /* If we've made it here, we have an MOV we want to coalesce out, and
1227 * a scan_inst pointing to the earliest instruction involved in
1228 * computing the value. Now go rewrite the instruction stream
1231 vec4_instruction
*scan_inst
= _scan_inst
;
1232 while (scan_inst
!= inst
) {
1233 if (scan_inst
->dst
.file
== VGRF
&&
1234 scan_inst
->dst
.nr
== inst
->src
[0].nr
&&
1235 scan_inst
->dst
.offset
/ REG_SIZE
==
1236 inst
->src
[0].offset
/ REG_SIZE
) {
1237 scan_inst
->reswizzle(inst
->dst
.writemask
,
1238 inst
->src
[0].swizzle
);
1239 scan_inst
->dst
.file
= inst
->dst
.file
;
1240 scan_inst
->dst
.nr
= inst
->dst
.nr
;
1241 scan_inst
->dst
.offset
= scan_inst
->dst
.offset
% REG_SIZE
+
1242 ROUND_DOWN_TO(inst
->dst
.offset
, REG_SIZE
);
1243 if (inst
->saturate
&&
1244 inst
->dst
.type
!= scan_inst
->dst
.type
) {
1245 /* If we have reached this point, scan_inst is a non
1246 * type-converting 'mov' and we can modify its register types
1247 * to match the ones in inst. Otherwise, we could have an
1248 * incorrect saturation result.
1250 scan_inst
->dst
.type
= inst
->dst
.type
;
1251 scan_inst
->src
[0].type
= inst
->src
[0].type
;
1253 scan_inst
->saturate
|= inst
->saturate
;
1255 scan_inst
= (vec4_instruction
*)scan_inst
->next
;
1257 inst
->remove(block
);
1263 invalidate_live_intervals();
1269 * Eliminate FIND_LIVE_CHANNEL instructions occurring outside any control
1270 * flow. We could probably do better here with some form of divergence
1274 vec4_visitor::eliminate_find_live_channel()
1276 bool progress
= false;
1279 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
1280 switch (inst
->opcode
) {
1286 case BRW_OPCODE_ENDIF
:
1287 case BRW_OPCODE_WHILE
:
1291 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
1293 inst
->opcode
= BRW_OPCODE_MOV
;
1294 inst
->src
[0] = brw_imm_d(0);
1295 inst
->force_writemask_all
= true;
1309 * Splits virtual GRFs requesting more than one contiguous physical register.
1311 * We initially create large virtual GRFs for temporary structures, arrays,
1312 * and matrices, so that the dereference visitor functions can add reg_offsets
1313 * to work their way down to the actual member being accessed. But when it
1314 * comes to optimization, we'd like to treat each register as individual
1315 * storage if possible.
1317 * So far, the only thing that might prevent splitting is a send message from
1321 vec4_visitor::split_virtual_grfs()
1323 int num_vars
= this->alloc
.count
;
1324 int new_virtual_grf
[num_vars
];
1325 bool split_grf
[num_vars
];
1327 memset(new_virtual_grf
, 0, sizeof(new_virtual_grf
));
1329 /* Try to split anything > 0 sized. */
1330 for (int i
= 0; i
< num_vars
; i
++) {
1331 split_grf
[i
] = this->alloc
.sizes
[i
] != 1;
1334 /* Check that the instructions are compatible with the registers we're trying
1337 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1338 if (inst
->dst
.file
== VGRF
&& regs_written(inst
) > 1)
1339 split_grf
[inst
->dst
.nr
] = false;
1341 for (int i
= 0; i
< 3; i
++) {
1342 if (inst
->src
[i
].file
== VGRF
&& regs_read(inst
, i
) > 1)
1343 split_grf
[inst
->src
[i
].nr
] = false;
1347 /* Allocate new space for split regs. Note that the virtual
1348 * numbers will be contiguous.
1350 for (int i
= 0; i
< num_vars
; i
++) {
1354 new_virtual_grf
[i
] = alloc
.allocate(1);
1355 for (unsigned j
= 2; j
< this->alloc
.sizes
[i
]; j
++) {
1356 unsigned reg
= alloc
.allocate(1);
1357 assert(reg
== new_virtual_grf
[i
] + j
- 1);
1360 this->alloc
.sizes
[i
] = 1;
1363 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1364 if (inst
->dst
.file
== VGRF
&& split_grf
[inst
->dst
.nr
] &&
1365 inst
->dst
.offset
/ REG_SIZE
!= 0) {
1366 inst
->dst
.nr
= (new_virtual_grf
[inst
->dst
.nr
] +
1367 inst
->dst
.offset
/ REG_SIZE
- 1);
1368 inst
->dst
.offset
%= REG_SIZE
;
1370 for (int i
= 0; i
< 3; i
++) {
1371 if (inst
->src
[i
].file
== VGRF
&& split_grf
[inst
->src
[i
].nr
] &&
1372 inst
->src
[i
].offset
/ REG_SIZE
!= 0) {
1373 inst
->src
[i
].nr
= (new_virtual_grf
[inst
->src
[i
].nr
] +
1374 inst
->src
[i
].offset
/ REG_SIZE
- 1);
1375 inst
->src
[i
].offset
%= REG_SIZE
;
1379 invalidate_live_intervals();
1383 vec4_visitor::dump_instruction(backend_instruction
*be_inst
)
1385 dump_instruction(be_inst
, stderr
);
1389 vec4_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
1391 vec4_instruction
*inst
= (vec4_instruction
*)be_inst
;
1393 if (inst
->predicate
) {
1394 fprintf(file
, "(%cf0.%d%s) ",
1395 inst
->predicate_inverse
? '-' : '+',
1397 pred_ctrl_align16
[inst
->predicate
]);
1400 fprintf(file
, "%s", brw_instruction_name(devinfo
, inst
->opcode
));
1402 fprintf(file
, ".sat");
1403 if (inst
->conditional_mod
) {
1404 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
1405 if (!inst
->predicate
&&
1406 (devinfo
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
1407 inst
->opcode
!= BRW_OPCODE_IF
&&
1408 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
1409 fprintf(file
, ".f0.%d", inst
->flag_subreg
);
1414 switch (inst
->dst
.file
) {
1416 fprintf(file
, "vgrf%d.%d", inst
->dst
.nr
, inst
->dst
.offset
/ REG_SIZE
);
1419 fprintf(file
, "g%d", inst
->dst
.nr
);
1422 fprintf(file
, "m%d", inst
->dst
.nr
);
1425 switch (inst
->dst
.nr
) {
1427 fprintf(file
, "null");
1429 case BRW_ARF_ADDRESS
:
1430 fprintf(file
, "a0.%d", inst
->dst
.subnr
);
1432 case BRW_ARF_ACCUMULATOR
:
1433 fprintf(file
, "acc%d", inst
->dst
.subnr
);
1436 fprintf(file
, "f%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
1439 fprintf(file
, "arf%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
1442 if (inst
->dst
.subnr
)
1443 fprintf(file
, "+%d", inst
->dst
.subnr
);
1446 fprintf(file
, "(null)");
1451 unreachable("not reached");
1453 if (inst
->dst
.writemask
!= WRITEMASK_XYZW
) {
1455 if (inst
->dst
.writemask
& 1)
1457 if (inst
->dst
.writemask
& 2)
1459 if (inst
->dst
.writemask
& 4)
1461 if (inst
->dst
.writemask
& 8)
1464 fprintf(file
, ":%s", brw_reg_type_letters(inst
->dst
.type
));
1466 if (inst
->src
[0].file
!= BAD_FILE
)
1467 fprintf(file
, ", ");
1469 for (int i
= 0; i
< 3 && inst
->src
[i
].file
!= BAD_FILE
; i
++) {
1470 if (inst
->src
[i
].negate
)
1472 if (inst
->src
[i
].abs
)
1474 switch (inst
->src
[i
].file
) {
1476 fprintf(file
, "vgrf%d", inst
->src
[i
].nr
);
1479 fprintf(file
, "g%d", inst
->src
[i
].nr
);
1482 fprintf(file
, "attr%d", inst
->src
[i
].nr
);
1485 fprintf(file
, "u%d", inst
->src
[i
].nr
);
1488 switch (inst
->src
[i
].type
) {
1489 case BRW_REGISTER_TYPE_F
:
1490 fprintf(file
, "%fF", inst
->src
[i
].f
);
1492 case BRW_REGISTER_TYPE_D
:
1493 fprintf(file
, "%dD", inst
->src
[i
].d
);
1495 case BRW_REGISTER_TYPE_UD
:
1496 fprintf(file
, "%uU", inst
->src
[i
].ud
);
1498 case BRW_REGISTER_TYPE_VF
:
1499 fprintf(file
, "[%-gF, %-gF, %-gF, %-gF]",
1500 brw_vf_to_float((inst
->src
[i
].ud
>> 0) & 0xff),
1501 brw_vf_to_float((inst
->src
[i
].ud
>> 8) & 0xff),
1502 brw_vf_to_float((inst
->src
[i
].ud
>> 16) & 0xff),
1503 brw_vf_to_float((inst
->src
[i
].ud
>> 24) & 0xff));
1506 fprintf(file
, "???");
1511 switch (inst
->src
[i
].nr
) {
1513 fprintf(file
, "null");
1515 case BRW_ARF_ADDRESS
:
1516 fprintf(file
, "a0.%d", inst
->src
[i
].subnr
);
1518 case BRW_ARF_ACCUMULATOR
:
1519 fprintf(file
, "acc%d", inst
->src
[i
].subnr
);
1522 fprintf(file
, "f%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
1525 fprintf(file
, "arf%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
1528 if (inst
->src
[i
].subnr
)
1529 fprintf(file
, "+%d", inst
->src
[i
].subnr
);
1532 fprintf(file
, "(null)");
1535 unreachable("not reached");
1538 /* Don't print .0; and only VGRFs have reg_offsets and sizes */
1539 if (inst
->src
[i
].offset
/ REG_SIZE
!= 0 &&
1540 inst
->src
[i
].file
== VGRF
&&
1541 alloc
.sizes
[inst
->src
[i
].nr
] != 1)
1542 fprintf(file
, ".%d", inst
->src
[i
].offset
/ REG_SIZE
);
1544 if (inst
->src
[i
].file
!= IMM
) {
1545 static const char *chans
[4] = {"x", "y", "z", "w"};
1547 for (int c
= 0; c
< 4; c
++) {
1548 fprintf(file
, "%s", chans
[BRW_GET_SWZ(inst
->src
[i
].swizzle
, c
)]);
1552 if (inst
->src
[i
].abs
)
1555 if (inst
->src
[i
].file
!= IMM
) {
1556 fprintf(file
, ":%s", brw_reg_type_letters(inst
->src
[i
].type
));
1559 if (i
< 2 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
1560 fprintf(file
, ", ");
1563 if (inst
->force_writemask_all
)
1564 fprintf(file
, " NoMask");
1566 fprintf(file
, "\n");
1570 static inline struct brw_reg
1571 attribute_to_hw_reg(int attr
, bool interleaved
)
1574 return stride(brw_vec4_grf(attr
/ 2, (attr
% 2) * 4), 0, 4, 1);
1576 return brw_vec8_grf(attr
, 0);
1581 * Replace each register of type ATTR in this->instructions with a reference
1582 * to a fixed HW register.
1584 * If interleaved is true, then each attribute takes up half a register, with
1585 * register N containing attribute 2*N in its first half and attribute 2*N+1
1586 * in its second half (this corresponds to the payload setup used by geometry
1587 * shaders in "single" or "dual instanced" dispatch mode). If interleaved is
1588 * false, then each attribute takes up a whole register, with register N
1589 * containing attribute N (this corresponds to the payload setup used by
1590 * vertex shaders, and by geometry shaders in "dual object" dispatch mode).
1593 vec4_visitor::lower_attributes_to_hw_regs(const int *attribute_map
,
1596 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1597 for (int i
= 0; i
< 3; i
++) {
1598 if (inst
->src
[i
].file
!= ATTR
)
1601 int grf
= attribute_map
[inst
->src
[i
].nr
+
1602 inst
->src
[i
].offset
/ REG_SIZE
];
1604 /* All attributes used in the shader need to have been assigned a
1605 * hardware register by the caller
1609 struct brw_reg reg
= attribute_to_hw_reg(grf
, interleaved
);
1610 reg
.swizzle
= inst
->src
[i
].swizzle
;
1611 reg
.type
= inst
->src
[i
].type
;
1612 if (inst
->src
[i
].abs
)
1614 if (inst
->src
[i
].negate
)
1623 vec4_vs_visitor::setup_attributes(int payload_reg
)
1626 int attribute_map
[VERT_ATTRIB_MAX
+ 2];
1627 memset(attribute_map
, 0, sizeof(attribute_map
));
1630 for (int i
= 0; i
< VERT_ATTRIB_MAX
; i
++) {
1631 if (vs_prog_data
->inputs_read
& BITFIELD64_BIT(i
)) {
1632 attribute_map
[i
] = payload_reg
+ nr_attributes
;
1637 /* VertexID is stored by the VF as the last vertex element, but we
1638 * don't represent it with a flag in inputs_read, so we call it
1641 if (vs_prog_data
->uses_vertexid
|| vs_prog_data
->uses_instanceid
||
1642 vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
) {
1643 attribute_map
[VERT_ATTRIB_MAX
] = payload_reg
+ nr_attributes
;
1647 if (vs_prog_data
->uses_drawid
) {
1648 attribute_map
[VERT_ATTRIB_MAX
+ 1] = payload_reg
+ nr_attributes
;
1652 lower_attributes_to_hw_regs(attribute_map
, false /* interleaved */);
1654 return payload_reg
+ vs_prog_data
->nr_attributes
;
1658 vec4_visitor::setup_uniforms(int reg
)
1660 prog_data
->base
.dispatch_grf_start_reg
= reg
;
1662 /* The pre-gen6 VS requires that some push constants get loaded no
1663 * matter what, or the GPU would hang.
1665 if (devinfo
->gen
< 6 && this->uniforms
== 0) {
1666 stage_prog_data
->param
=
1667 reralloc(NULL
, stage_prog_data
->param
, const gl_constant_value
*, 4);
1668 for (unsigned int i
= 0; i
< 4; i
++) {
1669 unsigned int slot
= this->uniforms
* 4 + i
;
1670 static gl_constant_value zero
= { 0.0 };
1671 stage_prog_data
->param
[slot
] = &zero
;
1677 reg
+= ALIGN(uniforms
, 2) / 2;
1680 stage_prog_data
->nr_params
= this->uniforms
* 4;
1682 prog_data
->base
.curb_read_length
=
1683 reg
- prog_data
->base
.dispatch_grf_start_reg
;
1689 vec4_vs_visitor::setup_payload(void)
1693 /* The payload always contains important data in g0, which contains
1694 * the URB handles that are passed on to the URB write at the end
1695 * of the thread. So, we always start push constants at g1.
1699 reg
= setup_uniforms(reg
);
1701 reg
= setup_attributes(reg
);
1703 this->first_non_payload_grf
= reg
;
1707 vec4_visitor::lower_minmax()
1709 assert(devinfo
->gen
< 6);
1711 bool progress
= false;
1713 foreach_block_and_inst_safe(block
, vec4_instruction
, inst
, cfg
) {
1714 const vec4_builder
ibld(this, block
, inst
);
1716 if (inst
->opcode
== BRW_OPCODE_SEL
&&
1717 inst
->predicate
== BRW_PREDICATE_NONE
) {
1718 /* FIXME: Using CMP doesn't preserve the NaN propagation semantics of
1719 * the original SEL.L/GE instruction
1721 ibld
.CMP(ibld
.null_reg_d(), inst
->src
[0], inst
->src
[1],
1722 inst
->conditional_mod
);
1723 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1724 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
1731 invalidate_live_intervals();
1737 vec4_visitor::get_timestamp()
1739 assert(devinfo
->gen
>= 7);
1741 src_reg ts
= src_reg(brw_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
1746 BRW_REGISTER_TYPE_UD
,
1747 BRW_VERTICAL_STRIDE_0
,
1749 BRW_HORIZONTAL_STRIDE_4
,
1753 dst_reg dst
= dst_reg(this, glsl_type::uvec4_type
);
1755 vec4_instruction
*mov
= emit(MOV(dst
, ts
));
1756 /* We want to read the 3 fields we care about (mostly field 0, but also 2)
1757 * even if it's not enabled in the dispatch.
1759 mov
->force_writemask_all
= true;
1761 return src_reg(dst
);
1765 vec4_visitor::emit_shader_time_begin()
1767 current_annotation
= "shader time start";
1768 shader_start_time
= get_timestamp();
1772 vec4_visitor::emit_shader_time_end()
1774 current_annotation
= "shader time end";
1775 src_reg shader_end_time
= get_timestamp();
1778 /* Check that there weren't any timestamp reset events (assuming these
1779 * were the only two timestamp reads that happened).
1781 src_reg reset_end
= shader_end_time
;
1782 reset_end
.swizzle
= BRW_SWIZZLE_ZZZZ
;
1783 vec4_instruction
*test
= emit(AND(dst_null_ud(), reset_end
, brw_imm_ud(1u)));
1784 test
->conditional_mod
= BRW_CONDITIONAL_Z
;
1786 emit(IF(BRW_PREDICATE_NORMAL
));
1788 /* Take the current timestamp and get the delta. */
1789 shader_start_time
.negate
= true;
1790 dst_reg diff
= dst_reg(this, glsl_type::uint_type
);
1791 emit(ADD(diff
, shader_start_time
, shader_end_time
));
1793 /* If there were no instructions between the two timestamp gets, the diff
1794 * is 2 cycles. Remove that overhead, so I can forget about that when
1795 * trying to determine the time taken for single instructions.
1797 emit(ADD(diff
, src_reg(diff
), brw_imm_ud(-2u)));
1799 emit_shader_time_write(0, src_reg(diff
));
1800 emit_shader_time_write(1, brw_imm_ud(1u));
1801 emit(BRW_OPCODE_ELSE
);
1802 emit_shader_time_write(2, brw_imm_ud(1u));
1803 emit(BRW_OPCODE_ENDIF
);
1807 vec4_visitor::emit_shader_time_write(int shader_time_subindex
, src_reg value
)
1810 dst_reg(this, glsl_type::get_array_instance(glsl_type::vec4_type
, 2));
1812 dst_reg offset
= dst
;
1814 time
.offset
+= REG_SIZE
;
1816 offset
.type
= BRW_REGISTER_TYPE_UD
;
1817 int index
= shader_time_index
* 3 + shader_time_subindex
;
1818 emit(MOV(offset
, brw_imm_d(index
* SHADER_TIME_STRIDE
)));
1820 time
.type
= BRW_REGISTER_TYPE_UD
;
1821 emit(MOV(time
, value
));
1823 vec4_instruction
*inst
=
1824 emit(SHADER_OPCODE_SHADER_TIME_ADD
, dst_reg(), src_reg(dst
));
1829 vec4_visitor::convert_to_hw_regs()
1831 foreach_block_and_inst(block
, vec4_instruction
, inst
, cfg
) {
1832 for (int i
= 0; i
< 3; i
++) {
1833 struct src_reg
&src
= inst
->src
[i
];
1837 reg
= brw_vec8_grf(src
.nr
+ src
.offset
/ REG_SIZE
, 0);
1838 reg
.type
= src
.type
;
1839 reg
.swizzle
= src
.swizzle
;
1841 reg
.negate
= src
.negate
;
1845 reg
= stride(brw_vec4_grf(prog_data
->base
.dispatch_grf_start_reg
+
1846 (src
.nr
+ src
.offset
/ 16) / 2,
1847 ((src
.nr
+ src
.offset
/ 16) % 2) * 4),
1849 reg
.type
= src
.type
;
1850 reg
.swizzle
= src
.swizzle
;
1852 reg
.negate
= src
.negate
;
1854 /* This should have been moved to pull constants. */
1855 assert(!src
.reladdr
);
1864 /* Probably unused. */
1865 reg
= brw_null_reg();
1870 unreachable("not reached");
1876 if (inst
->is_3src(devinfo
)) {
1877 /* 3-src instructions with scalar sources support arbitrary subnr,
1878 * but don't actually use swizzles. Convert swizzle into subnr.
1880 for (int i
= 0; i
< 3; i
++) {
1881 if (inst
->src
[i
].vstride
== BRW_VERTICAL_STRIDE_0
) {
1882 assert(brw_is_single_value_swizzle(inst
->src
[i
].swizzle
));
1883 inst
->src
[i
].subnr
+= 4 * BRW_GET_SWZ(inst
->src
[i
].swizzle
, 0);
1888 dst_reg
&dst
= inst
->dst
;
1891 switch (inst
->dst
.file
) {
1893 reg
= brw_vec8_grf(dst
.nr
+ dst
.offset
/ REG_SIZE
, 0);
1894 reg
.type
= dst
.type
;
1895 reg
.writemask
= dst
.writemask
;
1899 assert(((dst
.nr
+ dst
.offset
/ REG_SIZE
) & ~BRW_MRF_COMPR4
) < BRW_MAX_MRF(devinfo
->gen
));
1900 reg
= brw_message_reg(dst
.nr
+ dst
.offset
/ REG_SIZE
);
1901 reg
.type
= dst
.type
;
1902 reg
.writemask
= dst
.writemask
;
1907 reg
= dst
.as_brw_reg();
1911 reg
= brw_null_reg();
1917 unreachable("not reached");
1927 if (shader_time_index
>= 0)
1928 emit_shader_time_begin();
1941 /* Before any optimization, push array accesses out to scratch
1942 * space where we need them to be. This pass may allocate new
1943 * virtual GRFs, so we want to do it early. It also makes sure
1944 * that we have reladdr computations available for CSE, since we'll
1945 * often do repeated subexpressions for those.
1947 move_grf_array_access_to_scratch();
1948 move_uniform_array_access_to_pull_constants();
1950 pack_uniform_registers();
1951 move_push_constants_to_pull_constants();
1952 split_virtual_grfs();
1954 #define OPT(pass, args...) ({ \
1956 bool this_progress = pass(args); \
1958 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
1959 char filename[64]; \
1960 snprintf(filename, 64, "%s-%s-%02d-%02d-" #pass, \
1961 stage_abbrev, nir->info.name, iteration, pass_num); \
1963 backend_shader::dump_instructions(filename); \
1966 progress = progress || this_progress; \
1971 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
1973 snprintf(filename
, 64, "%s-%s-00-00-start",
1974 stage_abbrev
, nir
->info
.name
);
1976 backend_shader::dump_instructions(filename
);
1987 OPT(opt_predicated_break
, this);
1988 OPT(opt_reduce_swizzle
);
1989 OPT(dead_code_eliminate
);
1990 OPT(dead_control_flow_eliminate
, this);
1991 OPT(opt_copy_propagation
);
1992 OPT(opt_cmod_propagation
);
1995 OPT(opt_register_coalesce
);
1996 OPT(eliminate_find_live_channel
);
2001 if (OPT(opt_vector_float
)) {
2003 OPT(opt_copy_propagation
, false);
2004 OPT(opt_copy_propagation
, true);
2005 OPT(dead_code_eliminate
);
2008 if (devinfo
->gen
<= 5 && OPT(lower_minmax
)) {
2009 OPT(opt_cmod_propagation
);
2011 OPT(opt_copy_propagation
);
2012 OPT(dead_code_eliminate
);
2020 if (unlikely(INTEL_DEBUG
& DEBUG_SPILL_VEC4
)) {
2021 /* Debug of register spilling: Go spill everything. */
2022 const int grf_count
= alloc
.count
;
2023 float spill_costs
[alloc
.count
];
2024 bool no_spill
[alloc
.count
];
2025 evaluate_spill_costs(spill_costs
, no_spill
);
2026 for (int i
= 0; i
< grf_count
; i
++) {
2033 bool allocated_without_spills
= reg_allocate();
2035 if (!allocated_without_spills
) {
2036 compiler
->shader_perf_log(log_data
,
2037 "%s shader triggered register spilling. "
2038 "Try reducing the number of live vec4 values "
2039 "to improve performance.\n",
2042 while (!reg_allocate()) {
2048 opt_schedule_instructions();
2050 opt_set_dependency_control();
2052 convert_to_hw_regs();
2054 if (last_scratch
> 0) {
2055 prog_data
->base
.total_scratch
=
2056 brw_get_scratch_size(last_scratch
* REG_SIZE
);
2062 } /* namespace brw */
2067 * Compile a vertex shader.
2069 * Returns the final assembly and the program's size.
2072 brw_compile_vs(const struct brw_compiler
*compiler
, void *log_data
,
2074 const struct brw_vs_prog_key
*key
,
2075 struct brw_vs_prog_data
*prog_data
,
2076 const nir_shader
*src_shader
,
2077 gl_clip_plane
*clip_planes
,
2078 bool use_legacy_snorm_formula
,
2079 int shader_time_index
,
2080 unsigned *final_assembly_size
,
2083 const bool is_scalar
= compiler
->scalar_stage
[MESA_SHADER_VERTEX
];
2084 nir_shader
*shader
= nir_shader_clone(mem_ctx
, src_shader
);
2085 shader
= brw_nir_apply_sampler_key(shader
, compiler
->devinfo
, &key
->tex
,
2087 brw_nir_lower_vs_inputs(shader
, compiler
->devinfo
, is_scalar
,
2088 use_legacy_snorm_formula
, key
->gl_attrib_wa_flags
);
2089 brw_nir_lower_vue_outputs(shader
, is_scalar
);
2090 shader
= brw_postprocess_nir(shader
, compiler
->devinfo
, is_scalar
);
2092 const unsigned *assembly
= NULL
;
2094 unsigned nr_attributes
= _mesa_bitcount_64(prog_data
->inputs_read
);
2096 /* gl_VertexID and gl_InstanceID are system values, but arrive via an
2097 * incoming vertex attribute. So, add an extra slot.
2099 if (shader
->info
.system_values_read
&
2100 (BITFIELD64_BIT(SYSTEM_VALUE_BASE_VERTEX
) |
2101 BITFIELD64_BIT(SYSTEM_VALUE_BASE_INSTANCE
) |
2102 BITFIELD64_BIT(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
) |
2103 BITFIELD64_BIT(SYSTEM_VALUE_INSTANCE_ID
))) {
2107 /* gl_DrawID has its very own vec4 */
2108 if (shader
->info
.system_values_read
& BITFIELD64_BIT(SYSTEM_VALUE_DRAW_ID
)) {
2112 unsigned nr_attribute_slots
=
2114 _mesa_bitcount_64(shader
->info
.double_inputs_read
);
2116 /* The 3DSTATE_VS documentation lists the lower bound on "Vertex URB Entry
2117 * Read Length" as 1 in vec4 mode, and 0 in SIMD8 mode. Empirically, in
2118 * vec4 mode, the hardware appears to wedge unless we read something.
2121 prog_data
->base
.urb_read_length
=
2122 DIV_ROUND_UP(nr_attribute_slots
, 2);
2124 prog_data
->base
.urb_read_length
=
2125 DIV_ROUND_UP(MAX2(nr_attribute_slots
, 1), 2);
2127 prog_data
->nr_attributes
= nr_attributes
;
2128 prog_data
->nr_attribute_slots
= nr_attribute_slots
;
2130 /* Since vertex shaders reuse the same VUE entry for inputs and outputs
2131 * (overwriting the original contents), we need to make sure the size is
2132 * the larger of the two.
2134 const unsigned vue_entries
=
2135 MAX2(nr_attribute_slots
, (unsigned)prog_data
->base
.vue_map
.num_slots
);
2137 if (compiler
->devinfo
->gen
== 6)
2138 prog_data
->base
.urb_entry_size
= DIV_ROUND_UP(vue_entries
, 8);
2140 prog_data
->base
.urb_entry_size
= DIV_ROUND_UP(vue_entries
, 4);
2143 prog_data
->base
.dispatch_mode
= DISPATCH_MODE_SIMD8
;
2145 fs_visitor
v(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
.base
,
2146 NULL
, /* prog; Only used for TEXTURE_RECTANGLE on gen < 8 */
2147 shader
, 8, shader_time_index
);
2148 if (!v
.run_vs(clip_planes
)) {
2150 *error_str
= ralloc_strdup(mem_ctx
, v
.fail_msg
);
2155 prog_data
->base
.base
.dispatch_grf_start_reg
= v
.payload
.num_regs
;
2157 fs_generator
g(compiler
, log_data
, mem_ctx
, (void *) key
,
2158 &prog_data
->base
.base
, v
.promoted_constants
,
2159 v
.runtime_check_aads_emit
, MESA_SHADER_VERTEX
);
2160 if (INTEL_DEBUG
& DEBUG_VS
) {
2161 const char *debug_name
=
2162 ralloc_asprintf(mem_ctx
, "%s vertex shader %s",
2163 shader
->info
.label
? shader
->info
.label
: "unnamed",
2166 g
.enable_debug(debug_name
);
2168 g
.generate_code(v
.cfg
, 8);
2169 assembly
= g
.get_assembly(final_assembly_size
);
2173 prog_data
->base
.dispatch_mode
= DISPATCH_MODE_4X2_DUAL_OBJECT
;
2175 vec4_vs_visitor
v(compiler
, log_data
, key
, prog_data
,
2176 shader
, clip_planes
, mem_ctx
,
2177 shader_time_index
, use_legacy_snorm_formula
);
2180 *error_str
= ralloc_strdup(mem_ctx
, v
.fail_msg
);
2185 assembly
= brw_vec4_generate_assembly(compiler
, log_data
, mem_ctx
,
2186 shader
, &prog_data
->base
, v
.cfg
,
2187 final_assembly_size
);