src/mesa/drivers/dri/i965/brw_vec4.h

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #ifndef BRW_VEC4_H
  25 #define BRW_VEC4_H
  26
  27 #include <stdint.h>
  28 #include "brw_shader.h"
  29 #include "main/compiler.h"
  30 #include "program/hash_table.h"
  31 #include "brw_program.h"
  32
  33 #ifdef __cplusplus
  34 extern "C" {
  35 #endif
  36
  37 #include "brw_context.h"
  38 #include "brw_eu.h"
  39 #include "intel_asm_printer.h"
  40
  41 #ifdef __cplusplus
  42 }; /* extern "C" */
  43 #include "gen8_generator.h"
  44 #endif
  45
  46 #include "glsl/ir.h"
  47
  48
  49 struct brw_vec4_compile {
  50    GLuint last_scratch; /**< measured in 32-byte (register size) units */
  51 };
  52
  53
  54 struct brw_vec4_prog_key {
  55    GLuint program_string_id;
  56
  57    /**
  58     * True if at least one clip flag is enabled, regardless of whether the
  59     * shader uses clip planes or gl_ClipDistance.
  60     */
  61    GLuint userclip_active:1;
  62
  63    /**
  64     * How many user clipping planes are being uploaded to the vertex shader as
  65     * push constants.
  66     */
  67    GLuint nr_userclip_plane_consts:4;
  68
  69    GLuint clamp_vertex_color:1;
  70
  71    struct brw_sampler_prog_key_data tex;
  72 };
  73
  74
  75 #ifdef __cplusplus
  76 extern "C" {
  77 #endif
  78
  79 void
  80 brw_vec4_setup_prog_key_for_precompile(struct gl_context *ctx,
  81                                        struct brw_vec4_prog_key *key,
  82                                        GLuint id, struct gl_program *prog);
  83
  84 #ifdef __cplusplus
  85 } /* extern "C" */
  86
  87 namespace brw {
  88
  89 class dst_reg;
  90
  91 unsigned
  92 swizzle_for_size(int size);
  93
  94 class src_reg : public backend_reg
  95 {
  96 public:
  97    DECLARE_RALLOC_CXX_OPERATORS(src_reg)
  98
  99    void init();
 100
 101    src_reg(register_file file, int reg, const glsl_type *type);
 102    src_reg();
 103    src_reg(float f);
 104    src_reg(uint32_t u);
 105    src_reg(int32_t i);
 106    src_reg(struct brw_reg reg);
 107
 108    bool equals(const src_reg &r) const;
 109
 110    src_reg(class vec4_visitor *v, const struct glsl_type *type);
 111
 112    explicit src_reg(dst_reg reg);
 113
 114    GLuint swizzle; /**< BRW_SWIZZLE_XYZW macros from brw_reg.h. */
 115
 116    src_reg *reladdr;
 117 };
 118
 119 static inline src_reg
 120 retype(src_reg reg, unsigned type)
 121 {
 122    reg.fixed_hw_reg.type = reg.type = type;
 123    return reg;
 124 }
 125
 126 static inline src_reg
 127 offset(src_reg reg, unsigned delta)
 128 {
 129    assert(delta == 0 || (reg.file != HW_REG && reg.file != IMM));
 130    reg.reg_offset += delta;
 131    return reg;
 132 }
 133
 134 /**
 135  * Reswizzle a given source register.
 136  * \sa brw_swizzle().
 137  */
 138 static inline src_reg
 139 swizzle(src_reg reg, unsigned swizzle)
 140 {
 141    assert(reg.file != HW_REG);
 142    reg.swizzle = BRW_SWIZZLE4(
 143       BRW_GET_SWZ(reg.swizzle, BRW_GET_SWZ(swizzle, 0)),
 144       BRW_GET_SWZ(reg.swizzle, BRW_GET_SWZ(swizzle, 1)),
 145       BRW_GET_SWZ(reg.swizzle, BRW_GET_SWZ(swizzle, 2)),
 146       BRW_GET_SWZ(reg.swizzle, BRW_GET_SWZ(swizzle, 3)));
 147    return reg;
 148 }
 149
 150 static inline src_reg
 151 negate(src_reg reg)
 152 {
 153    assert(reg.file != HW_REG && reg.file != IMM);
 154    reg.negate = !reg.negate;
 155    return reg;
 156 }
 157
 158 class dst_reg : public backend_reg
 159 {
 160 public:
 161    DECLARE_RALLOC_CXX_OPERATORS(dst_reg)
 162
 163    void init();
 164
 165    dst_reg();
 166    dst_reg(register_file file, int reg);
 167    dst_reg(register_file file, int reg, const glsl_type *type, int writemask);
 168    dst_reg(struct brw_reg reg);
 169    dst_reg(class vec4_visitor *v, const struct glsl_type *type);
 170
 171    explicit dst_reg(src_reg reg);
 172
 173    int writemask; /**< Bitfield of WRITEMASK_[XYZW] */
 174
 175    src_reg *reladdr;
 176 };
 177
 178 static inline dst_reg
 179 retype(dst_reg reg, unsigned type)
 180 {
 181    reg.fixed_hw_reg.type = reg.type = type;
 182    return reg;
 183 }
 184
 185 static inline dst_reg
 186 offset(dst_reg reg, unsigned delta)
 187 {
 188    assert(delta == 0 || (reg.file != HW_REG && reg.file != IMM));
 189    reg.reg_offset += delta;
 190    return reg;
 191 }
 192
 193 static inline dst_reg
 194 writemask(dst_reg reg, unsigned mask)
 195 {
 196    assert(reg.file != HW_REG && reg.file != IMM);
 197    assert((reg.writemask & mask) != 0);
 198    reg.writemask &= mask;
 199    return reg;
 200 }
 201
 202 class vec4_instruction : public backend_instruction {
 203 public:
 204    DECLARE_RALLOC_CXX_OPERATORS(vec4_instruction)
 205
 206    vec4_instruction(vec4_visitor *v, enum opcode opcode,
 207                     const dst_reg &dst = dst_reg(),
 208                     const src_reg &src0 = src_reg(),
 209                     const src_reg &src1 = src_reg(),
 210                     const src_reg &src2 = src_reg());
 211
 212    struct brw_reg get_dst(void);
 213    struct brw_reg get_src(const struct brw_vec4_prog_data *prog_data, int i);
 214
 215    dst_reg dst;
 216    src_reg src[3];
 217
 218    bool saturate;
 219    bool force_writemask_all;
 220    bool no_dd_clear, no_dd_check;
 221
 222    int conditional_mod; /**< BRW_CONDITIONAL_* */
 223
 224    int sampler;
 225    uint32_t texture_offset; /**< Texture Offset bitfield */
 226    int target; /**< MRT target. */
 227    bool shadow_compare;
 228
 229    enum brw_urb_write_flags urb_write_flags;
 230    bool header_present;
 231    int mlen; /**< SEND message length */
 232    int base_mrf; /**< First MRF in the SEND message, if mlen is nonzero. */
 233
 234    uint32_t offset; /* spill/unspill offset */
 235
 236    bool is_send_from_grf();
 237    bool can_reswizzle_dst(int dst_writemask, int swizzle, int swizzle_mask);
 238    void reswizzle_dst(int dst_writemask, int swizzle);
 239    bool can_do_source_mods(struct brw_context *brw);
 240
 241    bool reads_flag()
 242    {
 243       return predicate || opcode == VS_OPCODE_UNPACK_FLAGS_SIMD4X2;
 244    }
 245
 246    bool writes_flag()
 247    {
 248       return conditional_mod && opcode != BRW_OPCODE_SEL;
 249    }
 250 };
 251
 252 /**
 253  * The vertex shader front-end.
 254  *
 255  * Translates either GLSL IR or Mesa IR (for ARB_vertex_program and
 256  * fixed-function) into VS IR.
 257  */
 258 class vec4_visitor : public backend_visitor
 259 {
 260 public:
 261    vec4_visitor(struct brw_context *brw,
 262                 struct brw_vec4_compile *c,
 263                 struct gl_program *prog,
 264                 const struct brw_vec4_prog_key *key,
 265                 struct brw_vec4_prog_data *prog_data,
 266                 struct gl_shader_program *shader_prog,
 267                 gl_shader_stage stage,
 268                 void *mem_ctx,
 269                 bool debug_flag,
 270                 bool no_spills,
 271                 shader_time_shader_type st_base,
 272                 shader_time_shader_type st_written,
 273                 shader_time_shader_type st_reset);
 274    ~vec4_visitor();
 275
 276    dst_reg dst_null_f()
 277    {
 278       return dst_reg(brw_null_reg());
 279    }
 280
 281    dst_reg dst_null_d()
 282    {
 283       return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
 284    }
 285
 286    dst_reg dst_null_ud()
 287    {
 288       return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD));
 289    }
 290
 291    struct brw_vec4_compile * const c;
 292    const struct brw_vec4_prog_key * const key;
 293    struct brw_vec4_prog_data * const prog_data;
 294    unsigned int sanity_param_count;
 295
 296    char *fail_msg;
 297    bool failed;
 298
 299    /**
 300     * GLSL IR currently being processed, which is associated with our
 301     * driver IR instructions for debugging purposes.
 302     */
 303    const void *base_ir;
 304    const char *current_annotation;
 305
 306    int *virtual_grf_sizes;
 307    int virtual_grf_count;
 308    int virtual_grf_array_size;
 309    int first_non_payload_grf;
 310    unsigned int max_grf;
 311    int *virtual_grf_start;
 312    int *virtual_grf_end;
 313    dst_reg userplane[MAX_CLIP_PLANES];
 314
 315    /**
 316     * This is the size to be used for an array with an element per
 317     * reg_offset
 318     */
 319    int virtual_grf_reg_count;
 320    /** Per-virtual-grf indices into an array of size virtual_grf_reg_count */
 321    int *virtual_grf_reg_map;
 322
 323    bool live_intervals_valid;
 324
 325    dst_reg *variable_storage(ir_variable *var);
 326
 327    void reladdr_to_temp(ir_instruction *ir, src_reg *reg, int *num_reladdr);
 328
 329    bool need_all_constants_in_pull_buffer;
 330
 331    /**
 332     * \name Visit methods
 333     *
 334     * As typical for the visitor pattern, there must be one \c visit method for
 335     * each concrete subclass of \c ir_instruction.  Virtual base classes within
 336     * the hierarchy should not have \c visit methods.
 337     */
 338    /*@{*/
 339    virtual void visit(ir_variable *);
 340    virtual void visit(ir_loop *);
 341    virtual void visit(ir_loop_jump *);
 342    virtual void visit(ir_function_signature *);
 343    virtual void visit(ir_function *);
 344    virtual void visit(ir_expression *);
 345    virtual void visit(ir_swizzle *);
 346    virtual void visit(ir_dereference_variable  *);
 347    virtual void visit(ir_dereference_array *);
 348    virtual void visit(ir_dereference_record *);
 349    virtual void visit(ir_assignment *);
 350    virtual void visit(ir_constant *);
 351    virtual void visit(ir_call *);
 352    virtual void visit(ir_return *);
 353    virtual void visit(ir_discard *);
 354    virtual void visit(ir_texture *);
 355    virtual void visit(ir_if *);
 356    virtual void visit(ir_emit_vertex *);
 357    virtual void visit(ir_end_primitive *);
 358    /*@}*/
 359
 360    src_reg result;
 361
 362    /* Regs for vertex results.  Generated at ir_variable visiting time
 363     * for the ir->location's used.
 364     */
 365    dst_reg output_reg[BRW_VARYING_SLOT_COUNT];
 366    const char *output_reg_annotation[BRW_VARYING_SLOT_COUNT];
 367    int *uniform_size;
 368    int *uniform_vector_size;
 369    int uniform_array_size; /*< Size of uniform_[vector_]size arrays */
 370    int uniforms;
 371
 372    src_reg shader_start_time;
 373
 374    struct hash_table *variable_ht;
 375
 376    bool run(void);
 377    void fail(const char *msg, ...);
 378
 379    int virtual_grf_alloc(int size);
 380    void setup_uniform_clipplane_values();
 381    void setup_uniform_values(ir_variable *ir);
 382    void setup_builtin_uniform_values(ir_variable *ir);
 383    int setup_uniforms(int payload_reg);
 384    bool reg_allocate_trivial();
 385    bool reg_allocate();
 386    void evaluate_spill_costs(float *spill_costs, bool *no_spill);
 387    int choose_spill_reg(struct ra_graph *g);
 388    void spill_reg(int spill_reg);
 389    void move_grf_array_access_to_scratch();
 390    void move_uniform_array_access_to_pull_constants();
 391    void move_push_constants_to_pull_constants();
 392    void split_uniform_registers();
 393    void pack_uniform_registers();
 394    void calculate_live_intervals();
 395    void invalidate_live_intervals();
 396    void split_virtual_grfs();
 397    bool dead_code_eliminate();
 398    bool virtual_grf_interferes(int a, int b);
 399    bool opt_copy_propagation();
 400    bool opt_algebraic();
 401    bool opt_register_coalesce();
 402    void opt_set_dependency_control();
 403    void opt_schedule_instructions();
 404
 405    vec4_instruction *emit(vec4_instruction *inst);
 406
 407    vec4_instruction *emit(enum opcode opcode);
 408
 409    vec4_instruction *emit(enum opcode opcode, dst_reg dst);
 410
 411    vec4_instruction *emit(enum opcode opcode, dst_reg dst, src_reg src0);
 412
 413    vec4_instruction *emit(enum opcode opcode, dst_reg dst,
 414                           src_reg src0, src_reg src1);
 415
 416    vec4_instruction *emit(enum opcode opcode, dst_reg dst,
 417                           src_reg src0, src_reg src1, src_reg src2);
 418
 419    vec4_instruction *emit_before(vec4_instruction *inst,
 420                                  vec4_instruction *new_inst);
 421
 422    vec4_instruction *MOV(const dst_reg &dst, const src_reg &src0);
 423    vec4_instruction *NOT(const dst_reg &dst, const src_reg &src0);
 424    vec4_instruction *RNDD(const dst_reg &dst, const src_reg &src0);
 425    vec4_instruction *RNDE(const dst_reg &dst, const src_reg &src0);
 426    vec4_instruction *RNDZ(const dst_reg &dst, const src_reg &src0);
 427    vec4_instruction *FRC(const dst_reg &dst, const src_reg &src0);
 428    vec4_instruction *F32TO16(const dst_reg &dst, const src_reg &src0);
 429    vec4_instruction *F16TO32(const dst_reg &dst, const src_reg &src0);
 430    vec4_instruction *ADD(const dst_reg &dst, const src_reg &src0,
 431                          const src_reg &src1);
 432    vec4_instruction *MUL(const dst_reg &dst, const src_reg &src0,
 433                          const src_reg &src1);
 434    vec4_instruction *MACH(const dst_reg &dst, const src_reg &src0,
 435                           const src_reg &src1);
 436    vec4_instruction *MAC(const dst_reg &dst, const src_reg &src0,
 437                          const src_reg &src1);
 438    vec4_instruction *AND(const dst_reg &dst, const src_reg &src0,
 439                          const src_reg &src1);
 440    vec4_instruction *OR(const dst_reg &dst, const src_reg &src0,
 441                         const src_reg &src1);
 442    vec4_instruction *XOR(const dst_reg &dst, const src_reg &src0,
 443                          const src_reg &src1);
 444    vec4_instruction *DP3(const dst_reg &dst, const src_reg &src0,
 445                          const src_reg &src1);
 446    vec4_instruction *DP4(const dst_reg &dst, const src_reg &src0,
 447                          const src_reg &src1);
 448    vec4_instruction *DPH(const dst_reg &dst, const src_reg &src0,
 449                          const src_reg &src1);
 450    vec4_instruction *SHL(const dst_reg &dst, const src_reg &src0,
 451                          const src_reg &src1);
 452    vec4_instruction *SHR(const dst_reg &dst, const src_reg &src0,
 453                          const src_reg &src1);
 454    vec4_instruction *ASR(const dst_reg &dst, const src_reg &src0,
 455                          const src_reg &src1);
 456    vec4_instruction *CMP(dst_reg dst, src_reg src0, src_reg src1,
 457                          uint32_t condition);
 458    vec4_instruction *IF(src_reg src0, src_reg src1, uint32_t condition);
 459    vec4_instruction *IF(uint32_t predicate);
 460    vec4_instruction *PULL_CONSTANT_LOAD(const dst_reg &dst,
 461                                         const src_reg &index);
 462    vec4_instruction *SCRATCH_READ(const dst_reg &dst, const src_reg &index);
 463    vec4_instruction *SCRATCH_WRITE(const dst_reg &dst, const src_reg &src,
 464                                    const src_reg &index);
 465    vec4_instruction *LRP(const dst_reg &dst, const src_reg &a,
 466                          const src_reg &y, const src_reg &x);
 467    vec4_instruction *BFREV(const dst_reg &dst, const src_reg &value);
 468    vec4_instruction *BFE(const dst_reg &dst, const src_reg &bits,
 469                          const src_reg &offset, const src_reg &value);
 470    vec4_instruction *BFI1(const dst_reg &dst, const src_reg &bits,
 471                           const src_reg &offset);
 472    vec4_instruction *BFI2(const dst_reg &dst, const src_reg &bfi1_dst,
 473                           const src_reg &insert, const src_reg &base);
 474    vec4_instruction *FBH(const dst_reg &dst, const src_reg &value);
 475    vec4_instruction *FBL(const dst_reg &dst, const src_reg &value);
 476    vec4_instruction *CBIT(const dst_reg &dst, const src_reg &value);
 477    vec4_instruction *MAD(const dst_reg &dst, const src_reg &c,
 478                          const src_reg &b, const src_reg &a);
 479    vec4_instruction *ADDC(const dst_reg &dst, const src_reg &src0,
 480                           const src_reg &src1);
 481    vec4_instruction *SUBB(const dst_reg &dst, const src_reg &src0,
 482                           const src_reg &src1);
 483
 484    int implied_mrf_writes(vec4_instruction *inst);
 485
 486    bool try_rewrite_rhs_to_dst(ir_assignment *ir,
 487                                dst_reg dst,
 488                                src_reg src,
 489                                vec4_instruction *pre_rhs_inst,
 490                                vec4_instruction *last_rhs_inst);
 491
 492    /** Walks an exec_list of ir_instruction and sends it through this visitor. */
 493    void visit_instructions(const exec_list *list);
 494
 495    void emit_vp_sop(uint32_t condmod, dst_reg dst,
 496                     src_reg src0, src_reg src1, src_reg one);
 497
 498    void emit_bool_to_cond_code(ir_rvalue *ir, uint32_t *predicate);
 499    void emit_bool_comparison(unsigned int op, dst_reg dst, src_reg src0, src_reg src1);
 500    void emit_if_gen6(ir_if *ir);
 501
 502    void emit_minmax(uint32_t condmod, dst_reg dst, src_reg src0, src_reg src1);
 503
 504    void emit_lrp(const dst_reg &dst,
 505                  const src_reg &x, const src_reg &y, const src_reg &a);
 506
 507    void emit_block_move(dst_reg *dst, src_reg *src,
 508                         const struct glsl_type *type, uint32_t predicate);
 509
 510    void emit_constant_values(dst_reg *dst, ir_constant *value);
 511
 512    /**
 513     * Emit the correct dot-product instruction for the type of arguments
 514     */
 515    void emit_dp(dst_reg dst, src_reg src0, src_reg src1, unsigned elements);
 516
 517    void emit_scalar(ir_instruction *ir, enum prog_opcode op,
 518                     dst_reg dst, src_reg src0);
 519
 520    void emit_scalar(ir_instruction *ir, enum prog_opcode op,
 521                     dst_reg dst, src_reg src0, src_reg src1);
 522
 523    void emit_scs(ir_instruction *ir, enum prog_opcode op,
 524                  dst_reg dst, const src_reg &src);
 525
 526    src_reg fix_3src_operand(src_reg src);
 527
 528    void emit_math1_gen6(enum opcode opcode, dst_reg dst, src_reg src);
 529    void emit_math1_gen4(enum opcode opcode, dst_reg dst, src_reg src);
 530    void emit_math(enum opcode opcode, dst_reg dst, src_reg src);
 531    void emit_math2_gen6(enum opcode opcode, dst_reg dst, src_reg src0, src_reg src1);
 532    void emit_math2_gen4(enum opcode opcode, dst_reg dst, src_reg src0, src_reg src1);
 533    void emit_math(enum opcode opcode, dst_reg dst, src_reg src0, src_reg src1);
 534    src_reg fix_math_operand(src_reg src);
 535
 536    void emit_pack_half_2x16(dst_reg dst, src_reg src0);
 537    void emit_unpack_half_2x16(dst_reg dst, src_reg src0);
 538
 539    uint32_t gather_channel(ir_texture *ir, int sampler);
 540    src_reg emit_mcs_fetch(ir_texture *ir, src_reg coordinate, int sampler);
 541    void emit_gen6_gather_wa(uint8_t wa, dst_reg dst);
 542    void swizzle_result(ir_texture *ir, src_reg orig_val, int sampler);
 543
 544    void emit_ndc_computation();
 545    void emit_psiz_and_flags(struct brw_reg reg);
 546    void emit_clip_distances(dst_reg reg, int offset);
 547    void emit_generic_urb_slot(dst_reg reg, int varying);
 548    void emit_urb_slot(int mrf, int varying);
 549
 550    void emit_shader_time_begin();
 551    void emit_shader_time_end();
 552    void emit_shader_time_write(enum shader_time_shader_type type,
 553                                src_reg value);
 554
 555    void emit_untyped_atomic(unsigned atomic_op, unsigned surf_index,
 556                             dst_reg dst, src_reg offset, src_reg src0,
 557                             src_reg src1);
 558
 559    void emit_untyped_surface_read(unsigned surf_index, dst_reg dst,
 560                                   src_reg offset);
 561
 562    src_reg get_scratch_offset(vec4_instruction *inst,
 563                               src_reg *reladdr, int reg_offset);
 564    src_reg get_pull_constant_offset(vec4_instruction *inst,
 565                                     src_reg *reladdr, int reg_offset);
 566    void emit_scratch_read(vec4_instruction *inst,
 567                           dst_reg dst,
 568                           src_reg orig_src,
 569                           int base_offset);
 570    void emit_scratch_write(vec4_instruction *inst,
 571                            int base_offset);
 572    void emit_pull_constant_load(vec4_instruction *inst,
 573                                 dst_reg dst,
 574                                 src_reg orig_src,
 575                                 int base_offset);
 576
 577    bool try_emit_sat(ir_expression *ir);
 578    bool try_emit_mad(ir_expression *ir);
 579    bool try_emit_b2f_of_compare(ir_expression *ir);
 580    void resolve_ud_negate(src_reg *reg);
 581
 582    src_reg get_timestamp();
 583
 584    bool process_move_condition(ir_rvalue *ir);
 585
 586    void dump_instruction(backend_instruction *inst);
 587    void dump_instruction(backend_instruction *inst, FILE *file);
 588
 589    void visit_atomic_counter_intrinsic(ir_call *ir);
 590
 591 protected:
 592    void emit_vertex();
 593    void lower_attributes_to_hw_regs(const int *attribute_map,
 594                                     bool interleaved);
 595    void setup_payload_interference(struct ra_graph *g, int first_payload_node,
 596                                    int reg_node_count);
 597    virtual dst_reg *make_reg_for_system_value(ir_variable *ir) = 0;
 598    virtual void setup_payload() = 0;
 599    virtual void emit_prolog() = 0;
 600    virtual void emit_program_code() = 0;
 601    virtual void emit_thread_end() = 0;
 602    virtual void emit_urb_write_header(int mrf) = 0;
 603    virtual vec4_instruction *emit_urb_write_opcode(bool complete) = 0;
 604    virtual int compute_array_stride(ir_dereference_array *ir);
 605
 606    const bool debug_flag;
 607
 608 private:
 609    /**
 610     * If true, then register allocation should fail instead of spilling.
 611     */
 612    const bool no_spills;
 613
 614    const shader_time_shader_type st_base;
 615    const shader_time_shader_type st_written;
 616    const shader_time_shader_type st_reset;
 617 };
 618
 619
 620 /**
 621  * The vertex shader code generator.
 622  *
 623  * Translates VS IR to actual i965 assembly code.
 624  */
 625 class vec4_generator
 626 {
 627 public:
 628    vec4_generator(struct brw_context *brw,
 629                   struct gl_shader_program *shader_prog,
 630                   struct gl_program *prog,
 631                   struct brw_vec4_prog_data *prog_data,
 632                   void *mem_ctx,
 633                   bool debug_flag);
 634    ~vec4_generator();
 635
 636    const unsigned *generate_assembly(exec_list *insts, unsigned *asm_size);
 637
 638 private:
 639    void generate_code(exec_list *instructions);
 640    void generate_vec4_instruction(vec4_instruction *inst,
 641                                   struct brw_reg dst,
 642                                   struct brw_reg *src);
 643
 644    void generate_math1_gen4(vec4_instruction *inst,
 645                             struct brw_reg dst,
 646                             struct brw_reg src);
 647    void generate_math2_gen4(vec4_instruction *inst,
 648                             struct brw_reg dst,
 649                             struct brw_reg src0,
 650                             struct brw_reg src1);
 651    void generate_math_gen6(vec4_instruction *inst,
 652                            struct brw_reg dst,
 653                            struct brw_reg src0,
 654                            struct brw_reg src1);
 655
 656    void generate_tex(vec4_instruction *inst,
 657                      struct brw_reg dst,
 658                      struct brw_reg src);
 659
 660    void generate_vs_urb_write(vec4_instruction *inst);
 661    void generate_gs_urb_write(vec4_instruction *inst);
 662    void generate_gs_thread_end(vec4_instruction *inst);
 663    void generate_gs_set_write_offset(struct brw_reg dst,
 664                                      struct brw_reg src0,
 665                                      struct brw_reg src1);
 666    void generate_gs_set_vertex_count(struct brw_reg dst,
 667                                      struct brw_reg src);
 668    void generate_gs_set_dword_2_immed(struct brw_reg dst, struct brw_reg src);
 669    void generate_gs_prepare_channel_masks(struct brw_reg dst);
 670    void generate_gs_set_channel_masks(struct brw_reg dst, struct brw_reg src);
 671    void generate_gs_get_instance_id(struct brw_reg dst);
 672    void generate_oword_dual_block_offsets(struct brw_reg m1,
 673                                           struct brw_reg index);
 674    void generate_scratch_write(vec4_instruction *inst,
 675                                struct brw_reg dst,
 676                                struct brw_reg src,
 677                                struct brw_reg index);
 678    void generate_scratch_read(vec4_instruction *inst,
 679                               struct brw_reg dst,
 680                               struct brw_reg index);
 681    void generate_pull_constant_load(vec4_instruction *inst,
 682                                     struct brw_reg dst,
 683                                     struct brw_reg index,
 684                                     struct brw_reg offset);
 685    void generate_pull_constant_load_gen7(vec4_instruction *inst,
 686                                          struct brw_reg dst,
 687                                          struct brw_reg surf_index,
 688                                          struct brw_reg offset);
 689    void generate_unpack_flags(vec4_instruction *inst,
 690                               struct brw_reg dst);
 691
 692    void generate_untyped_atomic(vec4_instruction *inst,
 693                                 struct brw_reg dst,
 694                                 struct brw_reg atomic_op,
 695                                 struct brw_reg surf_index);
 696
 697    void generate_untyped_surface_read(vec4_instruction *inst,
 698                                       struct brw_reg dst,
 699                                       struct brw_reg surf_index);
 700
 701    struct brw_context *brw;
 702
 703    struct brw_compile *p;
 704
 705    struct gl_shader_program *shader_prog;
 706    const struct gl_program *prog;
 707
 708    struct brw_vec4_prog_data *prog_data;
 709
 710    void *mem_ctx;
 711    const bool debug_flag;
 712 };
 713
 714 /**
 715  * The vertex shader code generator.
 716  *
 717  * Translates VS IR to actual i965 assembly code.
 718  */
 719 class gen8_vec4_generator : public gen8_generator
 720 {
 721 public:
 722    gen8_vec4_generator(struct brw_context *brw,
 723                        struct gl_shader_program *shader_prog,
 724                        struct gl_program *prog,
 725                        struct brw_vec4_prog_data *prog_data,
 726                        void *mem_ctx,
 727                        bool debug_flag);
 728    ~gen8_vec4_generator();
 729
 730    const unsigned *generate_assembly(exec_list *insts, unsigned *asm_size);
 731
 732 private:
 733    void generate_code(exec_list *instructions);
 734    void generate_vec4_instruction(vec4_instruction *inst,
 735                                   struct brw_reg dst,
 736                                   struct brw_reg *src);
 737
 738    void generate_tex(vec4_instruction *inst,
 739                      struct brw_reg dst);
 740
 741    void generate_urb_write(vec4_instruction *ir, bool copy_g0);
 742    void generate_gs_thread_end(vec4_instruction *ir);
 743    void generate_gs_set_write_offset(struct brw_reg dst,
 744                                      struct brw_reg src0,
 745                                      struct brw_reg src1);
 746    void generate_gs_set_vertex_count(struct brw_reg dst,
 747                                      struct brw_reg src);
 748    void generate_gs_set_dword_2_immed(struct brw_reg dst, struct brw_reg src);
 749    void generate_gs_prepare_channel_masks(struct brw_reg dst);
 750    void generate_gs_set_channel_masks(struct brw_reg dst, struct brw_reg src);
 751
 752    void generate_oword_dual_block_offsets(struct brw_reg m1,
 753                                           struct brw_reg index);
 754    void generate_scratch_write(vec4_instruction *inst,
 755                                struct brw_reg dst,
 756                                struct brw_reg src,
 757                                struct brw_reg index);
 758    void generate_scratch_read(vec4_instruction *inst,
 759                               struct brw_reg dst,
 760                               struct brw_reg index);
 761    void generate_pull_constant_load(vec4_instruction *inst,
 762                                     struct brw_reg dst,
 763                                     struct brw_reg index,
 764                                     struct brw_reg offset);
 765    void generate_untyped_atomic(vec4_instruction *ir,
 766                                 struct brw_reg dst,
 767                                 struct brw_reg atomic_op,
 768                                 struct brw_reg surf_index);
 769    void generate_untyped_surface_read(vec4_instruction *ir,
 770                                       struct brw_reg dst,
 771                                       struct brw_reg surf_index);
 772
 773    struct brw_vec4_prog_data *prog_data;
 774
 775    const bool debug_flag;
 776 };
 777
 778
 779 } /* namespace brw */
 780 #endif /* __cplusplus */
 781
 782 #endif /* BRW_VEC4_H */