i965/vec4: Replace vec4_instruction::regs_written with ::size_written field in bytes.
[mesa.git] / src / mesa / drivers / dri / i965 / brw_vec4_cmod_propagation.cpp
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 */
24
25 /** @file brw_vec4_cmod_propagation.cpp
26 *
27 * Really similar to brw_fs_cmod_propagation but adapted to vec4 needs. Check
28 * brw_fs_cmod_propagation for further details on the rationale behind this
29 * optimization.
30 */
31
32 #include "brw_vec4.h"
33 #include "brw_cfg.h"
34 #include "brw_eu.h"
35
36 namespace brw {
37
38 static bool
39 opt_cmod_propagation_local(bblock_t *block)
40 {
41 bool progress = false;
42 int ip = block->end_ip + 1;
43
44 foreach_inst_in_block_reverse_safe(vec4_instruction, inst, block) {
45 ip--;
46
47 if ((inst->opcode != BRW_OPCODE_AND &&
48 inst->opcode != BRW_OPCODE_CMP &&
49 inst->opcode != BRW_OPCODE_MOV) ||
50 inst->predicate != BRW_PREDICATE_NONE ||
51 !inst->dst.is_null() ||
52 inst->src[0].file != VGRF ||
53 inst->src[0].abs)
54 continue;
55
56 if (inst->opcode == BRW_OPCODE_AND &&
57 !(inst->src[1].is_one() &&
58 inst->conditional_mod == BRW_CONDITIONAL_NZ &&
59 !inst->src[0].negate))
60 continue;
61
62 if (inst->opcode == BRW_OPCODE_CMP && !inst->src[1].is_zero())
63 continue;
64
65 if (inst->opcode == BRW_OPCODE_MOV &&
66 inst->conditional_mod != BRW_CONDITIONAL_NZ)
67 continue;
68
69 bool read_flag = false;
70 foreach_inst_in_block_reverse_starting_from(vec4_instruction, scan_inst, inst) {
71 if (inst->src[0].in_range(scan_inst->dst,
72 DIV_ROUND_UP(scan_inst->size_written, REG_SIZE))) {
73 if ((scan_inst->predicate && scan_inst->opcode != BRW_OPCODE_SEL) ||
74 scan_inst->dst.offset / REG_SIZE != inst->src[0].offset / REG_SIZE ||
75 (scan_inst->dst.writemask != WRITEMASK_X &&
76 scan_inst->dst.writemask != WRITEMASK_XYZW) ||
77 (scan_inst->dst.writemask == WRITEMASK_XYZW &&
78 inst->src[0].swizzle != BRW_SWIZZLE_XYZW) ||
79 (inst->dst.writemask & ~scan_inst->dst.writemask) != 0) {
80 break;
81 }
82
83 /* CMP's result is the same regardless of dest type. */
84 if (inst->conditional_mod == BRW_CONDITIONAL_NZ &&
85 scan_inst->opcode == BRW_OPCODE_CMP &&
86 (inst->dst.type == BRW_REGISTER_TYPE_D ||
87 inst->dst.type == BRW_REGISTER_TYPE_UD)) {
88 inst->remove(block);
89 progress = true;
90 break;
91 }
92
93 /* If the AND wasn't handled by the previous case, it isn't safe
94 * to remove it.
95 */
96 if (inst->opcode == BRW_OPCODE_AND)
97 break;
98
99 /* Comparisons operate differently for ints and floats */
100 if (scan_inst->dst.type != inst->dst.type &&
101 (scan_inst->dst.type == BRW_REGISTER_TYPE_F ||
102 inst->dst.type == BRW_REGISTER_TYPE_F))
103 break;
104
105 /* If the instruction generating inst's source also wrote the
106 * flag, and inst is doing a simple .nz comparison, then inst
107 * is redundant - the appropriate value is already in the flag
108 * register. Delete inst.
109 */
110 if (inst->conditional_mod == BRW_CONDITIONAL_NZ &&
111 !inst->src[0].negate &&
112 scan_inst->writes_flag()) {
113 inst->remove(block);
114 progress = true;
115 break;
116 }
117
118 /* The conditional mod of the CMP/CMPN instructions behaves
119 * specially because the flag output is not calculated from the
120 * result of the instruction, but the other way around, which
121 * means that even if the condmod to propagate and the condmod
122 * from the CMP instruction are the same they will in general give
123 * different results because they are evaluated based on different
124 * inputs.
125 */
126 if (scan_inst->opcode == BRW_OPCODE_CMP ||
127 scan_inst->opcode == BRW_OPCODE_CMPN)
128 break;
129
130 /* Otherwise, try propagating the conditional. */
131 enum brw_conditional_mod cond =
132 inst->src[0].negate ? brw_swap_cmod(inst->conditional_mod)
133 : inst->conditional_mod;
134
135 if (scan_inst->can_do_cmod() &&
136 ((!read_flag && scan_inst->conditional_mod == BRW_CONDITIONAL_NONE) ||
137 scan_inst->conditional_mod == cond)) {
138 scan_inst->conditional_mod = cond;
139 inst->remove(block);
140 progress = true;
141 }
142 break;
143 }
144
145 if (scan_inst->writes_flag())
146 break;
147
148 read_flag = read_flag || scan_inst->reads_flag();
149 }
150 }
151
152 return progress;
153 }
154
155 bool
156 vec4_visitor::opt_cmod_propagation()
157 {
158 bool progress = false;
159
160 foreach_block_reverse(block, cfg) {
161 progress = opt_cmod_propagation_local(block) || progress;
162 }
163
164 if (progress)
165 invalidate_live_intervals();
166
167 return progress;
168 }
169
170 } /* namespace brw */