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i965/gs: Avoid DW * DW mul
[mesa.git] / src / mesa / drivers / dri / i965 / brw_vec4_generator.cpp
1 /* Copyright © 2011 Intel Corporation
2 *
3 * Permission is hereby granted, free of charge, to any person obtaining a
4 * copy of this software and associated documentation files (the "Software"),
5 * to deal in the Software without restriction, including without limitation
6 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
7 * and/or sell copies of the Software, and to permit persons to whom the
8 * Software is furnished to do so, subject to the following conditions:
9 *
10 * The above copyright notice and this permission notice (including the next
11 * paragraph) shall be included in all copies or substantial portions of the
12 * Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
20 * IN THE SOFTWARE.
21 */
22
23 #include "brw_vec4.h"
24 #include "brw_cfg.h"
25
26 extern "C" {
27 #include "brw_eu.h"
28 #include "main/macros.h"
29 #include "program/prog_print.h"
30 #include "program/prog_parameter.h"
31 };
32
33 namespace brw {
34
35 struct brw_reg
36 vec4_instruction::get_dst(void)
37 {
38 struct brw_reg brw_reg;
39
40 switch (dst.file) {
41 case GRF:
42 brw_reg = brw_vec8_grf(dst.reg + dst.reg_offset, 0);
43 brw_reg = retype(brw_reg, dst.type);
44 brw_reg.dw1.bits.writemask = dst.writemask;
45 break;
46
47 case MRF:
48 brw_reg = brw_message_reg(dst.reg + dst.reg_offset);
49 brw_reg = retype(brw_reg, dst.type);
50 brw_reg.dw1.bits.writemask = dst.writemask;
51 break;
52
53 case HW_REG:
54 assert(dst.type == dst.fixed_hw_reg.type);
55 brw_reg = dst.fixed_hw_reg;
56 break;
57
58 case BAD_FILE:
59 brw_reg = brw_null_reg();
60 break;
61
62 default:
63 unreachable("not reached");
64 }
65 return brw_reg;
66 }
67
68 struct brw_reg
69 vec4_instruction::get_src(const struct brw_vec4_prog_data *prog_data, int i)
70 {
71 struct brw_reg brw_reg;
72
73 switch (src[i].file) {
74 case GRF:
75 brw_reg = brw_vec8_grf(src[i].reg + src[i].reg_offset, 0);
76 brw_reg = retype(brw_reg, src[i].type);
77 brw_reg.dw1.bits.swizzle = src[i].swizzle;
78 if (src[i].abs)
79 brw_reg = brw_abs(brw_reg);
80 if (src[i].negate)
81 brw_reg = negate(brw_reg);
82 break;
83
84 case IMM:
85 switch (src[i].type) {
86 case BRW_REGISTER_TYPE_F:
87 brw_reg = brw_imm_f(src[i].fixed_hw_reg.dw1.f);
88 break;
89 case BRW_REGISTER_TYPE_D:
90 brw_reg = brw_imm_d(src[i].fixed_hw_reg.dw1.d);
91 break;
92 case BRW_REGISTER_TYPE_UD:
93 brw_reg = brw_imm_ud(src[i].fixed_hw_reg.dw1.ud);
94 break;
95 case BRW_REGISTER_TYPE_VF:
96 brw_reg = brw_imm_vf(src[i].fixed_hw_reg.dw1.ud);
97 break;
98 default:
99 unreachable("not reached");
100 }
101 break;
102
103 case UNIFORM:
104 brw_reg = stride(brw_vec4_grf(prog_data->base.dispatch_grf_start_reg +
105 (src[i].reg + src[i].reg_offset) / 2,
106 ((src[i].reg + src[i].reg_offset) % 2) * 4),
107 0, 4, 1);
108 brw_reg = retype(brw_reg, src[i].type);
109 brw_reg.dw1.bits.swizzle = src[i].swizzle;
110 if (src[i].abs)
111 brw_reg = brw_abs(brw_reg);
112 if (src[i].negate)
113 brw_reg = negate(brw_reg);
114
115 /* This should have been moved to pull constants. */
116 assert(!src[i].reladdr);
117 break;
118
119 case HW_REG:
120 assert(src[i].type == src[i].fixed_hw_reg.type);
121 brw_reg = src[i].fixed_hw_reg;
122 break;
123
124 case BAD_FILE:
125 /* Probably unused. */
126 brw_reg = brw_null_reg();
127 break;
128 case ATTR:
129 default:
130 unreachable("not reached");
131 }
132
133 return brw_reg;
134 }
135
136 vec4_generator::vec4_generator(struct brw_context *brw,
137 struct gl_shader_program *shader_prog,
138 struct gl_program *prog,
139 struct brw_vec4_prog_data *prog_data,
140 void *mem_ctx,
141 bool debug_flag)
142 : brw(brw), shader_prog(shader_prog), prog(prog), prog_data(prog_data),
143 mem_ctx(mem_ctx), debug_flag(debug_flag)
144 {
145 p = rzalloc(mem_ctx, struct brw_compile);
146 brw_init_compile(brw, p, mem_ctx);
147 }
148
149 vec4_generator::~vec4_generator()
150 {
151 }
152
153 void
154 vec4_generator::generate_math1_gen4(vec4_instruction *inst,
155 struct brw_reg dst,
156 struct brw_reg src)
157 {
158 gen4_math(p,
159 dst,
160 brw_math_function(inst->opcode),
161 inst->base_mrf,
162 src,
163 BRW_MATH_PRECISION_FULL);
164 }
165
166 static void
167 check_gen6_math_src_arg(struct brw_reg src)
168 {
169 /* Source swizzles are ignored. */
170 assert(!src.abs);
171 assert(!src.negate);
172 assert(src.dw1.bits.swizzle == BRW_SWIZZLE_XYZW);
173 }
174
175 void
176 vec4_generator::generate_math_gen6(vec4_instruction *inst,
177 struct brw_reg dst,
178 struct brw_reg src0,
179 struct brw_reg src1)
180 {
181 /* Can't do writemask because math can't be align16. */
182 assert(dst.dw1.bits.writemask == WRITEMASK_XYZW);
183 /* Source swizzles are ignored. */
184 check_gen6_math_src_arg(src0);
185 if (src1.file == BRW_GENERAL_REGISTER_FILE)
186 check_gen6_math_src_arg(src1);
187
188 brw_set_default_access_mode(p, BRW_ALIGN_1);
189 gen6_math(p, dst, brw_math_function(inst->opcode), src0, src1);
190 brw_set_default_access_mode(p, BRW_ALIGN_16);
191 }
192
193 void
194 vec4_generator::generate_math2_gen4(vec4_instruction *inst,
195 struct brw_reg dst,
196 struct brw_reg src0,
197 struct brw_reg src1)
198 {
199 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
200 * "Message Payload":
201 *
202 * "Operand0[7]. For the INT DIV functions, this operand is the
203 * denominator."
204 * ...
205 * "Operand1[7]. For the INT DIV functions, this operand is the
206 * numerator."
207 */
208 bool is_int_div = inst->opcode != SHADER_OPCODE_POW;
209 struct brw_reg &op0 = is_int_div ? src1 : src0;
210 struct brw_reg &op1 = is_int_div ? src0 : src1;
211
212 brw_push_insn_state(p);
213 brw_set_default_saturate(p, false);
214 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
215 brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), op1.type), op1);
216 brw_pop_insn_state(p);
217
218 gen4_math(p,
219 dst,
220 brw_math_function(inst->opcode),
221 inst->base_mrf,
222 op0,
223 BRW_MATH_PRECISION_FULL);
224 }
225
226 void
227 vec4_generator::generate_tex(vec4_instruction *inst,
228 struct brw_reg dst,
229 struct brw_reg src,
230 struct brw_reg sampler_index)
231 {
232 int msg_type = -1;
233
234 if (brw->gen >= 5) {
235 switch (inst->opcode) {
236 case SHADER_OPCODE_TEX:
237 case SHADER_OPCODE_TXL:
238 if (inst->shadow_compare) {
239 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
240 } else {
241 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
242 }
243 break;
244 case SHADER_OPCODE_TXD:
245 if (inst->shadow_compare) {
246 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
247 assert(brw->gen >= 8 || brw->is_haswell);
248 msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
249 } else {
250 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
251 }
252 break;
253 case SHADER_OPCODE_TXF:
254 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
255 break;
256 case SHADER_OPCODE_TXF_CMS:
257 if (brw->gen >= 7)
258 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
259 else
260 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
261 break;
262 case SHADER_OPCODE_TXF_MCS:
263 assert(brw->gen >= 7);
264 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS;
265 break;
266 case SHADER_OPCODE_TXS:
267 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
268 break;
269 case SHADER_OPCODE_TG4:
270 if (inst->shadow_compare) {
271 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C;
272 } else {
273 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
274 }
275 break;
276 case SHADER_OPCODE_TG4_OFFSET:
277 if (inst->shadow_compare) {
278 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C;
279 } else {
280 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO;
281 }
282 break;
283 default:
284 unreachable("should not get here: invalid vec4 texture opcode");
285 }
286 } else {
287 switch (inst->opcode) {
288 case SHADER_OPCODE_TEX:
289 case SHADER_OPCODE_TXL:
290 if (inst->shadow_compare) {
291 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_COMPARE;
292 assert(inst->mlen == 3);
293 } else {
294 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD;
295 assert(inst->mlen == 2);
296 }
297 break;
298 case SHADER_OPCODE_TXD:
299 /* There is no sample_d_c message; comparisons are done manually. */
300 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS;
301 assert(inst->mlen == 4);
302 break;
303 case SHADER_OPCODE_TXF:
304 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_LD;
305 assert(inst->mlen == 2);
306 break;
307 case SHADER_OPCODE_TXS:
308 msg_type = BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO;
309 assert(inst->mlen == 2);
310 break;
311 default:
312 unreachable("should not get here: invalid vec4 texture opcode");
313 }
314 }
315
316 assert(msg_type != -1);
317
318 assert(sampler_index.type == BRW_REGISTER_TYPE_UD);
319
320 /* Load the message header if present. If there's a texture offset, we need
321 * to set it up explicitly and load the offset bitfield. Otherwise, we can
322 * use an implied move from g0 to the first message register.
323 */
324 if (inst->header_present) {
325 if (brw->gen < 6 && !inst->offset) {
326 /* Set up an implied move from g0 to the MRF. */
327 src = brw_vec8_grf(0, 0);
328 } else {
329 struct brw_reg header =
330 retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD);
331
332 /* Explicitly set up the message header by copying g0 to the MRF. */
333 brw_push_insn_state(p);
334 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
335 brw_MOV(p, header, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
336
337 brw_set_default_access_mode(p, BRW_ALIGN_1);
338
339 if (inst->offset) {
340 /* Set the texel offset bits in DWord 2. */
341 brw_MOV(p, get_element_ud(header, 2),
342 brw_imm_ud(inst->offset));
343 }
344
345 brw_adjust_sampler_state_pointer(p, header, sampler_index, dst);
346 brw_pop_insn_state(p);
347 }
348 }
349
350 uint32_t return_format;
351
352 switch (dst.type) {
353 case BRW_REGISTER_TYPE_D:
354 return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
355 break;
356 case BRW_REGISTER_TYPE_UD:
357 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
358 break;
359 default:
360 return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
361 break;
362 }
363
364 uint32_t base_binding_table_index = (inst->opcode == SHADER_OPCODE_TG4 ||
365 inst->opcode == SHADER_OPCODE_TG4_OFFSET)
366 ? prog_data->base.binding_table.gather_texture_start
367 : prog_data->base.binding_table.texture_start;
368
369 if (sampler_index.file == BRW_IMMEDIATE_VALUE) {
370 uint32_t sampler = sampler_index.dw1.ud;
371
372 brw_SAMPLE(p,
373 dst,
374 inst->base_mrf,
375 src,
376 sampler + base_binding_table_index,
377 sampler % 16,
378 msg_type,
379 1, /* response length */
380 inst->mlen,
381 inst->header_present,
382 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
383 return_format);
384
385 brw_mark_surface_used(&prog_data->base, sampler + base_binding_table_index);
386 } else {
387 /* Non-constant sampler index. */
388 /* Note: this clobbers `dst` as a temporary before emitting the send */
389
390 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
391 struct brw_reg temp = vec1(retype(dst, BRW_REGISTER_TYPE_UD));
392
393 struct brw_reg sampler_reg = vec1(retype(sampler_index, BRW_REGISTER_TYPE_UD));
394
395 brw_push_insn_state(p);
396 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
397 brw_set_default_access_mode(p, BRW_ALIGN_1);
398
399 /* Some care required: `sampler` and `temp` may alias:
400 * addr = sampler & 0xff
401 * temp = (sampler << 8) & 0xf00
402 * addr = addr | temp
403 */
404 brw_ADD(p, addr, sampler_reg, brw_imm_ud(base_binding_table_index));
405 brw_SHL(p, temp, sampler_reg, brw_imm_ud(8u));
406 brw_AND(p, temp, temp, brw_imm_ud(0x0f00));
407 brw_AND(p, addr, addr, brw_imm_ud(0x0ff));
408 brw_OR(p, addr, addr, temp);
409
410 /* a0.0 |= <descriptor> */
411 brw_inst *insn_or = brw_next_insn(p, BRW_OPCODE_OR);
412 brw_set_sampler_message(p, insn_or,
413 0 /* surface */,
414 0 /* sampler */,
415 msg_type,
416 1 /* rlen */,
417 inst->mlen /* mlen */,
418 inst->header_present /* header */,
419 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
420 return_format);
421 brw_inst_set_exec_size(p->brw, insn_or, BRW_EXECUTE_1);
422 brw_inst_set_src1_reg_type(p->brw, insn_or, BRW_REGISTER_TYPE_UD);
423 brw_set_src0(p, insn_or, addr);
424 brw_set_dest(p, insn_or, addr);
425
426
427 /* dst = send(offset, a0.0) */
428 brw_inst *insn_send = brw_next_insn(p, BRW_OPCODE_SEND);
429 brw_set_dest(p, insn_send, dst);
430 brw_set_src0(p, insn_send, src);
431 brw_set_indirect_send_descriptor(p, insn_send, BRW_SFID_SAMPLER, addr);
432
433 brw_pop_insn_state(p);
434
435 /* visitor knows more than we do about the surface limit required,
436 * so has already done marking.
437 */
438 }
439 }
440
441 void
442 vec4_generator::generate_vs_urb_write(vec4_instruction *inst)
443 {
444 brw_urb_WRITE(p,
445 brw_null_reg(), /* dest */
446 inst->base_mrf, /* starting mrf reg nr */
447 brw_vec8_grf(0, 0), /* src */
448 inst->urb_write_flags,
449 inst->mlen,
450 0, /* response len */
451 inst->offset, /* urb destination offset */
452 BRW_URB_SWIZZLE_INTERLEAVE);
453 }
454
455 void
456 vec4_generator::generate_gs_urb_write(vec4_instruction *inst)
457 {
458 struct brw_reg src = brw_message_reg(inst->base_mrf);
459 brw_urb_WRITE(p,
460 brw_null_reg(), /* dest */
461 inst->base_mrf, /* starting mrf reg nr */
462 src,
463 inst->urb_write_flags,
464 inst->mlen,
465 0, /* response len */
466 inst->offset, /* urb destination offset */
467 BRW_URB_SWIZZLE_INTERLEAVE);
468 }
469
470 void
471 vec4_generator::generate_gs_urb_write_allocate(vec4_instruction *inst)
472 {
473 struct brw_reg src = brw_message_reg(inst->base_mrf);
474
475 /* We pass the temporary passed in src0 as the writeback register */
476 brw_urb_WRITE(p,
477 inst->get_src(this->prog_data, 0), /* dest */
478 inst->base_mrf, /* starting mrf reg nr */
479 src,
480 BRW_URB_WRITE_ALLOCATE_COMPLETE,
481 inst->mlen,
482 1, /* response len */
483 inst->offset, /* urb destination offset */
484 BRW_URB_SWIZZLE_INTERLEAVE);
485
486 /* Now put allocated urb handle in dst.0 */
487 brw_push_insn_state(p);
488 brw_set_default_access_mode(p, BRW_ALIGN_1);
489 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
490 brw_MOV(p, get_element_ud(inst->get_dst(), 0),
491 get_element_ud(inst->get_src(this->prog_data, 0), 0));
492 brw_set_default_access_mode(p, BRW_ALIGN_16);
493 brw_pop_insn_state(p);
494 }
495
496 void
497 vec4_generator::generate_gs_thread_end(vec4_instruction *inst)
498 {
499 struct brw_reg src = brw_message_reg(inst->base_mrf);
500 brw_urb_WRITE(p,
501 brw_null_reg(), /* dest */
502 inst->base_mrf, /* starting mrf reg nr */
503 src,
504 BRW_URB_WRITE_EOT | inst->urb_write_flags,
505 brw->gen >= 8 ? 2 : 1,/* message len */
506 0, /* response len */
507 0, /* urb destination offset */
508 BRW_URB_SWIZZLE_INTERLEAVE);
509 }
510
511 void
512 vec4_generator::generate_gs_set_write_offset(struct brw_reg dst,
513 struct brw_reg src0,
514 struct brw_reg src1)
515 {
516 /* From p22 of volume 4 part 2 of the Ivy Bridge PRM (2.4.3.1 Message
517 * Header: M0.3):
518 *
519 * Slot 0 Offset. This field, after adding to the Global Offset field
520 * in the message descriptor, specifies the offset (in 256-bit units)
521 * from the start of the URB entry, as referenced by URB Handle 0, at
522 * which the data will be accessed.
523 *
524 * Similar text describes DWORD M0.4, which is slot 1 offset.
525 *
526 * Therefore, we want to multiply DWORDs 0 and 4 of src0 (the x components
527 * of the register for geometry shader invocations 0 and 1) by the
528 * immediate value in src1, and store the result in DWORDs 3 and 4 of dst.
529 *
530 * We can do this with the following EU instruction:
531 *
532 * mul(2) dst.3<1>UD src0<8;2,4>UD src1<...>UW { Align1 WE_all }
533 */
534 brw_push_insn_state(p);
535 brw_set_default_access_mode(p, BRW_ALIGN_1);
536 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
537 assert(brw->gen >= 7 &&
538 src1.file == BRW_IMMEDIATE_VALUE &&
539 src1.type == BRW_REGISTER_TYPE_UD &&
540 src1.dw1.ud <= USHRT_MAX);
541 brw_MUL(p, suboffset(stride(dst, 2, 2, 1), 3), stride(src0, 8, 2, 4),
542 retype(src1, BRW_REGISTER_TYPE_UW));
543 brw_set_default_access_mode(p, BRW_ALIGN_16);
544 brw_pop_insn_state(p);
545 }
546
547 void
548 vec4_generator::generate_gs_set_vertex_count(struct brw_reg dst,
549 struct brw_reg src)
550 {
551 brw_push_insn_state(p);
552 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
553
554 if (brw->gen >= 8) {
555 /* Move the vertex count into the second MRF for the EOT write. */
556 brw_MOV(p, retype(brw_message_reg(dst.nr + 1), BRW_REGISTER_TYPE_UD),
557 src);
558 } else {
559 /* If we think of the src and dst registers as composed of 8 DWORDs each,
560 * we want to pick up the contents of DWORDs 0 and 4 from src, truncate
561 * them to WORDs, and then pack them into DWORD 2 of dst.
562 *
563 * It's easier to get the EU to do this if we think of the src and dst
564 * registers as composed of 16 WORDS each; then, we want to pick up the
565 * contents of WORDs 0 and 8 from src, and pack them into WORDs 4 and 5
566 * of dst.
567 *
568 * We can do that by the following EU instruction:
569 *
570 * mov (2) dst.4<1>:uw src<8;1,0>:uw { Align1, Q1, NoMask }
571 */
572 brw_set_default_access_mode(p, BRW_ALIGN_1);
573 brw_MOV(p,
574 suboffset(stride(retype(dst, BRW_REGISTER_TYPE_UW), 2, 2, 1), 4),
575 stride(retype(src, BRW_REGISTER_TYPE_UW), 8, 1, 0));
576 brw_set_default_access_mode(p, BRW_ALIGN_16);
577 }
578 brw_pop_insn_state(p);
579 }
580
581 void
582 vec4_generator::generate_gs_svb_write(vec4_instruction *inst,
583 struct brw_reg dst,
584 struct brw_reg src0,
585 struct brw_reg src1)
586 {
587 int binding = inst->sol_binding;
588 bool final_write = inst->sol_final_write;
589
590 brw_push_insn_state(p);
591 /* Copy Vertex data into M0.x */
592 brw_MOV(p, stride(dst, 4, 4, 1),
593 stride(retype(src0, BRW_REGISTER_TYPE_UD), 4, 4, 1));
594
595 /* Send SVB Write */
596 brw_svb_write(p,
597 final_write ? src1 : brw_null_reg(), /* dest == src1 */
598 1, /* msg_reg_nr */
599 dst, /* src0 == previous dst */
600 SURF_INDEX_GEN6_SOL_BINDING(binding), /* binding_table_index */
601 final_write); /* send_commit_msg */
602
603 /* Finally, wait for the write commit to occur so that we can proceed to
604 * other things safely.
605 *
606 * From the Sandybridge PRM, Volume 4, Part 1, Section 3.3:
607 *
608 * The write commit does not modify the destination register, but
609 * merely clears the dependency associated with the destination
610 * register. Thus, a simple “mov” instruction using the register as a
611 * source is sufficient to wait for the write commit to occur.
612 */
613 if (final_write) {
614 brw_MOV(p, src1, src1);
615 }
616 brw_pop_insn_state(p);
617 }
618
619 void
620 vec4_generator::generate_gs_svb_set_destination_index(vec4_instruction *inst,
621 struct brw_reg dst,
622 struct brw_reg src)
623 {
624
625 int vertex = inst->sol_vertex;
626 brw_push_insn_state(p);
627 brw_set_default_access_mode(p, BRW_ALIGN_1);
628 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
629 brw_MOV(p, get_element_ud(dst, 5), get_element_ud(src, vertex));
630 brw_pop_insn_state(p);
631 }
632
633 void
634 vec4_generator::generate_gs_set_dword_2(struct brw_reg dst, struct brw_reg src)
635 {
636 brw_push_insn_state(p);
637 brw_set_default_access_mode(p, BRW_ALIGN_1);
638 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
639 brw_MOV(p, suboffset(vec1(dst), 2), suboffset(vec1(src), 0));
640 brw_pop_insn_state(p);
641 }
642
643 void
644 vec4_generator::generate_gs_prepare_channel_masks(struct brw_reg dst)
645 {
646 /* We want to left shift just DWORD 4 (the x component belonging to the
647 * second geometry shader invocation) by 4 bits. So generate the
648 * instruction:
649 *
650 * shl(1) dst.4<1>UD dst.4<0,1,0>UD 4UD { align1 WE_all }
651 */
652 dst = suboffset(vec1(dst), 4);
653 brw_push_insn_state(p);
654 brw_set_default_access_mode(p, BRW_ALIGN_1);
655 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
656 brw_SHL(p, dst, dst, brw_imm_ud(4));
657 brw_pop_insn_state(p);
658 }
659
660 void
661 vec4_generator::generate_gs_set_channel_masks(struct brw_reg dst,
662 struct brw_reg src)
663 {
664 /* From p21 of volume 4 part 2 of the Ivy Bridge PRM (2.4.3.1 Message
665 * Header: M0.5):
666 *
667 * 15 Vertex 1 DATA [3] / Vertex 0 DATA[7] Channel Mask
668 *
669 * When Swizzle Control = URB_INTERLEAVED this bit controls Vertex 1
670 * DATA[3], when Swizzle Control = URB_NOSWIZZLE this bit controls
671 * Vertex 0 DATA[7]. This bit is ANDed with the corresponding
672 * channel enable to determine the final channel enable. For the
673 * URB_READ_OWORD & URB_READ_HWORD messages, when final channel
674 * enable is 1 it indicates that Vertex 1 DATA [3] will be included
675 * in the writeback message. For the URB_WRITE_OWORD &
676 * URB_WRITE_HWORD messages, when final channel enable is 1 it
677 * indicates that Vertex 1 DATA [3] will be written to the surface.
678 *
679 * 0: Vertex 1 DATA [3] / Vertex 0 DATA[7] channel not included
680 * 1: Vertex DATA [3] / Vertex 0 DATA[7] channel included
681 *
682 * 14 Vertex 1 DATA [2] Channel Mask
683 * 13 Vertex 1 DATA [1] Channel Mask
684 * 12 Vertex 1 DATA [0] Channel Mask
685 * 11 Vertex 0 DATA [3] Channel Mask
686 * 10 Vertex 0 DATA [2] Channel Mask
687 * 9 Vertex 0 DATA [1] Channel Mask
688 * 8 Vertex 0 DATA [0] Channel Mask
689 *
690 * (This is from a section of the PRM that is agnostic to the particular
691 * type of shader being executed, so "Vertex 0" and "Vertex 1" refer to
692 * geometry shader invocations 0 and 1, respectively). Since we have the
693 * enable flags for geometry shader invocation 0 in bits 3:0 of DWORD 0,
694 * and the enable flags for geometry shader invocation 1 in bits 7:0 of
695 * DWORD 4, we just need to OR them together and store the result in bits
696 * 15:8 of DWORD 5.
697 *
698 * It's easier to get the EU to do this if we think of the src and dst
699 * registers as composed of 32 bytes each; then, we want to pick up the
700 * contents of bytes 0 and 16 from src, OR them together, and store them in
701 * byte 21.
702 *
703 * We can do that by the following EU instruction:
704 *
705 * or(1) dst.21<1>UB src<0,1,0>UB src.16<0,1,0>UB { align1 WE_all }
706 *
707 * Note: this relies on the source register having zeros in (a) bits 7:4 of
708 * DWORD 0 and (b) bits 3:0 of DWORD 4. We can rely on (b) because the
709 * source register was prepared by GS_OPCODE_PREPARE_CHANNEL_MASKS (which
710 * shifts DWORD 4 left by 4 bits), and we can rely on (a) because prior to
711 * the execution of GS_OPCODE_PREPARE_CHANNEL_MASKS, DWORDs 0 and 4 need to
712 * contain valid channel mask values (which are in the range 0x0-0xf).
713 */
714 dst = retype(dst, BRW_REGISTER_TYPE_UB);
715 src = retype(src, BRW_REGISTER_TYPE_UB);
716 brw_push_insn_state(p);
717 brw_set_default_access_mode(p, BRW_ALIGN_1);
718 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
719 brw_OR(p, suboffset(vec1(dst), 21), vec1(src), suboffset(vec1(src), 16));
720 brw_pop_insn_state(p);
721 }
722
723 void
724 vec4_generator::generate_gs_get_instance_id(struct brw_reg dst)
725 {
726 /* We want to right shift R0.0 & R0.1 by GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT
727 * and store into dst.0 & dst.4. So generate the instruction:
728 *
729 * shr(8) dst<1> R0<1,4,0> GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT { align1 WE_normal 1Q }
730 */
731 brw_push_insn_state(p);
732 brw_set_default_access_mode(p, BRW_ALIGN_1);
733 dst = retype(dst, BRW_REGISTER_TYPE_UD);
734 struct brw_reg r0(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
735 brw_SHR(p, dst, stride(r0, 1, 4, 0),
736 brw_imm_ud(GEN7_GS_PAYLOAD_INSTANCE_ID_SHIFT));
737 brw_pop_insn_state(p);
738 }
739
740 void
741 vec4_generator::generate_gs_ff_sync_set_primitives(struct brw_reg dst,
742 struct brw_reg src0,
743 struct brw_reg src1,
744 struct brw_reg src2)
745 {
746 brw_push_insn_state(p);
747 brw_set_default_access_mode(p, BRW_ALIGN_1);
748 /* Save src0 data in 16:31 bits of dst.0 */
749 brw_AND(p, suboffset(vec1(dst), 0), suboffset(vec1(src0), 0),
750 brw_imm_ud(0xffffu));
751 brw_SHL(p, suboffset(vec1(dst), 0), suboffset(vec1(dst), 0), brw_imm_ud(16));
752 /* Save src1 data in 0:15 bits of dst.0 */
753 brw_AND(p, suboffset(vec1(src2), 0), suboffset(vec1(src1), 0),
754 brw_imm_ud(0xffffu));
755 brw_OR(p, suboffset(vec1(dst), 0),
756 suboffset(vec1(dst), 0),
757 suboffset(vec1(src2), 0));
758 brw_pop_insn_state(p);
759 }
760
761 void
762 vec4_generator::generate_gs_ff_sync(vec4_instruction *inst,
763 struct brw_reg dst,
764 struct brw_reg src0,
765 struct brw_reg src1)
766 {
767 /* This opcode uses an implied MRF register for:
768 * - the header of the ff_sync message. And as such it is expected to be
769 * initialized to r0 before calling here.
770 * - the destination where we will write the allocated URB handle.
771 */
772 struct brw_reg header =
773 retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD);
774
775 /* Overwrite dword 0 of the header (SO vertices to write) and
776 * dword 1 (number of primitives written).
777 */
778 brw_push_insn_state(p);
779 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
780 brw_set_default_access_mode(p, BRW_ALIGN_1);
781 brw_MOV(p, get_element_ud(header, 0), get_element_ud(src1, 0));
782 brw_MOV(p, get_element_ud(header, 1), get_element_ud(src0, 0));
783 brw_pop_insn_state(p);
784
785 /* Allocate URB handle in dst */
786 brw_ff_sync(p,
787 dst,
788 0,
789 header,
790 1, /* allocate */
791 1, /* response length */
792 0 /* eot */);
793
794 /* Now put allocated urb handle in header.0 */
795 brw_push_insn_state(p);
796 brw_set_default_access_mode(p, BRW_ALIGN_1);
797 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
798 brw_MOV(p, get_element_ud(header, 0), get_element_ud(dst, 0));
799
800 /* src1 is not an immediate when we use transform feedback */
801 if (src1.file != BRW_IMMEDIATE_VALUE)
802 brw_MOV(p, brw_vec4_grf(src1.nr, 0), brw_vec4_grf(dst.nr, 1));
803
804 brw_pop_insn_state(p);
805 }
806
807 void
808 vec4_generator::generate_gs_set_primitive_id(struct brw_reg dst)
809 {
810 /* In gen6, PrimitiveID is delivered in R0.1 of the payload */
811 struct brw_reg src = brw_vec8_grf(0, 0);
812 brw_push_insn_state(p);
813 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
814 brw_set_default_access_mode(p, BRW_ALIGN_1);
815 brw_MOV(p, get_element_ud(dst, 0), get_element_ud(src, 1));
816 brw_pop_insn_state(p);
817 }
818
819 void
820 vec4_generator::generate_oword_dual_block_offsets(struct brw_reg m1,
821 struct brw_reg index)
822 {
823 int second_vertex_offset;
824
825 if (brw->gen >= 6)
826 second_vertex_offset = 1;
827 else
828 second_vertex_offset = 16;
829
830 m1 = retype(m1, BRW_REGISTER_TYPE_D);
831
832 /* Set up M1 (message payload). Only the block offsets in M1.0 and
833 * M1.4 are used, and the rest are ignored.
834 */
835 struct brw_reg m1_0 = suboffset(vec1(m1), 0);
836 struct brw_reg m1_4 = suboffset(vec1(m1), 4);
837 struct brw_reg index_0 = suboffset(vec1(index), 0);
838 struct brw_reg index_4 = suboffset(vec1(index), 4);
839
840 brw_push_insn_state(p);
841 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
842 brw_set_default_access_mode(p, BRW_ALIGN_1);
843
844 brw_MOV(p, m1_0, index_0);
845
846 if (index.file == BRW_IMMEDIATE_VALUE) {
847 index_4.dw1.ud += second_vertex_offset;
848 brw_MOV(p, m1_4, index_4);
849 } else {
850 brw_ADD(p, m1_4, index_4, brw_imm_d(second_vertex_offset));
851 }
852
853 brw_pop_insn_state(p);
854 }
855
856 void
857 vec4_generator::generate_unpack_flags(vec4_instruction *inst,
858 struct brw_reg dst)
859 {
860 brw_push_insn_state(p);
861 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
862 brw_set_default_access_mode(p, BRW_ALIGN_1);
863
864 struct brw_reg flags = brw_flag_reg(0, 0);
865 struct brw_reg dst_0 = suboffset(vec1(dst), 0);
866 struct brw_reg dst_4 = suboffset(vec1(dst), 4);
867
868 brw_AND(p, dst_0, flags, brw_imm_ud(0x0f));
869 brw_AND(p, dst_4, flags, brw_imm_ud(0xf0));
870 brw_SHR(p, dst_4, dst_4, brw_imm_ud(4));
871
872 brw_pop_insn_state(p);
873 }
874
875 void
876 vec4_generator::generate_scratch_read(vec4_instruction *inst,
877 struct brw_reg dst,
878 struct brw_reg index)
879 {
880 struct brw_reg header = brw_vec8_grf(0, 0);
881
882 gen6_resolve_implied_move(p, &header, inst->base_mrf);
883
884 generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1),
885 index);
886
887 uint32_t msg_type;
888
889 if (brw->gen >= 6)
890 msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
891 else if (brw->gen == 5 || brw->is_g4x)
892 msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
893 else
894 msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
895
896 /* Each of the 8 channel enables is considered for whether each
897 * dword is written.
898 */
899 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
900 brw_set_dest(p, send, dst);
901 brw_set_src0(p, send, header);
902 if (brw->gen < 6)
903 brw_inst_set_cond_modifier(brw, send, inst->base_mrf);
904 brw_set_dp_read_message(p, send,
905 255, /* binding table index: stateless access */
906 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
907 msg_type,
908 BRW_DATAPORT_READ_TARGET_RENDER_CACHE,
909 2, /* mlen */
910 true, /* header_present */
911 1 /* rlen */);
912 }
913
914 void
915 vec4_generator::generate_scratch_write(vec4_instruction *inst,
916 struct brw_reg dst,
917 struct brw_reg src,
918 struct brw_reg index)
919 {
920 struct brw_reg header = brw_vec8_grf(0, 0);
921 bool write_commit;
922
923 /* If the instruction is predicated, we'll predicate the send, not
924 * the header setup.
925 */
926 brw_set_default_predicate_control(p, false);
927
928 gen6_resolve_implied_move(p, &header, inst->base_mrf);
929
930 generate_oword_dual_block_offsets(brw_message_reg(inst->base_mrf + 1),
931 index);
932
933 brw_MOV(p,
934 retype(brw_message_reg(inst->base_mrf + 2), BRW_REGISTER_TYPE_D),
935 retype(src, BRW_REGISTER_TYPE_D));
936
937 uint32_t msg_type;
938
939 if (brw->gen >= 7)
940 msg_type = GEN7_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
941 else if (brw->gen == 6)
942 msg_type = GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
943 else
944 msg_type = BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE;
945
946 brw_set_default_predicate_control(p, inst->predicate);
947
948 /* Pre-gen6, we have to specify write commits to ensure ordering
949 * between reads and writes within a thread. Afterwards, that's
950 * guaranteed and write commits only matter for inter-thread
951 * synchronization.
952 */
953 if (brw->gen >= 6) {
954 write_commit = false;
955 } else {
956 /* The visitor set up our destination register to be g0. This
957 * means that when the next read comes along, we will end up
958 * reading from g0 and causing a block on the write commit. For
959 * write-after-read, we are relying on the value of the previous
960 * read being used (and thus blocking on completion) before our
961 * write is executed. This means we have to be careful in
962 * instruction scheduling to not violate this assumption.
963 */
964 write_commit = true;
965 }
966
967 /* Each of the 8 channel enables is considered for whether each
968 * dword is written.
969 */
970 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
971 brw_set_dest(p, send, dst);
972 brw_set_src0(p, send, header);
973 if (brw->gen < 6)
974 brw_inst_set_cond_modifier(brw, send, inst->base_mrf);
975 brw_set_dp_write_message(p, send,
976 255, /* binding table index: stateless access */
977 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
978 msg_type,
979 3, /* mlen */
980 true, /* header present */
981 false, /* not a render target write */
982 write_commit, /* rlen */
983 false, /* eot */
984 write_commit);
985 }
986
987 void
988 vec4_generator::generate_pull_constant_load(vec4_instruction *inst,
989 struct brw_reg dst,
990 struct brw_reg index,
991 struct brw_reg offset)
992 {
993 assert(index.file == BRW_IMMEDIATE_VALUE &&
994 index.type == BRW_REGISTER_TYPE_UD);
995 uint32_t surf_index = index.dw1.ud;
996
997 struct brw_reg header = brw_vec8_grf(0, 0);
998
999 gen6_resolve_implied_move(p, &header, inst->base_mrf);
1000
1001 brw_MOV(p, retype(brw_message_reg(inst->base_mrf + 1), BRW_REGISTER_TYPE_D),
1002 offset);
1003
1004 uint32_t msg_type;
1005
1006 if (brw->gen >= 6)
1007 msg_type = GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
1008 else if (brw->gen == 5 || brw->is_g4x)
1009 msg_type = G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
1010 else
1011 msg_type = BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ;
1012
1013 /* Each of the 8 channel enables is considered for whether each
1014 * dword is written.
1015 */
1016 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1017 brw_set_dest(p, send, dst);
1018 brw_set_src0(p, send, header);
1019 if (brw->gen < 6)
1020 brw_inst_set_cond_modifier(brw, send, inst->base_mrf);
1021 brw_set_dp_read_message(p, send,
1022 surf_index,
1023 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD,
1024 msg_type,
1025 BRW_DATAPORT_READ_TARGET_DATA_CACHE,
1026 2, /* mlen */
1027 true, /* header_present */
1028 1 /* rlen */);
1029
1030 brw_mark_surface_used(&prog_data->base, surf_index);
1031 }
1032
1033 void
1034 vec4_generator::generate_pull_constant_load_gen7(vec4_instruction *inst,
1035 struct brw_reg dst,
1036 struct brw_reg surf_index,
1037 struct brw_reg offset)
1038 {
1039 assert(surf_index.type == BRW_REGISTER_TYPE_UD);
1040
1041 if (surf_index.file == BRW_IMMEDIATE_VALUE) {
1042
1043 brw_inst *insn = brw_next_insn(p, BRW_OPCODE_SEND);
1044 brw_set_dest(p, insn, dst);
1045 brw_set_src0(p, insn, offset);
1046 brw_set_sampler_message(p, insn,
1047 surf_index.dw1.ud,
1048 0, /* LD message ignores sampler unit */
1049 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1050 1, /* rlen */
1051 1, /* mlen */
1052 false, /* no header */
1053 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
1054 0);
1055
1056 brw_mark_surface_used(&prog_data->base, surf_index.dw1.ud);
1057
1058 } else {
1059
1060 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
1061
1062 brw_push_insn_state(p);
1063 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1064 brw_set_default_access_mode(p, BRW_ALIGN_1);
1065
1066 /* a0.0 = surf_index & 0xff */
1067 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
1068 brw_inst_set_exec_size(p->brw, insn_and, BRW_EXECUTE_1);
1069 brw_set_dest(p, insn_and, addr);
1070 brw_set_src0(p, insn_and, vec1(retype(surf_index, BRW_REGISTER_TYPE_UD)));
1071 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
1072
1073
1074 /* a0.0 |= <descriptor> */
1075 brw_inst *insn_or = brw_next_insn(p, BRW_OPCODE_OR);
1076 brw_set_sampler_message(p, insn_or,
1077 0 /* surface */,
1078 0 /* sampler */,
1079 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1080 1 /* rlen */,
1081 1 /* mlen */,
1082 false /* header */,
1083 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
1084 0);
1085 brw_inst_set_exec_size(p->brw, insn_or, BRW_EXECUTE_1);
1086 brw_inst_set_src1_reg_type(p->brw, insn_or, BRW_REGISTER_TYPE_UD);
1087 brw_set_src0(p, insn_or, addr);
1088 brw_set_dest(p, insn_or, addr);
1089
1090
1091 /* dst = send(offset, a0.0) */
1092 brw_inst *insn_send = brw_next_insn(p, BRW_OPCODE_SEND);
1093 brw_set_dest(p, insn_send, dst);
1094 brw_set_src0(p, insn_send, offset);
1095 brw_set_indirect_send_descriptor(p, insn_send, BRW_SFID_SAMPLER, addr);
1096
1097 brw_pop_insn_state(p);
1098
1099 /* visitor knows more than we do about the surface limit required,
1100 * so has already done marking.
1101 */
1102 }
1103 }
1104
1105 void
1106 vec4_generator::generate_untyped_atomic(vec4_instruction *inst,
1107 struct brw_reg dst,
1108 struct brw_reg atomic_op,
1109 struct brw_reg surf_index)
1110 {
1111 assert(atomic_op.file == BRW_IMMEDIATE_VALUE &&
1112 atomic_op.type == BRW_REGISTER_TYPE_UD &&
1113 surf_index.file == BRW_IMMEDIATE_VALUE &&
1114 surf_index.type == BRW_REGISTER_TYPE_UD);
1115
1116 brw_untyped_atomic(p, dst, brw_message_reg(inst->base_mrf),
1117 atomic_op.dw1.ud, surf_index.dw1.ud,
1118 inst->mlen, 1);
1119
1120 brw_mark_surface_used(&prog_data->base, surf_index.dw1.ud);
1121 }
1122
1123 void
1124 vec4_generator::generate_untyped_surface_read(vec4_instruction *inst,
1125 struct brw_reg dst,
1126 struct brw_reg surf_index)
1127 {
1128 assert(surf_index.file == BRW_IMMEDIATE_VALUE &&
1129 surf_index.type == BRW_REGISTER_TYPE_UD);
1130
1131 brw_untyped_surface_read(p, dst, brw_message_reg(inst->base_mrf),
1132 surf_index.dw1.ud,
1133 inst->mlen, 1);
1134
1135 brw_mark_surface_used(&prog_data->base, surf_index.dw1.ud);
1136 }
1137
1138 void
1139 vec4_generator::generate_code(const cfg_t *cfg)
1140 {
1141 struct annotation_info annotation;
1142 memset(&annotation, 0, sizeof(annotation));
1143 int loop_count = 0;
1144
1145 foreach_block_and_inst (block, vec4_instruction, inst, cfg) {
1146 struct brw_reg src[3], dst;
1147
1148 if (unlikely(debug_flag))
1149 annotate(brw, &annotation, cfg, inst, p->next_insn_offset);
1150
1151 for (unsigned int i = 0; i < 3; i++) {
1152 src[i] = inst->get_src(this->prog_data, i);
1153 }
1154 dst = inst->get_dst();
1155
1156 brw_set_default_predicate_control(p, inst->predicate);
1157 brw_set_default_predicate_inverse(p, inst->predicate_inverse);
1158 brw_set_default_saturate(p, inst->saturate);
1159 brw_set_default_mask_control(p, inst->force_writemask_all);
1160 brw_set_default_acc_write_control(p, inst->writes_accumulator);
1161
1162 unsigned pre_emit_nr_insn = p->nr_insn;
1163
1164 if (dst.width == BRW_WIDTH_4) {
1165 /* This happens in attribute fixups for "dual instanced" geometry
1166 * shaders, since they use attributes that are vec4's. Since the exec
1167 * width is only 4, it's essential that the caller set
1168 * force_writemask_all in order to make sure the instruction is executed
1169 * regardless of which channels are enabled.
1170 */
1171 assert(inst->force_writemask_all);
1172
1173 /* Fix up any <8;8,1> or <0;4,1> source registers to <4;4,1> to satisfy
1174 * the following register region restrictions (from Graphics BSpec:
1175 * 3D-Media-GPGPU Engine > EU Overview > Registers and Register Regions
1176 * > Register Region Restrictions)
1177 *
1178 * 1. ExecSize must be greater than or equal to Width.
1179 *
1180 * 2. If ExecSize = Width and HorzStride != 0, VertStride must be set
1181 * to Width * HorzStride."
1182 */
1183 for (int i = 0; i < 3; i++) {
1184 if (src[i].file == BRW_GENERAL_REGISTER_FILE)
1185 src[i] = stride(src[i], 4, 4, 1);
1186 }
1187 }
1188
1189 switch (inst->opcode) {
1190 case VEC4_OPCODE_UNPACK_UNIFORM:
1191 case BRW_OPCODE_MOV:
1192 brw_MOV(p, dst, src[0]);
1193 break;
1194 case BRW_OPCODE_ADD:
1195 brw_ADD(p, dst, src[0], src[1]);
1196 break;
1197 case BRW_OPCODE_MUL:
1198 brw_MUL(p, dst, src[0], src[1]);
1199 break;
1200 case BRW_OPCODE_MACH:
1201 brw_MACH(p, dst, src[0], src[1]);
1202 break;
1203
1204 case BRW_OPCODE_MAD:
1205 assert(brw->gen >= 6);
1206 brw_MAD(p, dst, src[0], src[1], src[2]);
1207 break;
1208
1209 case BRW_OPCODE_FRC:
1210 brw_FRC(p, dst, src[0]);
1211 break;
1212 case BRW_OPCODE_RNDD:
1213 brw_RNDD(p, dst, src[0]);
1214 break;
1215 case BRW_OPCODE_RNDE:
1216 brw_RNDE(p, dst, src[0]);
1217 break;
1218 case BRW_OPCODE_RNDZ:
1219 brw_RNDZ(p, dst, src[0]);
1220 break;
1221
1222 case BRW_OPCODE_AND:
1223 brw_AND(p, dst, src[0], src[1]);
1224 break;
1225 case BRW_OPCODE_OR:
1226 brw_OR(p, dst, src[0], src[1]);
1227 break;
1228 case BRW_OPCODE_XOR:
1229 brw_XOR(p, dst, src[0], src[1]);
1230 break;
1231 case BRW_OPCODE_NOT:
1232 brw_NOT(p, dst, src[0]);
1233 break;
1234 case BRW_OPCODE_ASR:
1235 brw_ASR(p, dst, src[0], src[1]);
1236 break;
1237 case BRW_OPCODE_SHR:
1238 brw_SHR(p, dst, src[0], src[1]);
1239 break;
1240 case BRW_OPCODE_SHL:
1241 brw_SHL(p, dst, src[0], src[1]);
1242 break;
1243
1244 case BRW_OPCODE_CMP:
1245 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1246 break;
1247 case BRW_OPCODE_SEL:
1248 brw_SEL(p, dst, src[0], src[1]);
1249 break;
1250
1251 case BRW_OPCODE_DPH:
1252 brw_DPH(p, dst, src[0], src[1]);
1253 break;
1254
1255 case BRW_OPCODE_DP4:
1256 brw_DP4(p, dst, src[0], src[1]);
1257 break;
1258
1259 case BRW_OPCODE_DP3:
1260 brw_DP3(p, dst, src[0], src[1]);
1261 break;
1262
1263 case BRW_OPCODE_DP2:
1264 brw_DP2(p, dst, src[0], src[1]);
1265 break;
1266
1267 case BRW_OPCODE_F32TO16:
1268 assert(brw->gen >= 7);
1269 brw_F32TO16(p, dst, src[0]);
1270 break;
1271
1272 case BRW_OPCODE_F16TO32:
1273 assert(brw->gen >= 7);
1274 brw_F16TO32(p, dst, src[0]);
1275 break;
1276
1277 case BRW_OPCODE_LRP:
1278 assert(brw->gen >= 6);
1279 brw_LRP(p, dst, src[0], src[1], src[2]);
1280 break;
1281
1282 case BRW_OPCODE_BFREV:
1283 assert(brw->gen >= 7);
1284 /* BFREV only supports UD type for src and dst. */
1285 brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
1286 retype(src[0], BRW_REGISTER_TYPE_UD));
1287 break;
1288 case BRW_OPCODE_FBH:
1289 assert(brw->gen >= 7);
1290 /* FBH only supports UD type for dst. */
1291 brw_FBH(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1292 break;
1293 case BRW_OPCODE_FBL:
1294 assert(brw->gen >= 7);
1295 /* FBL only supports UD type for dst. */
1296 brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1297 break;
1298 case BRW_OPCODE_CBIT:
1299 assert(brw->gen >= 7);
1300 /* CBIT only supports UD type for dst. */
1301 brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1302 break;
1303 case BRW_OPCODE_ADDC:
1304 assert(brw->gen >= 7);
1305 brw_ADDC(p, dst, src[0], src[1]);
1306 break;
1307 case BRW_OPCODE_SUBB:
1308 assert(brw->gen >= 7);
1309 brw_SUBB(p, dst, src[0], src[1]);
1310 break;
1311 case BRW_OPCODE_MAC:
1312 brw_MAC(p, dst, src[0], src[1]);
1313 break;
1314
1315 case BRW_OPCODE_BFE:
1316 assert(brw->gen >= 7);
1317 brw_BFE(p, dst, src[0], src[1], src[2]);
1318 break;
1319
1320 case BRW_OPCODE_BFI1:
1321 assert(brw->gen >= 7);
1322 brw_BFI1(p, dst, src[0], src[1]);
1323 break;
1324 case BRW_OPCODE_BFI2:
1325 assert(brw->gen >= 7);
1326 brw_BFI2(p, dst, src[0], src[1], src[2]);
1327 break;
1328
1329 case BRW_OPCODE_IF:
1330 if (inst->src[0].file != BAD_FILE) {
1331 /* The instruction has an embedded compare (only allowed on gen6) */
1332 assert(brw->gen == 6);
1333 gen6_IF(p, inst->conditional_mod, src[0], src[1]);
1334 } else {
1335 brw_inst *if_inst = brw_IF(p, BRW_EXECUTE_8);
1336 brw_inst_set_pred_control(brw, if_inst, inst->predicate);
1337 }
1338 break;
1339
1340 case BRW_OPCODE_ELSE:
1341 brw_ELSE(p);
1342 break;
1343 case BRW_OPCODE_ENDIF:
1344 brw_ENDIF(p);
1345 break;
1346
1347 case BRW_OPCODE_DO:
1348 brw_DO(p, BRW_EXECUTE_8);
1349 break;
1350
1351 case BRW_OPCODE_BREAK:
1352 brw_BREAK(p);
1353 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1354 break;
1355 case BRW_OPCODE_CONTINUE:
1356 brw_CONT(p);
1357 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1358 break;
1359
1360 case BRW_OPCODE_WHILE:
1361 brw_WHILE(p);
1362 loop_count++;
1363 break;
1364
1365 case SHADER_OPCODE_RCP:
1366 case SHADER_OPCODE_RSQ:
1367 case SHADER_OPCODE_SQRT:
1368 case SHADER_OPCODE_EXP2:
1369 case SHADER_OPCODE_LOG2:
1370 case SHADER_OPCODE_SIN:
1371 case SHADER_OPCODE_COS:
1372 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
1373 if (brw->gen >= 7) {
1374 gen6_math(p, dst, brw_math_function(inst->opcode), src[0],
1375 brw_null_reg());
1376 } else if (brw->gen == 6) {
1377 generate_math_gen6(inst, dst, src[0], brw_null_reg());
1378 } else {
1379 generate_math1_gen4(inst, dst, src[0]);
1380 }
1381 break;
1382
1383 case SHADER_OPCODE_POW:
1384 case SHADER_OPCODE_INT_QUOTIENT:
1385 case SHADER_OPCODE_INT_REMAINDER:
1386 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
1387 if (brw->gen >= 7) {
1388 gen6_math(p, dst, brw_math_function(inst->opcode), src[0], src[1]);
1389 } else if (brw->gen == 6) {
1390 generate_math_gen6(inst, dst, src[0], src[1]);
1391 } else {
1392 generate_math2_gen4(inst, dst, src[0], src[1]);
1393 }
1394 break;
1395
1396 case SHADER_OPCODE_TEX:
1397 case SHADER_OPCODE_TXD:
1398 case SHADER_OPCODE_TXF:
1399 case SHADER_OPCODE_TXF_CMS:
1400 case SHADER_OPCODE_TXF_MCS:
1401 case SHADER_OPCODE_TXL:
1402 case SHADER_OPCODE_TXS:
1403 case SHADER_OPCODE_TG4:
1404 case SHADER_OPCODE_TG4_OFFSET:
1405 generate_tex(inst, dst, src[0], src[1]);
1406 break;
1407
1408 case VS_OPCODE_URB_WRITE:
1409 generate_vs_urb_write(inst);
1410 break;
1411
1412 case SHADER_OPCODE_GEN4_SCRATCH_READ:
1413 generate_scratch_read(inst, dst, src[0]);
1414 break;
1415
1416 case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1417 generate_scratch_write(inst, dst, src[0], src[1]);
1418 break;
1419
1420 case VS_OPCODE_PULL_CONSTANT_LOAD:
1421 generate_pull_constant_load(inst, dst, src[0], src[1]);
1422 break;
1423
1424 case VS_OPCODE_PULL_CONSTANT_LOAD_GEN7:
1425 generate_pull_constant_load_gen7(inst, dst, src[0], src[1]);
1426 break;
1427
1428 case GS_OPCODE_URB_WRITE:
1429 generate_gs_urb_write(inst);
1430 break;
1431
1432 case GS_OPCODE_URB_WRITE_ALLOCATE:
1433 generate_gs_urb_write_allocate(inst);
1434 break;
1435
1436 case GS_OPCODE_SVB_WRITE:
1437 generate_gs_svb_write(inst, dst, src[0], src[1]);
1438 break;
1439
1440 case GS_OPCODE_SVB_SET_DST_INDEX:
1441 generate_gs_svb_set_destination_index(inst, dst, src[0]);
1442 break;
1443
1444 case GS_OPCODE_THREAD_END:
1445 generate_gs_thread_end(inst);
1446 break;
1447
1448 case GS_OPCODE_SET_WRITE_OFFSET:
1449 generate_gs_set_write_offset(dst, src[0], src[1]);
1450 break;
1451
1452 case GS_OPCODE_SET_VERTEX_COUNT:
1453 generate_gs_set_vertex_count(dst, src[0]);
1454 break;
1455
1456 case GS_OPCODE_FF_SYNC:
1457 generate_gs_ff_sync(inst, dst, src[0], src[1]);
1458 break;
1459
1460 case GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
1461 generate_gs_ff_sync_set_primitives(dst, src[0], src[1], src[2]);
1462 break;
1463
1464 case GS_OPCODE_SET_PRIMITIVE_ID:
1465 generate_gs_set_primitive_id(dst);
1466 break;
1467
1468 case GS_OPCODE_SET_DWORD_2:
1469 generate_gs_set_dword_2(dst, src[0]);
1470 break;
1471
1472 case GS_OPCODE_PREPARE_CHANNEL_MASKS:
1473 generate_gs_prepare_channel_masks(dst);
1474 break;
1475
1476 case GS_OPCODE_SET_CHANNEL_MASKS:
1477 generate_gs_set_channel_masks(dst, src[0]);
1478 break;
1479
1480 case GS_OPCODE_GET_INSTANCE_ID:
1481 generate_gs_get_instance_id(dst);
1482 break;
1483
1484 case SHADER_OPCODE_SHADER_TIME_ADD:
1485 brw_shader_time_add(p, src[0],
1486 prog_data->base.binding_table.shader_time_start);
1487 brw_mark_surface_used(&prog_data->base,
1488 prog_data->base.binding_table.shader_time_start);
1489 break;
1490
1491 case SHADER_OPCODE_UNTYPED_ATOMIC:
1492 generate_untyped_atomic(inst, dst, src[0], src[1]);
1493 break;
1494
1495 case SHADER_OPCODE_UNTYPED_SURFACE_READ:
1496 generate_untyped_surface_read(inst, dst, src[0]);
1497 break;
1498
1499 case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
1500 generate_unpack_flags(inst, dst);
1501 break;
1502
1503 case VEC4_OPCODE_PACK_BYTES: {
1504 /* Is effectively:
1505 *
1506 * mov(8) dst<16,4,1>:UB src<4,1,0>:UB
1507 *
1508 * but destinations' only regioning is horizontal stride, so instead we
1509 * have to use two instructions:
1510 *
1511 * mov(4) dst<1>:UB src<4,1,0>:UB
1512 * mov(4) dst.16<1>:UB src.16<4,1,0>:UB
1513 *
1514 * where they pack the four bytes from the low and high four DW.
1515 */
1516 assert(is_power_of_two(dst.dw1.bits.writemask) &&
1517 dst.dw1.bits.writemask != 0);
1518 unsigned offset = __builtin_ctz(dst.dw1.bits.writemask);
1519
1520 dst.type = BRW_REGISTER_TYPE_UB;
1521
1522 brw_set_default_access_mode(p, BRW_ALIGN_1);
1523
1524 src[0].type = BRW_REGISTER_TYPE_UB;
1525 src[0].vstride = BRW_VERTICAL_STRIDE_4;
1526 src[0].width = BRW_WIDTH_1;
1527 src[0].hstride = BRW_HORIZONTAL_STRIDE_0;
1528 dst.subnr = offset * 4;
1529 struct brw_inst *insn = brw_MOV(p, dst, src[0]);
1530 brw_inst_set_exec_size(brw, insn, BRW_EXECUTE_4);
1531 brw_inst_set_no_dd_clear(brw, insn, true);
1532 brw_inst_set_no_dd_check(brw, insn, inst->no_dd_check);
1533
1534 src[0].subnr = 16;
1535 dst.subnr = 16 + offset * 4;
1536 insn = brw_MOV(p, dst, src[0]);
1537 brw_inst_set_exec_size(brw, insn, BRW_EXECUTE_4);
1538 brw_inst_set_no_dd_clear(brw, insn, inst->no_dd_clear);
1539 brw_inst_set_no_dd_check(brw, insn, true);
1540
1541 brw_set_default_access_mode(p, BRW_ALIGN_16);
1542 break;
1543 }
1544
1545 default:
1546 if (inst->opcode < (int) ARRAY_SIZE(opcode_descs)) {
1547 _mesa_problem(&brw->ctx, "Unsupported opcode in `%s' in vec4\n",
1548 opcode_descs[inst->opcode].name);
1549 } else {
1550 _mesa_problem(&brw->ctx, "Unsupported opcode %d in vec4", inst->opcode);
1551 }
1552 abort();
1553 }
1554
1555 if (inst->opcode == VEC4_OPCODE_PACK_BYTES) {
1556 /* Handled dependency hints in the generator. */
1557
1558 assert(!inst->conditional_mod);
1559 } else if (inst->no_dd_clear || inst->no_dd_check || inst->conditional_mod) {
1560 assert(p->nr_insn == pre_emit_nr_insn + 1 ||
1561 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
1562 "emitting more than 1 instruction");
1563
1564 brw_inst *last = &p->store[pre_emit_nr_insn];
1565
1566 if (inst->conditional_mod)
1567 brw_inst_set_cond_modifier(brw, last, inst->conditional_mod);
1568 brw_inst_set_no_dd_clear(brw, last, inst->no_dd_clear);
1569 brw_inst_set_no_dd_check(brw, last, inst->no_dd_check);
1570 }
1571 }
1572
1573 brw_set_uip_jip(p);
1574 annotation_finalize(&annotation, p->next_insn_offset);
1575
1576 int before_size = p->next_insn_offset;
1577 brw_compact_instructions(p, 0, annotation.ann_count, annotation.ann);
1578 int after_size = p->next_insn_offset;
1579
1580 if (unlikely(debug_flag)) {
1581 if (shader_prog) {
1582 fprintf(stderr, "Native code for %s vertex shader %d:\n",
1583 shader_prog->Label ? shader_prog->Label : "unnamed",
1584 shader_prog->Name);
1585 } else {
1586 fprintf(stderr, "Native code for vertex program %d:\n", prog->Id);
1587 }
1588 fprintf(stderr, "vec4 shader: %d instructions. %d loops. Compacted %d to %d"
1589 " bytes (%.0f%%)\n",
1590 before_size / 16, loop_count, before_size, after_size,
1591 100.0f * (before_size - after_size) / before_size);
1592
1593 dump_assembly(p->store, annotation.ann_count, annotation.ann, brw, prog);
1594 ralloc_free(annotation.ann);
1595 }
1596 }
1597
1598 const unsigned *
1599 vec4_generator::generate_assembly(const cfg_t *cfg,
1600 unsigned *assembly_size)
1601 {
1602 brw_set_default_access_mode(p, BRW_ALIGN_16);
1603 generate_code(cfg);
1604
1605 return brw_get_program(p, assembly_size);
1606 }
1607
1608 } /* namespace brw */