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Merge branch 'master' into autoconf2
[mesa.git] / src / mesa / drivers / dri / i965 / brw_wm_glsl.c
1 #include "macros.h"
2 #include "shader/prog_parameter.h"
3 #include "brw_context.h"
4 #include "brw_eu.h"
5 #include "brw_wm.h"
6
7 /* Only guess, need a flag in gl_fragment_program later */
8 GLboolean brw_wm_is_glsl(const struct gl_fragment_program *fp)
9 {
10 int i;
11 for (i = 0; i < fp->Base.NumInstructions; i++) {
12 struct prog_instruction *inst = &fp->Base.Instructions[i];
13 switch (inst->Opcode) {
14 case OPCODE_IF:
15 case OPCODE_INT:
16 case OPCODE_ENDIF:
17 case OPCODE_CAL:
18 case OPCODE_BRK:
19 case OPCODE_RET:
20 case OPCODE_DDX:
21 case OPCODE_DDY:
22 case OPCODE_BGNLOOP:
23 return GL_TRUE;
24 default:
25 break;
26 }
27 }
28 return GL_FALSE;
29 }
30
31 static void set_reg(struct brw_wm_compile *c, int file, int index,
32 int component, struct brw_reg reg)
33 {
34 c->wm_regs[file][index][component].reg = reg;
35 c->wm_regs[file][index][component].inited = GL_TRUE;
36 }
37
38 static int get_scalar_dst_index(struct prog_instruction *inst)
39 {
40 int i;
41 for (i = 0; i < 4; i++)
42 if (inst->DstReg.WriteMask & (1<<i))
43 break;
44 return i;
45 }
46
47 static struct brw_reg alloc_tmp(struct brw_wm_compile *c)
48 {
49 struct brw_reg reg;
50 reg = brw_vec8_grf(c->tmp_index--, 0);
51 return reg;
52 }
53
54 static void release_tmps(struct brw_wm_compile *c)
55 {
56 c->tmp_index = 127;
57 }
58
59 static struct brw_reg
60 get_reg(struct brw_wm_compile *c, int file, int index, int component, int nr, GLuint neg, GLuint abs)
61 {
62 struct brw_reg reg;
63 switch (file) {
64 case PROGRAM_STATE_VAR:
65 case PROGRAM_CONSTANT:
66 case PROGRAM_UNIFORM:
67 file = PROGRAM_STATE_VAR;
68 break;
69 case PROGRAM_UNDEFINED:
70 return brw_null_reg();
71 default:
72 break;
73 }
74
75 if(c->wm_regs[file][index][component].inited)
76 reg = c->wm_regs[file][index][component].reg;
77 else
78 reg = brw_vec8_grf(c->reg_index, 0);
79
80 if(!c->wm_regs[file][index][component].inited) {
81 set_reg(c, file, index, component, reg);
82 c->reg_index++;
83 }
84
85 if (neg & (1<< component)) {
86 reg = negate(reg);
87 }
88 if (abs)
89 reg = brw_abs(reg);
90 return reg;
91 }
92
93 static void prealloc_reg(struct brw_wm_compile *c)
94 {
95 int i, j;
96 struct brw_reg reg;
97 int nr_interp_regs = 0;
98 GLuint inputs = FRAG_BIT_WPOS | c->fp_interp_emitted | c->fp_deriv_emitted;
99
100 for (i = 0; i < 4; i++) {
101 reg = (i < c->key.nr_depth_regs)
102 ? brw_vec8_grf(i*2, 0) : brw_vec8_grf(0, 0);
103 set_reg(c, PROGRAM_PAYLOAD, PAYLOAD_DEPTH, i, reg);
104 }
105 c->reg_index += 2*c->key.nr_depth_regs;
106 {
107 int nr_params = c->fp->program.Base.Parameters->NumParameters;
108 struct gl_program_parameter_list *plist =
109 c->fp->program.Base.Parameters;
110 int index = 0;
111 c->prog_data.nr_params = 4*nr_params;
112 for (i = 0; i < nr_params; i++) {
113 for (j = 0; j < 4; j++, index++) {
114 reg = brw_vec1_grf(c->reg_index + index/8,
115 index%8);
116 c->prog_data.param[index] =
117 &plist->ParameterValues[i][j];
118 set_reg(c, PROGRAM_STATE_VAR, i, j, reg);
119 }
120 }
121 c->nr_creg = 2*((4*nr_params+15)/16);
122 c->reg_index += c->nr_creg;
123 }
124 for (i = 0; i < FRAG_ATTRIB_MAX; i++) {
125 if (inputs & (1<<i)) {
126 nr_interp_regs++;
127 reg = brw_vec8_grf(c->reg_index, 0);
128 for (j = 0; j < 4; j++)
129 set_reg(c, PROGRAM_PAYLOAD, i, j, reg);
130 c->reg_index += 2;
131
132 }
133 }
134 c->prog_data.first_curbe_grf = c->key.nr_depth_regs * 2;
135 c->prog_data.urb_read_length = nr_interp_regs * 2;
136 c->prog_data.curb_read_length = c->nr_creg;
137 c->emit_mask_reg = brw_uw1_reg(BRW_GENERAL_REGISTER_FILE, c->reg_index, 0);
138 c->reg_index++;
139 c->stack = brw_uw16_reg(BRW_GENERAL_REGISTER_FILE, c->reg_index, 0);
140 c->reg_index += 2;
141 }
142
143 static struct brw_reg get_dst_reg(struct brw_wm_compile *c,
144 struct prog_instruction *inst, int component, int nr)
145 {
146 return get_reg(c, inst->DstReg.File, inst->DstReg.Index, component, nr,
147 0, 0);
148 }
149
150 static struct brw_reg get_src_reg(struct brw_wm_compile *c,
151 struct prog_src_register *src, int index, int nr)
152 {
153 int component = GET_SWZ(src->Swizzle, index);
154 return get_reg(c, src->File, src->Index, component, nr,
155 src->NegateBase, src->Abs);
156 }
157
158 static void emit_abs( struct brw_wm_compile *c,
159 struct prog_instruction *inst)
160 {
161 int i;
162 struct brw_compile *p = &c->func;
163 brw_set_saturate(p, inst->SaturateMode != SATURATE_OFF);
164 for (i = 0; i < 4; i++) {
165 if (inst->DstReg.WriteMask & (1<<i)) {
166 struct brw_reg src, dst;
167 dst = get_dst_reg(c, inst, i, 1);
168 src = get_src_reg(c, &inst->SrcReg[0], i, 1);
169 brw_MOV(p, dst, brw_abs(src));
170 }
171 }
172 brw_set_saturate(p, 0);
173 }
174
175 static void emit_int( struct brw_wm_compile *c,
176 struct prog_instruction *inst)
177 {
178 int i;
179 struct brw_compile *p = &c->func;
180 GLuint mask = inst->DstReg.WriteMask;
181 brw_set_saturate(p, inst->SaturateMode != SATURATE_OFF);
182 for (i = 0; i < 4; i++) {
183 if (mask & (1<<i)) {
184 struct brw_reg src, dst;
185 dst = get_dst_reg(c, inst, i, 1) ;
186 src = get_src_reg(c, &inst->SrcReg[0], i, 1);
187 brw_RNDD(p, dst, src);
188 }
189 }
190 brw_set_saturate(p, 0);
191 }
192
193 static void emit_mov( struct brw_wm_compile *c,
194 struct prog_instruction *inst)
195 {
196 int i;
197 struct brw_compile *p = &c->func;
198 GLuint mask = inst->DstReg.WriteMask;
199 brw_set_saturate(p, inst->SaturateMode != SATURATE_OFF);
200 for (i = 0; i < 4; i++) {
201 if (mask & (1<<i)) {
202 struct brw_reg src, dst;
203 dst = get_dst_reg(c, inst, i, 1);
204 src = get_src_reg(c, &inst->SrcReg[0], i, 1);
205 brw_MOV(p, dst, src);
206 }
207 }
208 brw_set_saturate(p, 0);
209 }
210
211 static void emit_pixel_xy(struct brw_wm_compile *c,
212 struct prog_instruction *inst)
213 {
214 struct brw_reg r1 = brw_vec1_grf(1, 0);
215 struct brw_reg r1_uw = retype(r1, BRW_REGISTER_TYPE_UW);
216
217 struct brw_reg dst0, dst1;
218 struct brw_compile *p = &c->func;
219 GLuint mask = inst->DstReg.WriteMask;
220
221 dst0 = get_dst_reg(c, inst, 0, 1);
222 dst1 = get_dst_reg(c, inst, 1, 1);
223 /* Calculate pixel centers by adding 1 or 0 to each of the
224 * micro-tile coordinates passed in r1.
225 */
226 if (mask & WRITEMASK_X) {
227 brw_ADD(p,
228 vec8(retype(dst0, BRW_REGISTER_TYPE_UW)),
229 stride(suboffset(r1_uw, 4), 2, 4, 0),
230 brw_imm_v(0x10101010));
231 }
232
233 if (mask & WRITEMASK_Y) {
234 brw_ADD(p,
235 vec8(retype(dst1, BRW_REGISTER_TYPE_UW)),
236 stride(suboffset(r1_uw, 5), 2, 4, 0),
237 brw_imm_v(0x11001100));
238 }
239
240 }
241
242 static void emit_delta_xy(struct brw_wm_compile *c,
243 struct prog_instruction *inst)
244 {
245 struct brw_reg r1 = brw_vec1_grf(1, 0);
246 struct brw_reg dst0, dst1, src0, src1;
247 struct brw_compile *p = &c->func;
248 GLuint mask = inst->DstReg.WriteMask;
249
250 dst0 = get_dst_reg(c, inst, 0, 1);
251 dst1 = get_dst_reg(c, inst, 1, 1);
252 src0 = get_src_reg(c, &inst->SrcReg[0], 0, 1);
253 src1 = get_src_reg(c, &inst->SrcReg[0], 1, 1);
254 /* Calc delta X,Y by subtracting origin in r1 from the pixel
255 * centers.
256 */
257 if (mask & WRITEMASK_X) {
258 brw_ADD(p,
259 dst0,
260 retype(src0, BRW_REGISTER_TYPE_UW),
261 negate(r1));
262 }
263
264 if (mask & WRITEMASK_Y) {
265 brw_ADD(p,
266 dst1,
267 retype(src1, BRW_REGISTER_TYPE_UW),
268 negate(suboffset(r1,1)));
269
270 }
271
272 }
273
274
275 static void fire_fb_write( struct brw_wm_compile *c,
276 GLuint base_reg,
277 GLuint nr )
278 {
279 struct brw_compile *p = &c->func;
280
281 /* Pass through control information:
282 */
283 /* mov (8) m1.0<1>:ud r1.0<8;8,1>:ud { Align1 NoMask } */
284 {
285 brw_push_insn_state(p);
286 brw_set_mask_control(p, BRW_MASK_DISABLE); /* ? */
287 brw_MOV(p,
288 brw_message_reg(base_reg + 1),
289 brw_vec8_grf(1, 0));
290 brw_pop_insn_state(p);
291 }
292 /* Send framebuffer write message: */
293 brw_fb_WRITE(p,
294 retype(vec8(brw_null_reg()), BRW_REGISTER_TYPE_UW),
295 base_reg,
296 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW),
297 0, /* render surface always 0 */
298 nr,
299 0,
300 1);
301 }
302
303 static void emit_fb_write(struct brw_wm_compile *c,
304 struct prog_instruction *inst)
305 {
306 struct brw_compile *p = &c->func;
307 int nr = 2;
308 int channel;
309 struct brw_reg src0;//, src1, src2, dst;
310
311 /* Reserve a space for AA - may not be needed:
312 */
313 if (c->key.aa_dest_stencil_reg)
314 nr += 1;
315 {
316 brw_push_insn_state(p);
317 for (channel = 0; channel < 4; channel++) {
318 src0 = get_src_reg(c, &inst->SrcReg[0], channel, 1);
319 /* mov (8) m2.0<1>:ud r28.0<8;8,1>:ud { Align1 } */
320 /* mov (8) m6.0<1>:ud r29.0<8;8,1>:ud { Align1 SecHalf } */
321 brw_MOV(p, brw_message_reg(nr + channel), src0);
322 }
323 /* skip over the regs populated above: */
324 nr += 8;
325 brw_pop_insn_state(p);
326 }
327
328 if (c->key.source_depth_to_render_target)
329 {
330 if (c->key.computes_depth) {
331 src0 = get_src_reg(c, &inst->SrcReg[2], 2, 1);
332 brw_MOV(p, brw_message_reg(nr), src0);
333 } else {
334 src0 = get_src_reg(c, &inst->SrcReg[1], 1, 1);
335 brw_MOV(p, brw_message_reg(nr), src0);
336 }
337
338 nr += 2;
339 }
340
341 fire_fb_write(c, 0, nr);
342 }
343
344 static void emit_pixel_w( struct brw_wm_compile *c,
345 struct prog_instruction *inst)
346 {
347 struct brw_compile *p = &c->func;
348 GLuint mask = inst->DstReg.WriteMask;
349 if (mask & WRITEMASK_W) {
350 struct brw_reg dst, src0, delta0, delta1;
351 struct brw_reg interp3;
352
353 dst = get_dst_reg(c, inst, 3, 1);
354 src0 = get_src_reg(c, &inst->SrcReg[0], 0, 1);
355 delta0 = get_src_reg(c, &inst->SrcReg[1], 0, 1);
356 delta1 = get_src_reg(c, &inst->SrcReg[1], 1, 1);
357
358 interp3 = brw_vec1_grf(src0.nr+1, 4);
359 /* Calc 1/w - just linterp wpos[3] optimized by putting the
360 * result straight into a message reg.
361 */
362 brw_LINE(p, brw_null_reg(), interp3, delta0);
363 brw_MAC(p, brw_message_reg(2), suboffset(interp3, 1), delta1);
364
365 /* Calc w */
366 brw_math_16( p, dst,
367 BRW_MATH_FUNCTION_INV,
368 BRW_MATH_SATURATE_NONE,
369 2, brw_null_reg(),
370 BRW_MATH_PRECISION_FULL);
371 }
372 }
373
374 static void emit_linterp(struct brw_wm_compile *c,
375 struct prog_instruction *inst)
376 {
377 struct brw_compile *p = &c->func;
378 GLuint mask = inst->DstReg.WriteMask;
379 struct brw_reg interp[4];
380 struct brw_reg dst, delta0, delta1;
381 struct brw_reg src0;
382
383 src0 = get_src_reg(c, &inst->SrcReg[0], 0, 1);
384 delta0 = get_src_reg(c, &inst->SrcReg[1], 0, 1);
385 delta1 = get_src_reg(c, &inst->SrcReg[1], 1, 1);
386 GLuint nr = src0.nr;
387 int i;
388
389 interp[0] = brw_vec1_grf(nr, 0);
390 interp[1] = brw_vec1_grf(nr, 4);
391 interp[2] = brw_vec1_grf(nr+1, 0);
392 interp[3] = brw_vec1_grf(nr+1, 4);
393
394 for(i = 0; i < 4; i++ ) {
395 if (mask & (1<<i)) {
396 dst = get_dst_reg(c, inst, i, 1);
397 brw_LINE(p, brw_null_reg(), interp[i], delta0);
398 brw_MAC(p, dst, suboffset(interp[i],1), delta1);
399 }
400 }
401 }
402
403 static void emit_cinterp(struct brw_wm_compile *c,
404 struct prog_instruction *inst)
405 {
406 struct brw_compile *p = &c->func;
407 GLuint mask = inst->DstReg.WriteMask;
408
409 struct brw_reg interp[4];
410 struct brw_reg dst, src0;
411
412 src0 = get_src_reg(c, &inst->SrcReg[0], 0, 1);
413 GLuint nr = src0.nr;
414 int i;
415
416 interp[0] = brw_vec1_grf(nr, 0);
417 interp[1] = brw_vec1_grf(nr, 4);
418 interp[2] = brw_vec1_grf(nr+1, 0);
419 interp[3] = brw_vec1_grf(nr+1, 4);
420
421 for(i = 0; i < 4; i++ ) {
422 if (mask & (1<<i)) {
423 dst = get_dst_reg(c, inst, i, 1);
424 brw_MOV(p, dst, suboffset(interp[i],3));
425 }
426 }
427 }
428
429 static void emit_pinterp(struct brw_wm_compile *c,
430 struct prog_instruction *inst)
431 {
432 struct brw_compile *p = &c->func;
433 GLuint mask = inst->DstReg.WriteMask;
434
435 struct brw_reg interp[4];
436 struct brw_reg dst, delta0, delta1;
437 struct brw_reg src0, w;
438
439 src0 = get_src_reg(c, &inst->SrcReg[0], 0, 1);
440 delta0 = get_src_reg(c, &inst->SrcReg[1], 0, 1);
441 delta1 = get_src_reg(c, &inst->SrcReg[1], 1, 1);
442 w = get_src_reg(c, &inst->SrcReg[2], 3, 1);
443 GLuint nr = src0.nr;
444 int i;
445
446 interp[0] = brw_vec1_grf(nr, 0);
447 interp[1] = brw_vec1_grf(nr, 4);
448 interp[2] = brw_vec1_grf(nr+1, 0);
449 interp[3] = brw_vec1_grf(nr+1, 4);
450
451 for(i = 0; i < 4; i++ ) {
452 if (mask & (1<<i)) {
453 dst = get_dst_reg(c, inst, i, 1);
454 brw_LINE(p, brw_null_reg(), interp[i], delta0);
455 brw_MAC(p, dst, suboffset(interp[i],1),
456 delta1);
457 brw_MUL(p, dst, dst, w);
458 }
459 }
460 }
461
462 static void emit_xpd(struct brw_wm_compile *c,
463 struct prog_instruction *inst)
464 {
465 int i;
466 struct brw_compile *p = &c->func;
467 GLuint mask = inst->DstReg.WriteMask;
468 for (i = 0; i < 4; i++) {
469 GLuint i2 = (i+2)%3;
470 GLuint i1 = (i+1)%3;
471 if (mask & (1<<i)) {
472 struct brw_reg src0, src1, dst;
473 dst = get_dst_reg(c, inst, i, 1);
474 src0 = negate(get_src_reg(c, &inst->SrcReg[0], i2, 1));
475 src1 = get_src_reg(c, &inst->SrcReg[1], i1, 1);
476 brw_MUL(p, brw_null_reg(), src0, src1);
477 src0 = get_src_reg(c, &inst->SrcReg[0], i1, 1);
478 src1 = get_src_reg(c, &inst->SrcReg[1], i2, 1);
479 brw_set_saturate(p, inst->SaturateMode != SATURATE_OFF);
480 brw_MAC(p, dst, src0, src1);
481 brw_set_saturate(p, 0);
482 }
483 }
484 brw_set_saturate(p, 0);
485 }
486
487 static void emit_dp3(struct brw_wm_compile *c,
488 struct prog_instruction *inst)
489 {
490 struct brw_reg src0[3], src1[3], dst;
491 int i;
492 struct brw_compile *p = &c->func;
493 for (i = 0; i < 3; i++) {
494 src0[i] = get_src_reg(c, &inst->SrcReg[0], i, 1);
495 src1[i] = get_src_reg(c, &inst->SrcReg[1], i, 1);
496 }
497
498 dst = get_dst_reg(c, inst, get_scalar_dst_index(inst), 1);
499 brw_MUL(p, brw_null_reg(), src0[0], src1[0]);
500 brw_MAC(p, brw_null_reg(), src0[1], src1[1]);
501 brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0);
502 brw_MAC(p, dst, src0[2], src1[2]);
503 brw_set_saturate(p, 0);
504 }
505
506 static void emit_dp4(struct brw_wm_compile *c,
507 struct prog_instruction *inst)
508 {
509 struct brw_reg src0[4], src1[4], dst;
510 int i;
511 struct brw_compile *p = &c->func;
512 for (i = 0; i < 4; i++) {
513 src0[i] = get_src_reg(c, &inst->SrcReg[0], i, 1);
514 src1[i] = get_src_reg(c, &inst->SrcReg[1], i, 1);
515 }
516 dst = get_dst_reg(c, inst, get_scalar_dst_index(inst), 1);
517 brw_MUL(p, brw_null_reg(), src0[0], src1[0]);
518 brw_MAC(p, brw_null_reg(), src0[1], src1[1]);
519 brw_MAC(p, brw_null_reg(), src0[2], src1[2]);
520 brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0);
521 brw_MAC(p, dst, src0[3], src1[3]);
522 brw_set_saturate(p, 0);
523 }
524
525 static void emit_dph(struct brw_wm_compile *c,
526 struct prog_instruction *inst)
527 {
528 struct brw_reg src0[4], src1[4], dst;
529 int i;
530 struct brw_compile *p = &c->func;
531 for (i = 0; i < 4; i++) {
532 src0[i] = get_src_reg(c, &inst->SrcReg[0], i, 1);
533 src1[i] = get_src_reg(c, &inst->SrcReg[1], i, 1);
534 }
535 dst = get_dst_reg(c, inst, get_scalar_dst_index(inst), 1);
536 brw_MUL(p, brw_null_reg(), src0[0], src1[0]);
537 brw_MAC(p, brw_null_reg(), src0[1], src1[1]);
538 brw_MAC(p, dst, src0[2], src1[2]);
539 brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0);
540 brw_ADD(p, dst, src0[3], src1[3]);
541 brw_set_saturate(p, 0);
542 }
543
544 static void emit_math1(struct brw_wm_compile *c,
545 struct prog_instruction *inst, GLuint func)
546 {
547 struct brw_compile *p = &c->func;
548 struct brw_reg src0, dst;
549
550 src0 = get_src_reg(c, &inst->SrcReg[0], 0, 1);
551 dst = get_dst_reg(c, inst, get_scalar_dst_index(inst), 1);
552 brw_MOV(p, brw_message_reg(2), src0);
553 brw_math(p,
554 dst,
555 func,
556 (inst->SaturateMode != SATURATE_OFF) ? BRW_MATH_SATURATE_SATURATE : BRW_MATH_SATURATE_NONE,
557 2,
558 brw_null_reg(),
559 BRW_MATH_DATA_VECTOR,
560 BRW_MATH_PRECISION_FULL);
561 }
562
563 static void emit_rcp(struct brw_wm_compile *c,
564 struct prog_instruction *inst)
565 {
566 emit_math1(c, inst, BRW_MATH_FUNCTION_INV);
567 }
568
569 static void emit_rsq(struct brw_wm_compile *c,
570 struct prog_instruction *inst)
571 {
572 emit_math1(c, inst, BRW_MATH_FUNCTION_RSQ);
573 }
574
575 static void emit_sin(struct brw_wm_compile *c,
576 struct prog_instruction *inst)
577 {
578 emit_math1(c, inst, BRW_MATH_FUNCTION_SIN);
579 }
580
581 static void emit_cos(struct brw_wm_compile *c,
582 struct prog_instruction *inst)
583 {
584 emit_math1(c, inst, BRW_MATH_FUNCTION_COS);
585 }
586
587 static void emit_ex2(struct brw_wm_compile *c,
588 struct prog_instruction *inst)
589 {
590 emit_math1(c, inst, BRW_MATH_FUNCTION_EXP);
591 }
592
593 static void emit_lg2(struct brw_wm_compile *c,
594 struct prog_instruction *inst)
595 {
596 emit_math1(c, inst, BRW_MATH_FUNCTION_LOG);
597 }
598
599 static void emit_add(struct brw_wm_compile *c,
600 struct prog_instruction *inst)
601 {
602 struct brw_compile *p = &c->func;
603 struct brw_reg src0, src1, dst;
604 GLuint mask = inst->DstReg.WriteMask;
605 int i;
606 brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0);
607 for (i = 0 ; i < 4; i++) {
608 if (mask & (1<<i)) {
609 dst = get_dst_reg(c, inst, i, 1);
610 src0 = get_src_reg(c, &inst->SrcReg[0], i, 1);
611 src1 = get_src_reg(c, &inst->SrcReg[1], i, 1);
612 brw_ADD(p, dst, src0, src1);
613 }
614 }
615 brw_set_saturate(p, 0);
616 }
617
618 static void emit_sub(struct brw_wm_compile *c,
619 struct prog_instruction *inst)
620 {
621 struct brw_compile *p = &c->func;
622 struct brw_reg src0, src1, dst;
623 GLuint mask = inst->DstReg.WriteMask;
624 int i;
625 brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0);
626 for (i = 0 ; i < 4; i++) {
627 if (mask & (1<<i)) {
628 dst = get_dst_reg(c, inst, i, 1);
629 src0 = get_src_reg(c, &inst->SrcReg[0], i, 1);
630 src1 = get_src_reg(c, &inst->SrcReg[1], i, 1);
631 brw_ADD(p, dst, src0, negate(src1));
632 }
633 }
634 brw_set_saturate(p, 0);
635 }
636
637 static void emit_mul(struct brw_wm_compile *c,
638 struct prog_instruction *inst)
639 {
640 struct brw_compile *p = &c->func;
641 struct brw_reg src0, src1, dst;
642 GLuint mask = inst->DstReg.WriteMask;
643 int i;
644 brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0);
645 for (i = 0 ; i < 4; i++) {
646 if (mask & (1<<i)) {
647 dst = get_dst_reg(c, inst, i, 1);
648 src0 = get_src_reg(c, &inst->SrcReg[0], i, 1);
649 src1 = get_src_reg(c, &inst->SrcReg[1], i, 1);
650 brw_MUL(p, dst, src0, src1);
651 }
652 }
653 brw_set_saturate(p, 0);
654 }
655
656 static void emit_frc(struct brw_wm_compile *c,
657 struct prog_instruction *inst)
658 {
659 struct brw_compile *p = &c->func;
660 struct brw_reg src0, dst;
661 GLuint mask = inst->DstReg.WriteMask;
662 int i;
663 brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0);
664 for (i = 0 ; i < 4; i++) {
665 if (mask & (1<<i)) {
666 dst = get_dst_reg(c, inst, i, 1);
667 src0 = get_src_reg(c, &inst->SrcReg[0], i, 1);
668 brw_FRC(p, dst, src0);
669 }
670 }
671 if (inst->SaturateMode != SATURATE_OFF)
672 brw_set_saturate(p, 0);
673 }
674
675 static void emit_flr(struct brw_wm_compile *c,
676 struct prog_instruction *inst)
677 {
678 struct brw_compile *p = &c->func;
679 struct brw_reg src0, dst;
680 GLuint mask = inst->DstReg.WriteMask;
681 int i;
682 brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0);
683 for (i = 0 ; i < 4; i++) {
684 if (mask & (1<<i)) {
685 dst = get_dst_reg(c, inst, i, 1);
686 src0 = get_src_reg(c, &inst->SrcReg[0], i, 1);
687 brw_RNDD(p, dst, src0);
688 }
689 }
690 brw_set_saturate(p, 0);
691 }
692
693 static void emit_max(struct brw_wm_compile *c,
694 struct prog_instruction *inst)
695 {
696 struct brw_compile *p = &c->func;
697 GLuint mask = inst->DstReg.WriteMask;
698 struct brw_reg src0, src1, dst;
699 int i;
700 brw_push_insn_state(p);
701 for (i = 0; i < 4; i++) {
702 if (mask & (1<<i)) {
703 dst = get_dst_reg(c, inst, i, 1);
704 src0 = get_src_reg(c, &inst->SrcReg[0], i, 1);
705 src1 = get_src_reg(c, &inst->SrcReg[1], i, 1);
706 brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0);
707 brw_MOV(p, dst, src0);
708 brw_set_saturate(p, 0);
709
710 brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_L, src0, src1);
711 brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0);
712 brw_set_predicate_control(p, BRW_PREDICATE_NORMAL);
713 brw_MOV(p, dst, src1);
714 brw_set_saturate(p, 0);
715 brw_set_predicate_control_flag_value(p, 0xff);
716 }
717 }
718 brw_pop_insn_state(p);
719 }
720
721 static void emit_min(struct brw_wm_compile *c,
722 struct prog_instruction *inst)
723 {
724 struct brw_compile *p = &c->func;
725 GLuint mask = inst->DstReg.WriteMask;
726 struct brw_reg src0, src1, dst;
727 int i;
728 brw_push_insn_state(p);
729 for (i = 0; i < 4; i++) {
730 if (mask & (1<<i)) {
731 dst = get_dst_reg(c, inst, i, 1);
732 src0 = get_src_reg(c, &inst->SrcReg[0], i, 1);
733 src1 = get_src_reg(c, &inst->SrcReg[1], i, 1);
734 brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0);
735 brw_MOV(p, dst, src0);
736 brw_set_saturate(p, 0);
737
738 brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_L, src1, src0);
739 brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0);
740 brw_set_predicate_control(p, BRW_PREDICATE_NORMAL);
741 brw_MOV(p, dst, src1);
742 brw_set_saturate(p, 0);
743 brw_set_predicate_control_flag_value(p, 0xff);
744 }
745 }
746 brw_pop_insn_state(p);
747 }
748
749 static void emit_pow(struct brw_wm_compile *c,
750 struct prog_instruction *inst)
751 {
752 struct brw_compile *p = &c->func;
753 struct brw_reg dst, src0, src1;
754 dst = get_dst_reg(c, inst, get_scalar_dst_index(inst), 1);
755 src0 = get_src_reg(c, &inst->SrcReg[0], 0, 1);
756 src1 = get_src_reg(c, &inst->SrcReg[1], 0, 1);
757
758 brw_MOV(p, brw_message_reg(2), src0);
759 brw_MOV(p, brw_message_reg(3), src1);
760
761 brw_math(p,
762 dst,
763 BRW_MATH_FUNCTION_POW,
764 (inst->SaturateMode != SATURATE_OFF) ? BRW_MATH_SATURATE_SATURATE : BRW_MATH_SATURATE_NONE,
765 2,
766 brw_null_reg(),
767 BRW_MATH_DATA_VECTOR,
768 BRW_MATH_PRECISION_FULL);
769 }
770
771 static void emit_lrp(struct brw_wm_compile *c,
772 struct prog_instruction *inst)
773 {
774 struct brw_compile *p = &c->func;
775 GLuint mask = inst->DstReg.WriteMask;
776 struct brw_reg dst, tmp1, tmp2, src0, src1, src2;
777 int i;
778 for (i = 0; i < 4; i++) {
779 if (mask & (1<<i)) {
780 dst = get_dst_reg(c, inst, i, 1);
781 src0 = get_src_reg(c, &inst->SrcReg[0], i, 1);
782
783 src1 = get_src_reg(c, &inst->SrcReg[1], i, 1);
784
785 if (src1.nr == dst.nr) {
786 tmp1 = alloc_tmp(c);
787 brw_MOV(p, tmp1, src1);
788 } else
789 tmp1 = src1;
790
791 src2 = get_src_reg(c, &inst->SrcReg[2], i, 1);
792 if (src2.nr == dst.nr) {
793 tmp2 = alloc_tmp(c);
794 brw_MOV(p, tmp2, src2);
795 } else
796 tmp2 = src2;
797
798 brw_ADD(p, dst, negate(src0), brw_imm_f(1.0));
799 brw_MUL(p, brw_null_reg(), dst, tmp2);
800 brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0);
801 brw_MAC(p, dst, src0, tmp1);
802 brw_set_saturate(p, 0);
803 }
804 release_tmps(c);
805 }
806 }
807
808 static void emit_kil(struct brw_wm_compile *c)
809 {
810 struct brw_compile *p = &c->func;
811 struct brw_reg depth = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
812 brw_push_insn_state(p);
813 brw_set_mask_control(p, BRW_MASK_DISABLE);
814 brw_NOT(p, c->emit_mask_reg, brw_mask_reg(1)); //IMASK
815 brw_AND(p, depth, c->emit_mask_reg, depth);
816 brw_pop_insn_state(p);
817 }
818
819 static void emit_mad(struct brw_wm_compile *c,
820 struct prog_instruction *inst)
821 {
822 struct brw_compile *p = &c->func;
823 GLuint mask = inst->DstReg.WriteMask;
824 struct brw_reg dst, src0, src1, src2;
825 int i;
826
827 for (i = 0; i < 4; i++) {
828 if (mask & (1<<i)) {
829 dst = get_dst_reg(c, inst, i, 1);
830 src0 = get_src_reg(c, &inst->SrcReg[0], i, 1);
831 src1 = get_src_reg(c, &inst->SrcReg[1], i, 1);
832 src2 = get_src_reg(c, &inst->SrcReg[2], i, 1);
833 brw_MUL(p, dst, src0, src1);
834
835 brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0);
836 brw_ADD(p, dst, dst, src2);
837 brw_set_saturate(p, 0);
838 }
839 }
840 }
841
842 static void emit_sop(struct brw_wm_compile *c,
843 struct prog_instruction *inst, GLuint cond)
844 {
845 struct brw_compile *p = &c->func;
846 GLuint mask = inst->DstReg.WriteMask;
847 struct brw_reg dst, src0, src1;
848 int i;
849
850 brw_push_insn_state(p);
851 for (i = 0; i < 4; i++) {
852 if (mask & (1<<i)) {
853 dst = get_dst_reg(c, inst, i, 1);
854 src0 = get_src_reg(c, &inst->SrcReg[0], i, 1);
855 src1 = get_src_reg(c, &inst->SrcReg[1], i, 1);
856 brw_CMP(p, brw_null_reg(), cond, src0, src1);
857 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
858 brw_MOV(p, dst, brw_imm_f(0.0));
859 brw_set_predicate_control(p, BRW_PREDICATE_NORMAL);
860 brw_MOV(p, dst, brw_imm_f(1.0));
861 }
862 }
863 brw_pop_insn_state(p);
864 }
865
866 static void emit_slt(struct brw_wm_compile *c,
867 struct prog_instruction *inst)
868 {
869 emit_sop(c, inst, BRW_CONDITIONAL_L);
870 }
871
872 static void emit_sle(struct brw_wm_compile *c,
873 struct prog_instruction *inst)
874 {
875 emit_sop(c, inst, BRW_CONDITIONAL_LE);
876 }
877
878 static void emit_sgt(struct brw_wm_compile *c,
879 struct prog_instruction *inst)
880 {
881 emit_sop(c, inst, BRW_CONDITIONAL_G);
882 }
883
884 static void emit_sge(struct brw_wm_compile *c,
885 struct prog_instruction *inst)
886 {
887 emit_sop(c, inst, BRW_CONDITIONAL_GE);
888 }
889
890 static void emit_seq(struct brw_wm_compile *c,
891 struct prog_instruction *inst)
892 {
893 emit_sop(c, inst, BRW_CONDITIONAL_EQ);
894 }
895
896 static void emit_sne(struct brw_wm_compile *c,
897 struct prog_instruction *inst)
898 {
899 emit_sop(c, inst, BRW_CONDITIONAL_NEQ);
900 }
901
902 static void emit_ddx(struct brw_wm_compile *c,
903 struct prog_instruction *inst)
904 {
905 struct brw_compile *p = &c->func;
906 GLuint mask = inst->DstReg.WriteMask;
907 struct brw_reg interp[4];
908 struct brw_reg dst;
909 struct brw_reg src0, w;
910 GLuint nr, i;
911 src0 = get_src_reg(c, &inst->SrcReg[0], 0, 1);
912 w = get_src_reg(c, &inst->SrcReg[1], 3, 1);
913 nr = src0.nr;
914 interp[0] = brw_vec1_grf(nr, 0);
915 interp[1] = brw_vec1_grf(nr, 4);
916 interp[2] = brw_vec1_grf(nr+1, 0);
917 interp[3] = brw_vec1_grf(nr+1, 4);
918 brw_set_saturate(p, inst->SaturateMode != SATURATE_OFF);
919 for(i = 0; i < 4; i++ ) {
920 if (mask & (1<<i)) {
921 dst = get_dst_reg(c, inst, i, 1);
922 brw_MOV(p, dst, interp[i]);
923 brw_MUL(p, dst, dst, w);
924 }
925 }
926 brw_set_saturate(p, 0);
927 }
928
929 static void emit_ddy(struct brw_wm_compile *c,
930 struct prog_instruction *inst)
931 {
932 struct brw_compile *p = &c->func;
933 GLuint mask = inst->DstReg.WriteMask;
934 struct brw_reg interp[4];
935 struct brw_reg dst;
936 struct brw_reg src0, w;
937 GLuint nr, i;
938
939 src0 = get_src_reg(c, &inst->SrcReg[0], 0, 1);
940 nr = src0.nr;
941 w = get_src_reg(c, &inst->SrcReg[1], 3, 1);
942 interp[0] = brw_vec1_grf(nr, 0);
943 interp[1] = brw_vec1_grf(nr, 4);
944 interp[2] = brw_vec1_grf(nr+1, 0);
945 interp[3] = brw_vec1_grf(nr+1, 4);
946 brw_set_saturate(p, inst->SaturateMode != SATURATE_OFF);
947 for(i = 0; i < 4; i++ ) {
948 if (mask & (1<<i)) {
949 dst = get_dst_reg(c, inst, i, 1);
950 brw_MOV(p, dst, suboffset(interp[i], 1));
951 brw_MUL(p, dst, dst, w);
952 }
953 }
954 brw_set_saturate(p, 0);
955 }
956
957 static void emit_wpos_xy(struct brw_wm_compile *c,
958 struct prog_instruction *inst)
959 {
960 struct brw_compile *p = &c->func;
961 GLuint mask = inst->DstReg.WriteMask;
962 struct brw_reg src0[2], dst[2];
963
964 dst[0] = get_dst_reg(c, inst, 0, 1);
965 dst[1] = get_dst_reg(c, inst, 1, 1);
966
967 src0[0] = get_src_reg(c, &inst->SrcReg[0], 0, 1);
968 src0[1] = get_src_reg(c, &inst->SrcReg[0], 1, 1);
969
970 /* Calc delta X,Y by subtracting origin in r1 from the pixel
971 * centers.
972 */
973 if (mask & WRITEMASK_X) {
974 brw_MOV(p,
975 dst[0],
976 retype(src0[0], BRW_REGISTER_TYPE_UW));
977 }
978
979 if (mask & WRITEMASK_Y) {
980 /* TODO -- window_height - Y */
981 brw_MOV(p,
982 dst[1],
983 retype(src0[1], BRW_REGISTER_TYPE_UW));
984
985 }
986 }
987
988 /* TODO
989 BIAS on SIMD8 not workind yet...
990 */
991 static void emit_txb(struct brw_wm_compile *c,
992 struct prog_instruction *inst)
993 {
994 struct brw_compile *p = &c->func;
995 struct brw_reg dst[4], src[4], payload_reg;
996 GLuint i;
997 payload_reg = get_reg(c, PROGRAM_PAYLOAD, PAYLOAD_DEPTH, 0, 1, 0, 0);
998 for (i = 0; i < 4; i++)
999 dst[i] = get_dst_reg(c, inst, i, 1);
1000 for (i = 0; i < 4; i++)
1001 src[i] = get_src_reg(c, &inst->SrcReg[0], i, 1);
1002
1003 switch (inst->TexSrcTarget) {
1004 case TEXTURE_1D_INDEX:
1005 brw_MOV(p, brw_message_reg(2), src[0]);
1006 brw_MOV(p, brw_message_reg(3), brw_imm_f(0));
1007 brw_MOV(p, brw_message_reg(4), brw_imm_f(0));
1008 break;
1009 case TEXTURE_2D_INDEX:
1010 case TEXTURE_RECT_INDEX:
1011 brw_MOV(p, brw_message_reg(2), src[0]);
1012 brw_MOV(p, brw_message_reg(3), src[1]);
1013 brw_MOV(p, brw_message_reg(4), brw_imm_f(0));
1014 break;
1015 default:
1016 brw_MOV(p, brw_message_reg(2), src[0]);
1017 brw_MOV(p, brw_message_reg(3), src[1]);
1018 brw_MOV(p, brw_message_reg(4), src[2]);
1019 break;
1020 }
1021 brw_MOV(p, brw_message_reg(5), src[3]);
1022 brw_MOV(p, brw_message_reg(6), brw_imm_f(0));
1023 brw_SAMPLE(p,
1024 retype(vec8(dst[0]), BRW_REGISTER_TYPE_UW),
1025 1,
1026 retype(payload_reg, BRW_REGISTER_TYPE_UW),
1027 inst->TexSrcUnit + 1, /* surface */
1028 inst->TexSrcUnit, /* sampler */
1029 inst->DstReg.WriteMask,
1030 BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS,
1031 4,
1032 4,
1033 0);
1034 }
1035
1036 static void emit_tex(struct brw_wm_compile *c,
1037 struct prog_instruction *inst)
1038 {
1039 struct brw_compile *p = &c->func;
1040 struct brw_reg dst[4], src[4], payload_reg;
1041 GLuint msg_len;
1042 GLuint i, nr;
1043 GLuint emit;
1044 GLboolean shadow = (c->key.shadowtex_mask & (1<<inst->TexSrcUnit)) ? 1 : 0;
1045
1046 payload_reg = get_reg(c, PROGRAM_PAYLOAD, PAYLOAD_DEPTH, 0, 1, 0, 0);
1047
1048 for (i = 0; i < 4; i++)
1049 dst[i] = get_dst_reg(c, inst, i, 1);
1050 for (i = 0; i < 4; i++)
1051 src[i] = get_src_reg(c, &inst->SrcReg[0], i, 1);
1052
1053
1054 switch (inst->TexSrcTarget) {
1055 case TEXTURE_1D_INDEX:
1056 emit = WRITEMASK_X;
1057 nr = 1;
1058 break;
1059 case TEXTURE_2D_INDEX:
1060 case TEXTURE_RECT_INDEX:
1061 emit = WRITEMASK_XY;
1062 nr = 2;
1063 break;
1064 default:
1065 emit = WRITEMASK_XYZ;
1066 nr = 3;
1067 break;
1068 }
1069 msg_len = 1;
1070
1071 for (i = 0; i < nr; i++) {
1072 static const GLuint swz[4] = {0,1,2,2};
1073 if (emit & (1<<i))
1074 brw_MOV(p, brw_message_reg(msg_len+1), src[swz[i]]);
1075 else
1076 brw_MOV(p, brw_message_reg(msg_len+1), brw_imm_f(0));
1077 msg_len += 1;
1078 }
1079
1080 if (shadow) {
1081 brw_MOV(p, brw_message_reg(5), brw_imm_f(0));
1082 brw_MOV(p, brw_message_reg(6), src[2]);
1083 }
1084
1085 brw_SAMPLE(p,
1086 retype(vec8(dst[0]), BRW_REGISTER_TYPE_UW),
1087 1,
1088 retype(payload_reg, BRW_REGISTER_TYPE_UW),
1089 inst->TexSrcUnit + 1, /* surface */
1090 inst->TexSrcUnit, /* sampler */
1091 inst->DstReg.WriteMask,
1092 BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE,
1093 4,
1094 shadow ? 6 : 4,
1095 0);
1096
1097 if (shadow)
1098 brw_MOV(p, dst[3], brw_imm_f(1.0));
1099 }
1100
1101 static void post_wm_emit( struct brw_wm_compile *c )
1102 {
1103 GLuint nr_insns = c->fp->program.Base.NumInstructions;
1104 GLuint insn, target_insn;
1105 struct prog_instruction *inst1, *inst2;
1106 struct brw_instruction *brw_inst1, *brw_inst2;
1107 int offset;
1108 for (insn = 0; insn < nr_insns; insn++) {
1109 inst1 = &c->fp->program.Base.Instructions[insn];
1110 brw_inst1 = inst1->Data;
1111 switch (inst1->Opcode) {
1112 case OPCODE_CAL:
1113 target_insn = inst1->BranchTarget;
1114 inst2 = &c->fp->program.Base.Instructions[target_insn];
1115 brw_inst2 = inst2->Data;
1116 offset = brw_inst2 - brw_inst1;
1117 brw_set_src1(brw_inst1, brw_imm_d(offset*16));
1118 break;
1119 default:
1120 break;
1121 }
1122 }
1123 }
1124
1125 static void brw_wm_emit_glsl(struct brw_wm_compile *c)
1126
1127 {
1128 #define MAX_IFSN 32
1129 #define MAX_LOOP_DEPTH 32
1130 struct brw_instruction *if_inst[MAX_IFSN], *loop_inst[MAX_LOOP_DEPTH];
1131 struct brw_instruction *inst0, *inst1;
1132 int i, if_insn = 0, loop_insn = 0;
1133 struct brw_compile *p = &c->func;
1134 struct brw_indirect stack_index = brw_indirect(0, 0);
1135
1136 brw_init_compile(&c->func);
1137 c->reg_index = 0;
1138 prealloc_reg(c);
1139 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
1140 brw_MOV(p, get_addr_reg(stack_index), brw_address(c->stack));
1141
1142 for (i = 0; i < c->nr_fp_insns; i++) {
1143 struct prog_instruction *inst = &c->prog_instructions[i];
1144 struct prog_instruction *orig_inst;
1145
1146 if ((orig_inst = inst->Data) != 0)
1147 orig_inst->Data = current_insn(p);
1148
1149 if (inst->CondUpdate)
1150 brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ);
1151 else
1152 brw_set_conditionalmod(p, BRW_CONDITIONAL_NONE);
1153
1154 switch (inst->Opcode) {
1155 case WM_PIXELXY:
1156 emit_pixel_xy(c, inst);
1157 break;
1158 case WM_DELTAXY:
1159 emit_delta_xy(c, inst);
1160 break;
1161 case WM_PIXELW:
1162 emit_pixel_w(c, inst);
1163 break;
1164 case WM_LINTERP:
1165 emit_linterp(c, inst);
1166 break;
1167 case WM_PINTERP:
1168 emit_pinterp(c, inst);
1169 break;
1170 case WM_CINTERP:
1171 emit_cinterp(c, inst);
1172 break;
1173 case WM_WPOSXY:
1174 emit_wpos_xy(c, inst);
1175 break;
1176 case WM_FB_WRITE:
1177 emit_fb_write(c, inst);
1178 break;
1179 case OPCODE_ABS:
1180 emit_abs(c, inst);
1181 break;
1182 case OPCODE_ADD:
1183 emit_add(c, inst);
1184 break;
1185 case OPCODE_SUB:
1186 emit_sub(c, inst);
1187 break;
1188 case OPCODE_FRC:
1189 emit_frc(c, inst);
1190 break;
1191 case OPCODE_FLR:
1192 emit_flr(c, inst);
1193 break;
1194 case OPCODE_LRP:
1195 emit_lrp(c, inst);
1196 break;
1197 case OPCODE_INT:
1198 emit_int(c, inst);
1199 break;
1200 case OPCODE_MOV:
1201 emit_mov(c, inst);
1202 break;
1203 case OPCODE_DP3:
1204 emit_dp3(c, inst);
1205 break;
1206 case OPCODE_DP4:
1207 emit_dp4(c, inst);
1208 break;
1209 case OPCODE_XPD:
1210 emit_xpd(c, inst);
1211 break;
1212 case OPCODE_DPH:
1213 emit_dph(c, inst);
1214 break;
1215 case OPCODE_RCP:
1216 emit_rcp(c, inst);
1217 break;
1218 case OPCODE_RSQ:
1219 emit_rsq(c, inst);
1220 break;
1221 case OPCODE_SIN:
1222 emit_sin(c, inst);
1223 break;
1224 case OPCODE_COS:
1225 emit_cos(c, inst);
1226 break;
1227 case OPCODE_EX2:
1228 emit_ex2(c, inst);
1229 break;
1230 case OPCODE_LG2:
1231 emit_lg2(c, inst);
1232 break;
1233 case OPCODE_MAX:
1234 emit_max(c, inst);
1235 break;
1236 case OPCODE_MIN:
1237 emit_min(c, inst);
1238 break;
1239 case OPCODE_DDX:
1240 emit_ddx(c, inst);
1241 break;
1242 case OPCODE_DDY:
1243 emit_ddy(c, inst);
1244 break;
1245 case OPCODE_SLT:
1246 emit_slt(c, inst);
1247 break;
1248 case OPCODE_SLE:
1249 emit_sle(c, inst);
1250 break;
1251 case OPCODE_SGT:
1252 emit_sgt(c, inst);
1253 break;
1254 case OPCODE_SGE:
1255 emit_sge(c, inst);
1256 break;
1257 case OPCODE_SEQ:
1258 emit_seq(c, inst);
1259 break;
1260 case OPCODE_SNE:
1261 emit_sne(c, inst);
1262 break;
1263 case OPCODE_MUL:
1264 emit_mul(c, inst);
1265 break;
1266 case OPCODE_POW:
1267 emit_pow(c, inst);
1268 break;
1269 case OPCODE_MAD:
1270 emit_mad(c, inst);
1271 break;
1272 case OPCODE_TEX:
1273 emit_tex(c, inst);
1274 break;
1275 case OPCODE_TXB:
1276 emit_txb(c, inst);
1277 break;
1278 case OPCODE_KIL_NV:
1279 emit_kil(c);
1280 break;
1281 case OPCODE_IF:
1282 assert(if_insn < MAX_IFSN);
1283 if_inst[if_insn++] = brw_IF(p, BRW_EXECUTE_8);
1284 break;
1285 case OPCODE_ELSE:
1286 if_inst[if_insn-1] = brw_ELSE(p, if_inst[if_insn-1]);
1287 break;
1288 case OPCODE_ENDIF:
1289 assert(if_insn > 0);
1290 brw_ENDIF(p, if_inst[--if_insn]);
1291 break;
1292 case OPCODE_BGNSUB:
1293 case OPCODE_ENDSUB:
1294 break;
1295 case OPCODE_CAL:
1296 brw_push_insn_state(p);
1297 brw_set_mask_control(p, BRW_MASK_DISABLE);
1298 brw_set_access_mode(p, BRW_ALIGN_1);
1299 brw_ADD(p, deref_1ud(stack_index, 0), brw_ip_reg(), brw_imm_d(3*16));
1300 brw_set_access_mode(p, BRW_ALIGN_16);
1301 brw_ADD(p, get_addr_reg(stack_index),
1302 get_addr_reg(stack_index), brw_imm_d(4));
1303 orig_inst = inst->Data;
1304 orig_inst->Data = &p->store[p->nr_insn];
1305 brw_ADD(p, brw_ip_reg(), brw_ip_reg(), brw_imm_d(1*16));
1306 brw_pop_insn_state(p);
1307 break;
1308
1309 case OPCODE_RET:
1310 brw_push_insn_state(p);
1311 brw_set_mask_control(p, BRW_MASK_DISABLE);
1312 brw_ADD(p, get_addr_reg(stack_index),
1313 get_addr_reg(stack_index), brw_imm_d(-4));
1314 brw_set_access_mode(p, BRW_ALIGN_1);
1315 brw_MOV(p, brw_ip_reg(), deref_1ud(stack_index, 0));
1316 brw_set_access_mode(p, BRW_ALIGN_16);
1317 brw_pop_insn_state(p);
1318
1319 break;
1320 case OPCODE_BGNLOOP:
1321 loop_inst[loop_insn++] = brw_DO(p, BRW_EXECUTE_8);
1322 break;
1323 case OPCODE_BRK:
1324 brw_BREAK(p);
1325 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
1326 break;
1327 case OPCODE_CONT:
1328 brw_CONT(p);
1329 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
1330 break;
1331 case OPCODE_ENDLOOP:
1332 loop_insn--;
1333 inst0 = inst1 = brw_WHILE(p, loop_inst[loop_insn]);
1334 /* patch all the BREAK instructions from
1335 last BEGINLOOP */
1336 while (inst0 > loop_inst[loop_insn]) {
1337 inst0--;
1338 if (inst0->header.opcode == BRW_OPCODE_BREAK) {
1339 inst0->bits3.if_else.jump_count = inst1 - inst0 + 1;
1340 inst0->bits3.if_else.pop_count = 0;
1341 } else if (inst0->header.opcode == BRW_OPCODE_CONTINUE) {
1342 inst0->bits3.if_else.jump_count = inst1 - inst0;
1343 inst0->bits3.if_else.pop_count = 0;
1344 }
1345 }
1346 break;
1347 default:
1348 _mesa_printf("unsupported IR in fragment shader %d\n",
1349 inst->Opcode);
1350 }
1351 if (inst->CondUpdate)
1352 brw_set_predicate_control(p, BRW_PREDICATE_NORMAL);
1353 else
1354 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
1355 }
1356 post_wm_emit(c);
1357 for (i = 0; i < c->fp->program.Base.NumInstructions; i++)
1358 c->fp->program.Base.Instructions[i].Data = NULL;
1359 }
1360
1361 void brw_wm_glsl_emit(struct brw_wm_compile *c)
1362 {
1363 brw_wm_pass_fp(c);
1364 c->tmp_index = 127;
1365 brw_wm_emit_glsl(c);
1366 c->prog_data.total_grf = c->reg_index;
1367 c->prog_data.total_scratch = 0;
1368 }