src/mesa/drivers/dri/i965/brw_wm_glsl.c

   1 #include "main/macros.h"
   2 #include "shader/prog_parameter.h"
   3 #include "brw_context.h"
   4 #include "brw_eu.h"
   5 #include "brw_wm.h"
   6
   7 /* Only guess, need a flag in gl_fragment_program later */
   8 GLboolean brw_wm_is_glsl(const struct gl_fragment_program *fp)
   9 {
  10     int i;
  11     for (i = 0; i < fp->Base.NumInstructions; i++) {
  12         struct prog_instruction *inst = &fp->Base.Instructions[i];
  13         switch (inst->Opcode) {
  14             case OPCODE_IF:
  15             case OPCODE_INT:
  16             case OPCODE_ENDIF:
  17             case OPCODE_CAL:
  18             case OPCODE_BRK:
  19             case OPCODE_RET:
  20             case OPCODE_DDX:
  21             case OPCODE_DDY:
  22             case OPCODE_BGNLOOP:
  23                 return GL_TRUE;
  24             default:
  25                 break;
  26         }
  27     }
  28     return GL_FALSE;
  29 }
  30
  31 static void set_reg(struct brw_wm_compile *c, int file, int index,
  32         int component, struct brw_reg reg)
  33 {
  34     c->wm_regs[file][index][component].reg = reg;
  35     c->wm_regs[file][index][component].inited = GL_TRUE;
  36 }
  37
  38 static int get_scalar_dst_index(struct prog_instruction *inst)
  39 {
  40     int i;
  41     for (i = 0; i < 4; i++)
  42         if (inst->DstReg.WriteMask & (1<<i))
  43             break;
  44     return i;
  45 }
  46
  47 static struct brw_reg alloc_tmp(struct brw_wm_compile *c)
  48 {
  49     struct brw_reg reg;
  50     if(c->tmp_index == c->tmp_max)
  51         c->tmp_regs[ c->tmp_max++ ] = c->reg_index++;
  52
  53     reg = brw_vec8_grf(c->tmp_regs[ c->tmp_index++ ], 0);
  54     return reg;
  55 }
  56
  57 static void release_tmps(struct brw_wm_compile *c)
  58 {
  59     c->tmp_index = 0;
  60 }
  61
  62 static struct brw_reg
  63 get_reg(struct brw_wm_compile *c, int file, int index, int component, int nr, GLuint neg, GLuint abs)
  64 {
  65     struct brw_reg reg;
  66     switch (file) {
  67         case PROGRAM_STATE_VAR:
  68         case PROGRAM_CONSTANT:
  69         case PROGRAM_UNIFORM:
  70             file = PROGRAM_STATE_VAR;
  71             break;
  72         case PROGRAM_UNDEFINED:
  73             return brw_null_reg();
  74         default:
  75             break;
  76     }
  77
  78     if(c->wm_regs[file][index][component].inited)
  79         reg = c->wm_regs[file][index][component].reg;
  80     else
  81         reg = brw_vec8_grf(c->reg_index, 0);
  82
  83     if(!c->wm_regs[file][index][component].inited) {
  84         set_reg(c, file, index, component, reg);
  85         c->reg_index++;
  86     }
  87
  88     if (neg & (1<< component)) {
  89         reg = negate(reg);
  90     }
  91     if (abs)
  92         reg = brw_abs(reg);
  93     return reg;
  94 }
  95
  96 static void prealloc_reg(struct brw_wm_compile *c)
  97 {
  98     int i, j;
  99     struct brw_reg reg;
 100     int nr_interp_regs = 0;
 101     GLuint inputs = FRAG_BIT_WPOS | c->fp_interp_emitted | c->fp_deriv_emitted;
 102
 103     for (i = 0; i < 4; i++) {
 104         reg = (i < c->key.nr_depth_regs)
 105             ? brw_vec8_grf(i*2, 0) : brw_vec8_grf(0, 0);
 106         set_reg(c, PROGRAM_PAYLOAD, PAYLOAD_DEPTH, i, reg);
 107     }
 108     c->reg_index += 2*c->key.nr_depth_regs;
 109     {
 110         int nr_params = c->fp->program.Base.Parameters->NumParameters;
 111         struct gl_program_parameter_list *plist =
 112             c->fp->program.Base.Parameters;
 113         int index = 0;
 114         c->prog_data.nr_params = 4*nr_params;
 115         for (i = 0; i < nr_params; i++) {
 116             for (j = 0; j < 4; j++, index++) {
 117                 reg = brw_vec1_grf(c->reg_index + index/8,
 118                         index%8);
 119                 c->prog_data.param[index] =
 120                     &plist->ParameterValues[i][j];
 121                 set_reg(c, PROGRAM_STATE_VAR, i, j, reg);
 122             }
 123         }
 124         c->nr_creg = 2*((4*nr_params+15)/16);
 125         c->reg_index += c->nr_creg;
 126     }
 127     for (i = 0; i < FRAG_ATTRIB_MAX; i++) {
 128         if (inputs & (1<<i)) {
 129             nr_interp_regs++;
 130             reg = brw_vec8_grf(c->reg_index, 0);
 131             for (j = 0; j < 4; j++)
 132                 set_reg(c, PROGRAM_PAYLOAD, i, j, reg);
 133             c->reg_index += 2;
 134
 135         }
 136     }
 137     c->prog_data.first_curbe_grf = c->key.nr_depth_regs * 2;
 138     c->prog_data.urb_read_length = nr_interp_regs * 2;
 139     c->prog_data.curb_read_length = c->nr_creg;
 140     c->emit_mask_reg = brw_uw1_reg(BRW_GENERAL_REGISTER_FILE, c->reg_index, 0);
 141     c->reg_index++;
 142     c->stack =  brw_uw16_reg(BRW_GENERAL_REGISTER_FILE, c->reg_index, 0);
 143     c->reg_index += 2;
 144 }
 145
 146 static struct brw_reg get_dst_reg(struct brw_wm_compile *c,
 147         struct prog_instruction *inst, int component, int nr)
 148 {
 149     return get_reg(c, inst->DstReg.File, inst->DstReg.Index, component, nr,
 150             0, 0);
 151 }
 152
 153 static struct brw_reg get_src_reg(struct brw_wm_compile *c,
 154         struct prog_src_register *src, int index, int nr)
 155 {
 156     int component = GET_SWZ(src->Swizzle, index);
 157     return get_reg(c, src->File, src->Index, component, nr,
 158             src->NegateBase, src->Abs);
 159 }
 160
 161 static void emit_abs( struct brw_wm_compile *c,
 162                 struct prog_instruction *inst)
 163 {
 164     int i;
 165     struct brw_compile *p = &c->func;
 166     brw_set_saturate(p, inst->SaturateMode != SATURATE_OFF);
 167     for (i = 0; i < 4; i++) {
 168         if (inst->DstReg.WriteMask & (1<<i)) {
 169             struct brw_reg src, dst;
 170             dst = get_dst_reg(c, inst, i, 1);
 171             src = get_src_reg(c, &inst->SrcReg[0], i, 1);
 172             brw_MOV(p, dst, brw_abs(src));
 173         }
 174     }
 175     brw_set_saturate(p, 0);
 176 }
 177
 178 static void emit_int( struct brw_wm_compile *c,
 179                 struct prog_instruction *inst)
 180 {
 181     int i;
 182     struct brw_compile *p = &c->func;
 183     GLuint mask = inst->DstReg.WriteMask;
 184     brw_set_saturate(p, inst->SaturateMode != SATURATE_OFF);
 185     for (i = 0; i < 4; i++) {
 186         if (mask & (1<<i)) {
 187             struct brw_reg src, dst;
 188             dst = get_dst_reg(c, inst, i, 1) ;
 189             src = get_src_reg(c, &inst->SrcReg[0], i, 1);
 190             brw_RNDD(p, dst, src);
 191         }
 192     }
 193     brw_set_saturate(p, 0);
 194 }
 195
 196 static void emit_mov( struct brw_wm_compile *c,
 197                 struct prog_instruction *inst)
 198 {
 199     int i;
 200     struct brw_compile *p = &c->func;
 201     GLuint mask = inst->DstReg.WriteMask;
 202     brw_set_saturate(p, inst->SaturateMode != SATURATE_OFF);
 203     for (i = 0; i < 4; i++) {
 204         if (mask & (1<<i)) {
 205             struct brw_reg src, dst;
 206             dst = get_dst_reg(c, inst, i, 1);
 207             src = get_src_reg(c, &inst->SrcReg[0], i, 1);
 208             brw_MOV(p, dst, src);
 209         }
 210     }
 211     brw_set_saturate(p, 0);
 212 }
 213
 214 static void emit_pixel_xy(struct brw_wm_compile *c,
 215                 struct prog_instruction *inst)
 216 {
 217     struct brw_reg r1 = brw_vec1_grf(1, 0);
 218     struct brw_reg r1_uw = retype(r1, BRW_REGISTER_TYPE_UW);
 219
 220     struct brw_reg dst0, dst1;
 221     struct brw_compile *p = &c->func;
 222     GLuint mask = inst->DstReg.WriteMask;
 223
 224     dst0 = get_dst_reg(c, inst, 0, 1);
 225     dst1 = get_dst_reg(c, inst, 1, 1);
 226     /* Calculate pixel centers by adding 1 or 0 to each of the
 227      * micro-tile coordinates passed in r1.
 228      */
 229     if (mask & WRITEMASK_X) {
 230         brw_ADD(p,
 231                 vec8(retype(dst0, BRW_REGISTER_TYPE_UW)),
 232                 stride(suboffset(r1_uw, 4), 2, 4, 0),
 233                 brw_imm_v(0x10101010));
 234     }
 235
 236     if (mask & WRITEMASK_Y) {
 237         brw_ADD(p,
 238                 vec8(retype(dst1, BRW_REGISTER_TYPE_UW)),
 239                 stride(suboffset(r1_uw, 5), 2, 4, 0),
 240                 brw_imm_v(0x11001100));
 241     }
 242
 243 }
 244
 245 static void emit_delta_xy(struct brw_wm_compile *c,
 246                 struct prog_instruction *inst)
 247 {
 248     struct brw_reg r1 = brw_vec1_grf(1, 0);
 249     struct brw_reg dst0, dst1, src0, src1;
 250     struct brw_compile *p = &c->func;
 251     GLuint mask = inst->DstReg.WriteMask;
 252
 253     dst0 = get_dst_reg(c, inst, 0, 1);
 254     dst1 = get_dst_reg(c, inst, 1, 1);
 255     src0 = get_src_reg(c, &inst->SrcReg[0], 0, 1);
 256     src1 = get_src_reg(c, &inst->SrcReg[0], 1, 1);
 257     /* Calc delta X,Y by subtracting origin in r1 from the pixel
 258      * centers.
 259      */
 260     if (mask & WRITEMASK_X) {
 261         brw_ADD(p,
 262                 dst0,
 263                 retype(src0, BRW_REGISTER_TYPE_UW),
 264                 negate(r1));
 265     }
 266
 267     if (mask & WRITEMASK_Y) {
 268         brw_ADD(p,
 269                 dst1,
 270                 retype(src1, BRW_REGISTER_TYPE_UW),
 271                 negate(suboffset(r1,1)));
 272
 273     }
 274
 275 }
 276
 277
 278 static void fire_fb_write( struct brw_wm_compile *c,
 279                            GLuint base_reg,
 280                            GLuint nr,
 281                            GLuint target,
 282                            GLuint eot)
 283 {
 284     struct brw_compile *p = &c->func;
 285     /* Pass through control information:
 286      */
 287     /*  mov (8) m1.0<1>:ud   r1.0<8;8,1>:ud   { Align1 NoMask } */
 288     {
 289         brw_push_insn_state(p);
 290         brw_set_mask_control(p, BRW_MASK_DISABLE); /* ? */
 291         brw_MOV(p,
 292                 brw_message_reg(base_reg + 1),
 293                 brw_vec8_grf(1, 0));
 294         brw_pop_insn_state(p);
 295     }
 296     /* Send framebuffer write message: */
 297     brw_fb_WRITE(p,
 298             retype(vec8(brw_null_reg()), BRW_REGISTER_TYPE_UW),
 299             base_reg,
 300             retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW),
 301             target,
 302             nr,
 303             0,
 304             eot);
 305 }
 306
 307 static void emit_fb_write(struct brw_wm_compile *c,
 308                 struct prog_instruction *inst)
 309 {
 310     struct brw_compile *p = &c->func;
 311     int nr = 2;
 312     int channel;
 313     GLuint target, eot;
 314     struct brw_reg src0;
 315
 316     /* Reserve a space for AA - may not be needed:
 317      */
 318     if (c->key.aa_dest_stencil_reg)
 319         nr += 1;
 320     {
 321         brw_push_insn_state(p);
 322         for (channel = 0; channel < 4; channel++) {
 323             src0 = get_src_reg(c,  &inst->SrcReg[0], channel, 1);
 324             /*  mov (8) m2.0<1>:ud   r28.0<8;8,1>:ud  { Align1 } */
 325             /*  mov (8) m6.0<1>:ud   r29.0<8;8,1>:ud  { Align1 SecHalf } */
 326             brw_MOV(p, brw_message_reg(nr + channel), src0);
 327         }
 328         /* skip over the regs populated above: */
 329         nr += 8;
 330         brw_pop_insn_state(p);
 331     }
 332
 333    if (c->key.source_depth_to_render_target)
 334    {
 335       if (c->key.computes_depth) {
 336          src0 = get_src_reg(c, &inst->SrcReg[2], 2, 1);
 337          brw_MOV(p, brw_message_reg(nr), src0);
 338       } else {
 339          src0 = get_src_reg(c, &inst->SrcReg[1], 1, 1);
 340          brw_MOV(p, brw_message_reg(nr), src0);
 341       }
 342
 343       nr += 2;
 344    }
 345     target = inst->Sampler >> 1;
 346     eot = inst->Sampler & 1;
 347     fire_fb_write(c, 0, nr, target, eot);
 348 }
 349
 350 static void emit_pixel_w( struct brw_wm_compile *c,
 351                 struct prog_instruction *inst)
 352 {
 353     struct brw_compile *p = &c->func;
 354     GLuint mask = inst->DstReg.WriteMask;
 355     if (mask & WRITEMASK_W) {
 356         struct brw_reg dst, src0, delta0, delta1;
 357         struct brw_reg interp3;
 358
 359         dst = get_dst_reg(c, inst, 3, 1);
 360         src0 = get_src_reg(c, &inst->SrcReg[0], 0, 1);
 361         delta0 = get_src_reg(c, &inst->SrcReg[1], 0, 1);
 362         delta1 = get_src_reg(c, &inst->SrcReg[1], 1, 1);
 363
 364         interp3 = brw_vec1_grf(src0.nr+1, 4);
 365         /* Calc 1/w - just linterp wpos[3] optimized by putting the
 366          * result straight into a message reg.
 367          */
 368         brw_LINE(p, brw_null_reg(), interp3, delta0);
 369         brw_MAC(p, brw_message_reg(2), suboffset(interp3, 1), delta1);
 370
 371         /* Calc w */
 372         brw_math_16( p, dst,
 373                 BRW_MATH_FUNCTION_INV,
 374                 BRW_MATH_SATURATE_NONE,
 375                 2, brw_null_reg(),
 376                 BRW_MATH_PRECISION_FULL);
 377     }
 378 }
 379
 380 static void emit_linterp(struct brw_wm_compile *c,
 381                 struct prog_instruction *inst)
 382 {
 383     struct brw_compile *p = &c->func;
 384     GLuint mask = inst->DstReg.WriteMask;
 385     struct brw_reg interp[4];
 386     struct brw_reg dst, delta0, delta1;
 387     struct brw_reg src0;
 388
 389     src0 = get_src_reg(c, &inst->SrcReg[0], 0, 1);
 390     delta0 = get_src_reg(c, &inst->SrcReg[1], 0, 1);
 391     delta1 = get_src_reg(c, &inst->SrcReg[1], 1, 1);
 392     GLuint nr = src0.nr;
 393     int i;
 394
 395     interp[0] = brw_vec1_grf(nr, 0);
 396     interp[1] = brw_vec1_grf(nr, 4);
 397     interp[2] = brw_vec1_grf(nr+1, 0);
 398     interp[3] = brw_vec1_grf(nr+1, 4);
 399
 400     for(i = 0; i < 4; i++ ) {
 401         if (mask & (1<<i)) {
 402             dst = get_dst_reg(c, inst, i, 1);
 403             brw_LINE(p, brw_null_reg(), interp[i], delta0);
 404             brw_MAC(p, dst, suboffset(interp[i],1), delta1);
 405         }
 406     }
 407 }
 408
 409 static void emit_cinterp(struct brw_wm_compile *c,
 410                 struct prog_instruction *inst)
 411 {
 412     struct brw_compile *p = &c->func;
 413     GLuint mask = inst->DstReg.WriteMask;
 414
 415     struct brw_reg interp[4];
 416     struct brw_reg dst, src0;
 417
 418     src0 = get_src_reg(c, &inst->SrcReg[0], 0, 1);
 419     GLuint nr = src0.nr;
 420     int i;
 421
 422     interp[0] = brw_vec1_grf(nr, 0);
 423     interp[1] = brw_vec1_grf(nr, 4);
 424     interp[2] = brw_vec1_grf(nr+1, 0);
 425     interp[3] = brw_vec1_grf(nr+1, 4);
 426
 427     for(i = 0; i < 4; i++ ) {
 428         if (mask & (1<<i)) {
 429             dst = get_dst_reg(c, inst, i, 1);
 430             brw_MOV(p, dst, suboffset(interp[i],3));
 431         }
 432     }
 433 }
 434
 435 static void emit_pinterp(struct brw_wm_compile *c,
 436                 struct prog_instruction *inst)
 437 {
 438     struct brw_compile *p = &c->func;
 439     GLuint mask = inst->DstReg.WriteMask;
 440
 441     struct brw_reg interp[4];
 442     struct brw_reg dst, delta0, delta1;
 443     struct brw_reg src0, w;
 444
 445     src0 = get_src_reg(c, &inst->SrcReg[0], 0, 1);
 446     delta0 = get_src_reg(c, &inst->SrcReg[1], 0, 1);
 447     delta1 = get_src_reg(c, &inst->SrcReg[1], 1, 1);
 448     w = get_src_reg(c, &inst->SrcReg[2], 3, 1);
 449     GLuint nr = src0.nr;
 450     int i;
 451
 452     interp[0] = brw_vec1_grf(nr, 0);
 453     interp[1] = brw_vec1_grf(nr, 4);
 454     interp[2] = brw_vec1_grf(nr+1, 0);
 455     interp[3] = brw_vec1_grf(nr+1, 4);
 456
 457     for(i = 0; i < 4; i++ ) {
 458         if (mask & (1<<i)) {
 459             dst = get_dst_reg(c, inst, i, 1);
 460             brw_LINE(p, brw_null_reg(), interp[i], delta0);
 461             brw_MAC(p, dst, suboffset(interp[i],1),
 462                     delta1);
 463             brw_MUL(p, dst, dst, w);
 464         }
 465     }
 466 }
 467
 468 static void emit_xpd(struct brw_wm_compile *c,
 469                 struct prog_instruction *inst)
 470 {
 471     int i;
 472     struct brw_compile *p = &c->func;
 473     GLuint mask = inst->DstReg.WriteMask;
 474     for (i = 0; i < 4; i++) {
 475         GLuint i2 = (i+2)%3;
 476         GLuint i1 = (i+1)%3;
 477         if (mask & (1<<i)) {
 478             struct brw_reg src0, src1, dst;
 479             dst = get_dst_reg(c, inst, i, 1);
 480             src0 = negate(get_src_reg(c, &inst->SrcReg[0], i2, 1));
 481             src1 = get_src_reg(c, &inst->SrcReg[1], i1, 1);
 482             brw_MUL(p, brw_null_reg(), src0, src1);
 483             src0 = get_src_reg(c, &inst->SrcReg[0], i1, 1);
 484             src1 = get_src_reg(c, &inst->SrcReg[1], i2, 1);
 485             brw_set_saturate(p, inst->SaturateMode != SATURATE_OFF);
 486             brw_MAC(p, dst, src0, src1);
 487             brw_set_saturate(p, 0);
 488         }
 489     }
 490     brw_set_saturate(p, 0);
 491 }
 492
 493 static void emit_dp3(struct brw_wm_compile *c,
 494                 struct prog_instruction *inst)
 495 {
 496     struct brw_reg src0[3], src1[3], dst;
 497     int i;
 498     struct brw_compile *p = &c->func;
 499     for (i = 0; i < 3; i++) {
 500         src0[i] = get_src_reg(c, &inst->SrcReg[0], i, 1);
 501         src1[i] = get_src_reg(c, &inst->SrcReg[1], i, 1);
 502     }
 503
 504     dst = get_dst_reg(c, inst, get_scalar_dst_index(inst), 1);
 505     brw_MUL(p, brw_null_reg(), src0[0], src1[0]);
 506     brw_MAC(p, brw_null_reg(), src0[1], src1[1]);
 507     brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0);
 508     brw_MAC(p, dst, src0[2], src1[2]);
 509     brw_set_saturate(p, 0);
 510 }
 511
 512 static void emit_dp4(struct brw_wm_compile *c,
 513                 struct prog_instruction *inst)
 514 {
 515     struct brw_reg src0[4], src1[4], dst;
 516     int i;
 517     struct brw_compile *p = &c->func;
 518     for (i = 0; i < 4; i++) {
 519         src0[i] = get_src_reg(c, &inst->SrcReg[0], i, 1);
 520         src1[i] = get_src_reg(c, &inst->SrcReg[1], i, 1);
 521     }
 522     dst = get_dst_reg(c, inst, get_scalar_dst_index(inst), 1);
 523     brw_MUL(p, brw_null_reg(), src0[0], src1[0]);
 524     brw_MAC(p, brw_null_reg(), src0[1], src1[1]);
 525     brw_MAC(p, brw_null_reg(), src0[2], src1[2]);
 526     brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0);
 527     brw_MAC(p, dst, src0[3], src1[3]);
 528     brw_set_saturate(p, 0);
 529 }
 530
 531 static void emit_dph(struct brw_wm_compile *c,
 532                 struct prog_instruction *inst)
 533 {
 534     struct brw_reg src0[4], src1[4], dst;
 535     int i;
 536     struct brw_compile *p = &c->func;
 537     for (i = 0; i < 4; i++) {
 538         src0[i] = get_src_reg(c, &inst->SrcReg[0], i, 1);
 539         src1[i] = get_src_reg(c, &inst->SrcReg[1], i, 1);
 540     }
 541     dst = get_dst_reg(c, inst, get_scalar_dst_index(inst), 1);
 542     brw_MUL(p, brw_null_reg(), src0[0], src1[0]);
 543     brw_MAC(p, brw_null_reg(), src0[1], src1[1]);
 544     brw_MAC(p, dst, src0[2], src1[2]);
 545     brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0);
 546     brw_ADD(p, dst, src0[3], src1[3]);
 547     brw_set_saturate(p, 0);
 548 }
 549
 550 static void emit_math1(struct brw_wm_compile *c,
 551                 struct prog_instruction *inst, GLuint func)
 552 {
 553     struct brw_compile *p = &c->func;
 554     struct brw_reg src0, dst;
 555
 556     src0 = get_src_reg(c, &inst->SrcReg[0], 0, 1);
 557     dst = get_dst_reg(c, inst, get_scalar_dst_index(inst), 1);
 558     brw_MOV(p, brw_message_reg(2), src0);
 559     brw_math(p,
 560             dst,
 561             func,
 562             (inst->SaturateMode != SATURATE_OFF) ? BRW_MATH_SATURATE_SATURATE : BRW_MATH_SATURATE_NONE,
 563             2,
 564             brw_null_reg(),
 565             BRW_MATH_DATA_VECTOR,
 566             BRW_MATH_PRECISION_FULL);
 567 }
 568
 569 static void emit_rcp(struct brw_wm_compile *c,
 570                 struct prog_instruction *inst)
 571 {
 572     emit_math1(c, inst, BRW_MATH_FUNCTION_INV);
 573 }
 574
 575 static void emit_rsq(struct brw_wm_compile *c,
 576                 struct prog_instruction *inst)
 577 {
 578     emit_math1(c, inst, BRW_MATH_FUNCTION_RSQ);
 579 }
 580
 581 static void emit_sin(struct brw_wm_compile *c,
 582                 struct prog_instruction *inst)
 583 {
 584     emit_math1(c, inst, BRW_MATH_FUNCTION_SIN);
 585 }
 586
 587 static void emit_cos(struct brw_wm_compile *c,
 588                 struct prog_instruction *inst)
 589 {
 590     emit_math1(c, inst, BRW_MATH_FUNCTION_COS);
 591 }
 592
 593 static void emit_ex2(struct brw_wm_compile *c,
 594                 struct prog_instruction *inst)
 595 {
 596     emit_math1(c, inst, BRW_MATH_FUNCTION_EXP);
 597 }
 598
 599 static void emit_lg2(struct brw_wm_compile *c,
 600                 struct prog_instruction *inst)
 601 {
 602     emit_math1(c, inst, BRW_MATH_FUNCTION_LOG);
 603 }
 604
 605 static void emit_add(struct brw_wm_compile *c,
 606                 struct prog_instruction *inst)
 607 {
 608     struct brw_compile *p = &c->func;
 609     struct brw_reg src0, src1, dst;
 610     GLuint mask = inst->DstReg.WriteMask;
 611     int i;
 612     brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0);
 613     for (i = 0 ; i < 4; i++) {
 614         if (mask & (1<<i)) {
 615             dst = get_dst_reg(c, inst, i, 1);
 616             src0 = get_src_reg(c, &inst->SrcReg[0], i, 1);
 617             src1 = get_src_reg(c, &inst->SrcReg[1], i, 1);
 618             brw_ADD(p, dst, src0, src1);
 619         }
 620     }
 621     brw_set_saturate(p, 0);
 622 }
 623
 624 static void emit_sub(struct brw_wm_compile *c,
 625                 struct prog_instruction *inst)
 626 {
 627     struct brw_compile *p = &c->func;
 628     struct brw_reg src0, src1, dst;
 629     GLuint mask = inst->DstReg.WriteMask;
 630     int i;
 631     brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0);
 632     for (i = 0 ; i < 4; i++) {
 633         if (mask & (1<<i)) {
 634             dst = get_dst_reg(c, inst, i, 1);
 635             src0 = get_src_reg(c, &inst->SrcReg[0], i, 1);
 636             src1 = get_src_reg(c, &inst->SrcReg[1], i, 1);
 637             brw_ADD(p, dst, src0, negate(src1));
 638         }
 639     }
 640     brw_set_saturate(p, 0);
 641 }
 642
 643 static void emit_mul(struct brw_wm_compile *c,
 644                 struct prog_instruction *inst)
 645 {
 646     struct brw_compile *p = &c->func;
 647     struct brw_reg src0, src1, dst;
 648     GLuint mask = inst->DstReg.WriteMask;
 649     int i;
 650     brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0);
 651     for (i = 0 ; i < 4; i++) {
 652         if (mask & (1<<i)) {
 653             dst = get_dst_reg(c, inst, i, 1);
 654             src0 = get_src_reg(c, &inst->SrcReg[0], i, 1);
 655             src1 = get_src_reg(c, &inst->SrcReg[1], i, 1);
 656             brw_MUL(p, dst, src0, src1);
 657         }
 658     }
 659     brw_set_saturate(p, 0);
 660 }
 661
 662 static void emit_frc(struct brw_wm_compile *c,
 663                 struct prog_instruction *inst)
 664 {
 665     struct brw_compile *p = &c->func;
 666     struct brw_reg src0, dst;
 667     GLuint mask = inst->DstReg.WriteMask;
 668     int i;
 669     brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0);
 670     for (i = 0 ; i < 4; i++) {
 671         if (mask & (1<<i)) {
 672             dst = get_dst_reg(c, inst, i, 1);
 673             src0 = get_src_reg(c, &inst->SrcReg[0], i, 1);
 674             brw_FRC(p, dst, src0);
 675         }
 676     }
 677     if (inst->SaturateMode != SATURATE_OFF)
 678         brw_set_saturate(p, 0);
 679 }
 680
 681 static void emit_flr(struct brw_wm_compile *c,
 682                 struct prog_instruction *inst)
 683 {
 684     struct brw_compile *p = &c->func;
 685     struct brw_reg src0, dst;
 686     GLuint mask = inst->DstReg.WriteMask;
 687     int i;
 688     brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0);
 689     for (i = 0 ; i < 4; i++) {
 690         if (mask & (1<<i)) {
 691             dst = get_dst_reg(c, inst, i, 1);
 692             src0 = get_src_reg(c, &inst->SrcReg[0], i, 1);
 693             brw_RNDD(p, dst, src0);
 694         }
 695     }
 696     brw_set_saturate(p, 0);
 697 }
 698
 699 static void emit_max(struct brw_wm_compile *c,
 700                 struct prog_instruction *inst)
 701 {
 702     struct brw_compile *p = &c->func;
 703     GLuint mask = inst->DstReg.WriteMask;
 704     struct brw_reg src0, src1, dst;
 705     int i;
 706     brw_push_insn_state(p);
 707     for (i = 0; i < 4; i++) {
 708         if (mask & (1<<i)) {
 709             dst = get_dst_reg(c, inst, i, 1);
 710             src0 = get_src_reg(c, &inst->SrcReg[0], i, 1);
 711             src1 = get_src_reg(c, &inst->SrcReg[1], i, 1);
 712             brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0);
 713             brw_MOV(p, dst, src0);
 714             brw_set_saturate(p, 0);
 715
 716             brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_L, src0, src1);
 717             brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0);
 718             brw_set_predicate_control(p, BRW_PREDICATE_NORMAL);
 719             brw_MOV(p, dst, src1);
 720             brw_set_saturate(p, 0);
 721             brw_set_predicate_control_flag_value(p, 0xff);
 722         }
 723     }
 724     brw_pop_insn_state(p);
 725 }
 726
 727 static void emit_min(struct brw_wm_compile *c,
 728                 struct prog_instruction *inst)
 729 {
 730     struct brw_compile *p = &c->func;
 731     GLuint mask = inst->DstReg.WriteMask;
 732     struct brw_reg src0, src1, dst;
 733     int i;
 734     brw_push_insn_state(p);
 735     for (i = 0; i < 4; i++) {
 736         if (mask & (1<<i)) {
 737             dst = get_dst_reg(c, inst, i, 1);
 738             src0 = get_src_reg(c, &inst->SrcReg[0], i, 1);
 739             src1 = get_src_reg(c, &inst->SrcReg[1], i, 1);
 740             brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0);
 741             brw_MOV(p, dst, src0);
 742             brw_set_saturate(p, 0);
 743
 744             brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_L, src1, src0);
 745             brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0);
 746             brw_set_predicate_control(p, BRW_PREDICATE_NORMAL);
 747             brw_MOV(p, dst, src1);
 748             brw_set_saturate(p, 0);
 749             brw_set_predicate_control_flag_value(p, 0xff);
 750         }
 751     }
 752     brw_pop_insn_state(p);
 753 }
 754
 755 static void emit_pow(struct brw_wm_compile *c,
 756                 struct prog_instruction *inst)
 757 {
 758     struct brw_compile *p = &c->func;
 759     struct brw_reg dst, src0, src1;
 760     dst = get_dst_reg(c, inst, get_scalar_dst_index(inst), 1);
 761     src0 = get_src_reg(c, &inst->SrcReg[0], 0, 1);
 762     src1 = get_src_reg(c, &inst->SrcReg[1], 0, 1);
 763
 764     brw_MOV(p, brw_message_reg(2), src0);
 765     brw_MOV(p, brw_message_reg(3), src1);
 766
 767     brw_math(p,
 768             dst,
 769             BRW_MATH_FUNCTION_POW,
 770             (inst->SaturateMode != SATURATE_OFF) ? BRW_MATH_SATURATE_SATURATE : BRW_MATH_SATURATE_NONE,
 771             2,
 772             brw_null_reg(),
 773             BRW_MATH_DATA_VECTOR,
 774             BRW_MATH_PRECISION_FULL);
 775 }
 776
 777 static void emit_lrp(struct brw_wm_compile *c,
 778                 struct prog_instruction *inst)
 779 {
 780     struct brw_compile *p = &c->func;
 781     GLuint mask = inst->DstReg.WriteMask;
 782     struct brw_reg dst, tmp1, tmp2, src0, src1, src2;
 783     int i;
 784     for (i = 0; i < 4; i++) {
 785         if (mask & (1<<i)) {
 786             dst = get_dst_reg(c, inst, i, 1);
 787             src0 = get_src_reg(c, &inst->SrcReg[0], i, 1);
 788
 789             src1 = get_src_reg(c, &inst->SrcReg[1], i, 1);
 790
 791             if (src1.nr == dst.nr) {
 792                 tmp1 = alloc_tmp(c);
 793                 brw_MOV(p, tmp1, src1);
 794             } else
 795                 tmp1 = src1;
 796
 797             src2 = get_src_reg(c, &inst->SrcReg[2], i, 1);
 798             if (src2.nr == dst.nr) {
 799                 tmp2 = alloc_tmp(c);
 800                 brw_MOV(p, tmp2, src2);
 801             } else
 802                 tmp2 = src2;
 803
 804             brw_ADD(p, dst, negate(src0), brw_imm_f(1.0));
 805             brw_MUL(p, brw_null_reg(), dst, tmp2);
 806             brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0);
 807             brw_MAC(p, dst, src0, tmp1);
 808             brw_set_saturate(p, 0);
 809         }
 810         release_tmps(c);
 811     }
 812 }
 813
 814 static void emit_kil(struct brw_wm_compile *c)
 815 {
 816         struct brw_compile *p = &c->func;
 817         struct brw_reg depth = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
 818         brw_push_insn_state(p);
 819         brw_set_mask_control(p, BRW_MASK_DISABLE);
 820         brw_NOT(p, c->emit_mask_reg, brw_mask_reg(1)); //IMASK
 821         brw_AND(p, depth, c->emit_mask_reg, depth);
 822         brw_pop_insn_state(p);
 823 }
 824
 825 static void emit_mad(struct brw_wm_compile *c,
 826                 struct prog_instruction *inst)
 827 {
 828     struct brw_compile *p = &c->func;
 829     GLuint mask = inst->DstReg.WriteMask;
 830     struct brw_reg dst, src0, src1, src2;
 831     int i;
 832
 833     for (i = 0; i < 4; i++) {
 834         if (mask & (1<<i)) {
 835             dst = get_dst_reg(c, inst, i, 1);
 836             src0 = get_src_reg(c, &inst->SrcReg[0], i, 1);
 837             src1 = get_src_reg(c, &inst->SrcReg[1], i, 1);
 838             src2 = get_src_reg(c, &inst->SrcReg[2], i, 1);
 839             brw_MUL(p, dst, src0, src1);
 840
 841             brw_set_saturate(p, (inst->SaturateMode != SATURATE_OFF) ? 1 : 0);
 842             brw_ADD(p, dst, dst, src2);
 843             brw_set_saturate(p, 0);
 844         }
 845     }
 846 }
 847
 848 static void emit_sop(struct brw_wm_compile *c,
 849                 struct prog_instruction *inst, GLuint cond)
 850 {
 851     struct brw_compile *p = &c->func;
 852     GLuint mask = inst->DstReg.WriteMask;
 853     struct brw_reg dst, src0, src1;
 854     int i;
 855
 856     for (i = 0; i < 4; i++) {
 857         if (mask & (1<<i)) {
 858             dst = get_dst_reg(c, inst, i, 1);
 859             src0 = get_src_reg(c, &inst->SrcReg[0], i, 1);
 860             src1 = get_src_reg(c, &inst->SrcReg[1], i, 1);
 861             brw_push_insn_state(p);
 862             brw_CMP(p, brw_null_reg(), cond, src0, src1);
 863             brw_set_predicate_control(p, BRW_PREDICATE_NONE);
 864             brw_MOV(p, dst, brw_imm_f(0.0));
 865             brw_set_predicate_control(p, BRW_PREDICATE_NORMAL);
 866             brw_MOV(p, dst, brw_imm_f(1.0));
 867             brw_pop_insn_state(p);
 868         }
 869     }
 870 }
 871
 872 static void emit_slt(struct brw_wm_compile *c,
 873                 struct prog_instruction *inst)
 874 {
 875     emit_sop(c, inst, BRW_CONDITIONAL_L);
 876 }
 877
 878 static void emit_sle(struct brw_wm_compile *c,
 879                 struct prog_instruction *inst)
 880 {
 881     emit_sop(c, inst, BRW_CONDITIONAL_LE);
 882 }
 883
 884 static void emit_sgt(struct brw_wm_compile *c,
 885                 struct prog_instruction *inst)
 886 {
 887     emit_sop(c, inst, BRW_CONDITIONAL_G);
 888 }
 889
 890 static void emit_sge(struct brw_wm_compile *c,
 891                 struct prog_instruction *inst)
 892 {
 893     emit_sop(c, inst, BRW_CONDITIONAL_GE);
 894 }
 895
 896 static void emit_seq(struct brw_wm_compile *c,
 897                 struct prog_instruction *inst)
 898 {
 899     emit_sop(c, inst, BRW_CONDITIONAL_EQ);
 900 }
 901
 902 static void emit_sne(struct brw_wm_compile *c,
 903                 struct prog_instruction *inst)
 904 {
 905     emit_sop(c, inst, BRW_CONDITIONAL_NEQ);
 906 }
 907
 908 static void emit_ddx(struct brw_wm_compile *c,
 909                 struct prog_instruction *inst)
 910 {
 911     struct brw_compile *p = &c->func;
 912     GLuint mask = inst->DstReg.WriteMask;
 913     struct brw_reg interp[4];
 914     struct brw_reg dst;
 915     struct brw_reg src0, w;
 916     GLuint nr, i;
 917     src0 = get_src_reg(c, &inst->SrcReg[0], 0, 1);
 918     w = get_src_reg(c, &inst->SrcReg[1], 3, 1);
 919     nr = src0.nr;
 920     interp[0] = brw_vec1_grf(nr, 0);
 921     interp[1] = brw_vec1_grf(nr, 4);
 922     interp[2] = brw_vec1_grf(nr+1, 0);
 923     interp[3] = brw_vec1_grf(nr+1, 4);
 924     brw_set_saturate(p, inst->SaturateMode != SATURATE_OFF);
 925     for(i = 0; i < 4; i++ ) {
 926         if (mask & (1<<i)) {
 927             dst = get_dst_reg(c, inst, i, 1);
 928             brw_MOV(p, dst, interp[i]);
 929             brw_MUL(p, dst, dst, w);
 930         }
 931     }
 932     brw_set_saturate(p, 0);
 933 }
 934
 935 static void emit_ddy(struct brw_wm_compile *c,
 936                 struct prog_instruction *inst)
 937 {
 938     struct brw_compile *p = &c->func;
 939     GLuint mask = inst->DstReg.WriteMask;
 940     struct brw_reg interp[4];
 941     struct brw_reg dst;
 942     struct brw_reg src0, w;
 943     GLuint nr, i;
 944
 945     src0 = get_src_reg(c, &inst->SrcReg[0], 0, 1);
 946     nr = src0.nr;
 947     w = get_src_reg(c, &inst->SrcReg[1], 3, 1);
 948     interp[0] = brw_vec1_grf(nr, 0);
 949     interp[1] = brw_vec1_grf(nr, 4);
 950     interp[2] = brw_vec1_grf(nr+1, 0);
 951     interp[3] = brw_vec1_grf(nr+1, 4);
 952     brw_set_saturate(p, inst->SaturateMode != SATURATE_OFF);
 953     for(i = 0; i < 4; i++ ) {
 954         if (mask & (1<<i)) {
 955             dst = get_dst_reg(c, inst, i, 1);
 956             brw_MOV(p, dst, suboffset(interp[i], 1));
 957             brw_MUL(p, dst, dst, w);
 958         }
 959     }
 960     brw_set_saturate(p, 0);
 961 }
 962
 963 static void emit_wpos_xy(struct brw_wm_compile *c,
 964                 struct prog_instruction *inst)
 965 {
 966     struct brw_compile *p = &c->func;
 967     GLuint mask = inst->DstReg.WriteMask;
 968     struct brw_reg src0[2], dst[2];
 969
 970     dst[0] = get_dst_reg(c, inst, 0, 1);
 971     dst[1] = get_dst_reg(c, inst, 1, 1);
 972
 973     src0[0] = get_src_reg(c, &inst->SrcReg[0], 0, 1);
 974     src0[1] = get_src_reg(c, &inst->SrcReg[0], 1, 1);
 975
 976     /* Calculate the pixel offset from window bottom left into destination
 977      * X and Y channels.
 978      */
 979     if (mask & WRITEMASK_X) {
 980         /* X' = X - origin_x */
 981         brw_ADD(p,
 982                 dst[0],
 983                 retype(src0[0], BRW_REGISTER_TYPE_W),
 984                 brw_imm_d(0 - c->key.origin_x));
 985     }
 986
 987     if (mask & WRITEMASK_Y) {
 988         /* Y' = height - (Y - origin_y) = height + origin_y - Y */
 989         brw_ADD(p,
 990                 dst[1],
 991                 negate(retype(src0[1], BRW_REGISTER_TYPE_W)),
 992                 brw_imm_d(c->key.origin_y + c->key.drawable_height - 1));
 993     }
 994 }
 995
 996 /* TODO
 997    BIAS on SIMD8 not workind yet...
 998  */
 999 static void emit_txb(struct brw_wm_compile *c,
1000                 struct prog_instruction *inst)
1001 {
1002     struct brw_compile *p = &c->func;
1003     struct brw_reg dst[4], src[4], payload_reg;
1004     GLuint unit = c->fp->program.Base.SamplerUnits[inst->TexSrcUnit];
1005
1006     GLuint i;
1007     payload_reg = get_reg(c, PROGRAM_PAYLOAD, PAYLOAD_DEPTH, 0, 1, 0, 0);
1008     for (i = 0; i < 4; i++)
1009         dst[i] = get_dst_reg(c, inst, i, 1);
1010     for (i = 0; i < 4; i++)
1011         src[i] = get_src_reg(c, &inst->SrcReg[0], i, 1);
1012
1013     switch (inst->TexSrcTarget) {
1014         case TEXTURE_1D_INDEX:
1015             brw_MOV(p, brw_message_reg(2), src[0]);
1016             brw_MOV(p, brw_message_reg(3), brw_imm_f(0));
1017             brw_MOV(p, brw_message_reg(4), brw_imm_f(0));
1018             break;
1019         case TEXTURE_2D_INDEX:
1020         case TEXTURE_RECT_INDEX:
1021             brw_MOV(p, brw_message_reg(2), src[0]);
1022             brw_MOV(p, brw_message_reg(3), src[1]);
1023             brw_MOV(p, brw_message_reg(4), brw_imm_f(0));
1024             break;
1025         default:
1026             brw_MOV(p, brw_message_reg(2), src[0]);
1027             brw_MOV(p, brw_message_reg(3), src[1]);
1028             brw_MOV(p, brw_message_reg(4), src[2]);
1029             break;
1030     }
1031     brw_MOV(p, brw_message_reg(5), src[3]);
1032     brw_MOV(p, brw_message_reg(6), brw_imm_f(0));
1033     brw_SAMPLE(p,
1034             retype(vec8(dst[0]), BRW_REGISTER_TYPE_UW),
1035             1,
1036             retype(payload_reg, BRW_REGISTER_TYPE_UW),
1037             unit + MAX_DRAW_BUFFERS, /* surface */
1038             unit,     /* sampler */
1039             inst->DstReg.WriteMask,
1040             BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS,
1041             4,
1042             4,
1043             0);
1044 }
1045
1046 static void emit_tex(struct brw_wm_compile *c,
1047                 struct prog_instruction *inst)
1048 {
1049     struct brw_compile *p = &c->func;
1050     struct brw_reg dst[4], src[4], payload_reg;
1051     GLuint unit = c->fp->program.Base.SamplerUnits[inst->TexSrcUnit];
1052
1053     GLuint msg_len;
1054     GLuint i, nr;
1055     GLuint emit;
1056     GLboolean shadow = (c->key.shadowtex_mask & (1<<unit)) ? 1 : 0;
1057
1058     payload_reg = get_reg(c, PROGRAM_PAYLOAD, PAYLOAD_DEPTH, 0, 1, 0, 0);
1059
1060     for (i = 0; i < 4; i++)
1061         dst[i] = get_dst_reg(c, inst, i, 1);
1062     for (i = 0; i < 4; i++)
1063         src[i] = get_src_reg(c, &inst->SrcReg[0], i, 1);
1064
1065
1066     switch (inst->TexSrcTarget) {
1067         case TEXTURE_1D_INDEX:
1068             emit = WRITEMASK_X;
1069             nr = 1;
1070             break;
1071         case TEXTURE_2D_INDEX:
1072         case TEXTURE_RECT_INDEX:
1073             emit = WRITEMASK_XY;
1074             nr = 2;
1075             break;
1076         default:
1077             emit = WRITEMASK_XYZ;
1078             nr = 3;
1079             break;
1080     }
1081     msg_len = 1;
1082
1083     for (i = 0; i < nr; i++) {
1084         static const GLuint swz[4] = {0,1,2,2};
1085         if (emit & (1<<i))
1086             brw_MOV(p, brw_message_reg(msg_len+1), src[swz[i]]);
1087         else
1088             brw_MOV(p, brw_message_reg(msg_len+1), brw_imm_f(0));
1089         msg_len += 1;
1090     }
1091
1092     if (shadow) {
1093         brw_MOV(p, brw_message_reg(5), brw_imm_f(0));
1094         brw_MOV(p, brw_message_reg(6), src[2]);
1095     }
1096
1097     brw_SAMPLE(p,
1098             retype(vec8(dst[0]), BRW_REGISTER_TYPE_UW),
1099             1,
1100             retype(payload_reg, BRW_REGISTER_TYPE_UW),
1101             unit + MAX_DRAW_BUFFERS, /* surface */
1102             unit,     /* sampler */
1103             inst->DstReg.WriteMask,
1104             BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE,
1105             4,
1106             shadow ? 6 : 4,
1107             0);
1108
1109     if (shadow)
1110         brw_MOV(p, dst[3], brw_imm_f(1.0));
1111 }
1112
1113 static void post_wm_emit( struct brw_wm_compile *c )
1114 {
1115     GLuint nr_insns = c->fp->program.Base.NumInstructions;
1116     GLuint insn, target_insn;
1117     struct prog_instruction *inst1, *inst2;
1118     struct brw_instruction *brw_inst1, *brw_inst2;
1119     int offset;
1120     for (insn = 0; insn < nr_insns; insn++) {
1121         inst1 = &c->fp->program.Base.Instructions[insn];
1122         brw_inst1 = inst1->Data;
1123         switch (inst1->Opcode) {
1124             case OPCODE_CAL:
1125                 target_insn = inst1->BranchTarget;
1126                 inst2 = &c->fp->program.Base.Instructions[target_insn];
1127                 brw_inst2 = inst2->Data;
1128                 offset = brw_inst2 - brw_inst1;
1129                 brw_set_src1(brw_inst1, brw_imm_d(offset*16));
1130                 break;
1131             default:
1132                 break;
1133         }
1134     }
1135 }
1136
1137 static void brw_wm_emit_glsl(struct brw_context *brw, struct brw_wm_compile *c)
1138 {
1139 #define MAX_IFSN 32
1140 #define MAX_LOOP_DEPTH 32
1141     struct brw_instruction *if_inst[MAX_IFSN], *loop_inst[MAX_LOOP_DEPTH];
1142     struct brw_instruction *inst0, *inst1;
1143     int i, if_insn = 0, loop_insn = 0;
1144     struct brw_compile *p = &c->func;
1145     struct brw_indirect stack_index = brw_indirect(0, 0);
1146
1147     c->reg_index = 0;
1148     prealloc_reg(c);
1149     brw_set_compression_control(p, BRW_COMPRESSION_NONE);
1150     brw_MOV(p, get_addr_reg(stack_index), brw_address(c->stack));
1151
1152     for (i = 0; i < c->nr_fp_insns; i++) {
1153         struct prog_instruction *inst = &c->prog_instructions[i];
1154         struct prog_instruction *orig_inst;
1155
1156         if ((orig_inst = inst->Data) != 0)
1157             orig_inst->Data = current_insn(p);
1158
1159         if (inst->CondUpdate)
1160             brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ);
1161         else
1162             brw_set_conditionalmod(p, BRW_CONDITIONAL_NONE);
1163
1164         switch (inst->Opcode) {
1165             case WM_PIXELXY:
1166                 emit_pixel_xy(c, inst);
1167                 break;
1168             case WM_DELTAXY:
1169                 emit_delta_xy(c, inst);
1170                 break;
1171             case WM_PIXELW:
1172                 emit_pixel_w(c, inst);
1173                 break;
1174             case WM_LINTERP:
1175                 emit_linterp(c, inst);
1176                 break;
1177             case WM_PINTERP:
1178                 emit_pinterp(c, inst);
1179                 break;
1180             case WM_CINTERP:
1181                 emit_cinterp(c, inst);
1182                 break;
1183             case WM_WPOSXY:
1184                 emit_wpos_xy(c, inst);
1185                 break;
1186             case WM_FB_WRITE:
1187                 emit_fb_write(c, inst);
1188                 break;
1189             case OPCODE_ABS:
1190                 emit_abs(c, inst);
1191                 break;
1192             case OPCODE_ADD:
1193                 emit_add(c, inst);
1194                 break;
1195             case OPCODE_SUB:
1196                 emit_sub(c, inst);
1197                 break;
1198             case OPCODE_FRC:
1199                 emit_frc(c, inst);
1200                 break;
1201             case OPCODE_FLR:
1202                 emit_flr(c, inst);
1203                 break;
1204             case OPCODE_LRP:
1205                 emit_lrp(c, inst);
1206                 break;
1207             case OPCODE_INT:
1208                 emit_int(c, inst);
1209                 break;
1210             case OPCODE_MOV:
1211                 emit_mov(c, inst);
1212                 break;
1213             case OPCODE_DP3:
1214                 emit_dp3(c, inst);
1215                 break;
1216             case OPCODE_DP4:
1217                 emit_dp4(c, inst);
1218                 break;
1219             case OPCODE_XPD:
1220                 emit_xpd(c, inst);
1221                 break;
1222             case OPCODE_DPH:
1223                 emit_dph(c, inst);
1224                 break;
1225             case OPCODE_RCP:
1226                 emit_rcp(c, inst);
1227                 break;
1228             case OPCODE_RSQ:
1229                 emit_rsq(c, inst);
1230                 break;
1231             case OPCODE_SIN:
1232                 emit_sin(c, inst);
1233                 break;
1234             case OPCODE_COS:
1235                 emit_cos(c, inst);
1236                 break;
1237             case OPCODE_EX2:
1238                 emit_ex2(c, inst);
1239                 break;
1240             case OPCODE_LG2:
1241                 emit_lg2(c, inst);
1242                 break;
1243             case OPCODE_MAX:
1244                 emit_max(c, inst);
1245                 break;
1246             case OPCODE_MIN:
1247                 emit_min(c, inst);
1248                 break;
1249             case OPCODE_DDX:
1250                 emit_ddx(c, inst);
1251                 break;
1252             case OPCODE_DDY:
1253                 emit_ddy(c, inst);
1254                 break;
1255             case OPCODE_SLT:
1256                 emit_slt(c, inst);
1257                 break;
1258             case OPCODE_SLE:
1259                 emit_sle(c, inst);
1260                 break;
1261             case OPCODE_SGT:
1262                 emit_sgt(c, inst);
1263                 break;
1264             case OPCODE_SGE:
1265                 emit_sge(c, inst);
1266                 break;
1267             case OPCODE_SEQ:
1268                 emit_seq(c, inst);
1269                 break;
1270             case OPCODE_SNE:
1271                 emit_sne(c, inst);
1272                 break;
1273             case OPCODE_MUL:
1274                 emit_mul(c, inst);
1275                 break;
1276             case OPCODE_POW:
1277                 emit_pow(c, inst);
1278                 break;
1279             case OPCODE_MAD:
1280                 emit_mad(c, inst);
1281                 break;
1282             case OPCODE_TEX:
1283                 emit_tex(c, inst);
1284                 break;
1285             case OPCODE_TXB:
1286                 emit_txb(c, inst);
1287                 break;
1288             case OPCODE_KIL_NV:
1289                 emit_kil(c);
1290                 break;
1291             case OPCODE_IF:
1292                 assert(if_insn < MAX_IFSN);
1293                 if_inst[if_insn++] = brw_IF(p, BRW_EXECUTE_8);
1294                 break;
1295             case OPCODE_ELSE:
1296                 if_inst[if_insn-1]  = brw_ELSE(p, if_inst[if_insn-1]);
1297                 break;
1298             case OPCODE_ENDIF:
1299                 assert(if_insn > 0);
1300                 brw_ENDIF(p, if_inst[--if_insn]);
1301                 break;
1302             case OPCODE_BGNSUB:
1303             case OPCODE_ENDSUB:
1304                 break;
1305             case OPCODE_CAL:
1306                 brw_push_insn_state(p);
1307                 brw_set_mask_control(p, BRW_MASK_DISABLE);
1308                 brw_set_access_mode(p, BRW_ALIGN_1);
1309                 brw_ADD(p, deref_1ud(stack_index, 0), brw_ip_reg(), brw_imm_d(3*16));
1310                 brw_set_access_mode(p, BRW_ALIGN_16);
1311                 brw_ADD(p, get_addr_reg(stack_index),
1312                          get_addr_reg(stack_index), brw_imm_d(4));
1313                 orig_inst = inst->Data;
1314                 orig_inst->Data = &p->store[p->nr_insn];
1315                 brw_ADD(p, brw_ip_reg(), brw_ip_reg(), brw_imm_d(1*16));
1316                 brw_pop_insn_state(p);
1317                 break;
1318
1319             case OPCODE_RET:
1320                 brw_push_insn_state(p);
1321                 brw_set_mask_control(p, BRW_MASK_DISABLE);
1322                 brw_ADD(p, get_addr_reg(stack_index),
1323                         get_addr_reg(stack_index), brw_imm_d(-4));
1324                 brw_set_access_mode(p, BRW_ALIGN_1);
1325                 brw_MOV(p, brw_ip_reg(), deref_1ud(stack_index, 0));
1326                 brw_set_access_mode(p, BRW_ALIGN_16);
1327                 brw_pop_insn_state(p);
1328
1329                 break;
1330             case OPCODE_BGNLOOP:
1331                 loop_inst[loop_insn++] = brw_DO(p, BRW_EXECUTE_8);
1332                 break;
1333             case OPCODE_BRK:
1334                 brw_BREAK(p);
1335                 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
1336                 break;
1337             case OPCODE_CONT:
1338                 brw_CONT(p);
1339                 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
1340                 break;
1341             case OPCODE_ENDLOOP:
1342                 loop_insn--;
1343                 inst0 = inst1 = brw_WHILE(p, loop_inst[loop_insn]);
1344                 /* patch all the BREAK instructions from
1345                    last BEGINLOOP */
1346                 while (inst0 > loop_inst[loop_insn]) {
1347                     inst0--;
1348                     if (inst0->header.opcode == BRW_OPCODE_BREAK) {
1349                         inst0->bits3.if_else.jump_count = inst1 - inst0 + 1;
1350                         inst0->bits3.if_else.pop_count = 0;
1351                     } else if (inst0->header.opcode == BRW_OPCODE_CONTINUE) {
1352                         inst0->bits3.if_else.jump_count = inst1 - inst0;
1353                         inst0->bits3.if_else.pop_count = 0;
1354                     }
1355                 }
1356                 break;
1357             default:
1358                 _mesa_printf("unsupported IR in fragment shader %d\n",
1359                         inst->Opcode);
1360         }
1361         if (inst->CondUpdate)
1362             brw_set_predicate_control(p, BRW_PREDICATE_NORMAL);
1363         else
1364             brw_set_predicate_control(p, BRW_PREDICATE_NONE);
1365     }
1366     post_wm_emit(c);
1367     for (i = 0; i < c->fp->program.Base.NumInstructions; i++)
1368         c->fp->program.Base.Instructions[i].Data = NULL;
1369 }
1370
1371 void brw_wm_glsl_emit(struct brw_context *brw, struct brw_wm_compile *c)
1372 {
1373     brw_wm_pass_fp(c);
1374     brw_wm_emit_glsl(brw, c);
1375     c->prog_data.total_grf = c->reg_index;
1376     c->prog_data.total_scratch = 0;
1377 }