src/mesa/drivers/dri/i965/brw_wm_state.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33
  34 #include "brw_context.h"
  35 #include "brw_state.h"
  36 #include "brw_defines.h"
  37 #include "brw_wm.h"
  38
  39 /***********************************************************************
  40  * WM unit - fragment programs and rasterization
  41  */
  42
  43 struct brw_wm_unit_key {
  44    unsigned int total_grf, total_scratch;
  45    unsigned int urb_entry_read_length;
  46    unsigned int curb_entry_read_length;
  47    unsigned int dispatch_grf_start_reg;
  48
  49    unsigned int curbe_offset;
  50    unsigned int urb_size;
  51
  52    unsigned int max_threads;
  53
  54    unsigned int nr_surfaces, sampler_count;
  55    GLboolean uses_depth, computes_depth, uses_kill, is_glsl;
  56    GLboolean polygon_stipple, stats_wm, line_stipple, offset_enable;
  57    GLfloat offset_units, offset_factor;
  58 };
  59
  60 static void
  61 wm_unit_populate_key(struct brw_context *brw, struct brw_wm_unit_key *key)
  62 {
  63    GLcontext *ctx = &brw->intel.ctx;
  64    const struct gl_fragment_program *fp = brw->fragment_program;
  65    const struct brw_fragment_program *bfp = (struct brw_fragment_program *) fp;
  66    struct intel_context *intel = &brw->intel;
  67
  68    memset(key, 0, sizeof(*key));
  69
  70    if (INTEL_DEBUG & DEBUG_SINGLE_THREAD)
  71       key->max_threads = 1;
  72    else {
  73       /* WM maximum threads is number of EUs times number of threads per EU. */
  74       if (BRW_IS_IGDNG(brw))
  75          key->max_threads = 12 * 6;
  76       else if (BRW_IS_G4X(brw))
  77          key->max_threads = 10 * 5;
  78       else
  79          key->max_threads = 8 * 4;
  80    }
  81
  82    /* CACHE_NEW_WM_PROG */
  83    key->total_grf = brw->wm.prog_data->total_grf;
  84    key->urb_entry_read_length = brw->wm.prog_data->urb_read_length;
  85    key->curb_entry_read_length = brw->wm.prog_data->curb_read_length;
  86    key->dispatch_grf_start_reg = brw->wm.prog_data->first_curbe_grf;
  87    key->total_scratch = ALIGN(brw->wm.prog_data->total_scratch, 1024);
  88
  89    /* BRW_NEW_URB_FENCE */
  90    key->urb_size = brw->urb.vsize;
  91
  92    /* BRW_NEW_CURBE_OFFSETS */
  93    key->curbe_offset = brw->curbe.wm_start;
  94
  95    /* BRW_NEW_NR_SURFACEs */
  96    key->nr_surfaces = brw->wm.nr_surfaces;
  97
  98    /* CACHE_NEW_SAMPLER */
  99    key->sampler_count = brw->wm.sampler_count;
 100
 101    /* _NEW_POLYGONSTIPPLE */
 102    key->polygon_stipple = ctx->Polygon.StippleFlag;
 103
 104    /* BRW_NEW_FRAGMENT_PROGRAM */
 105    key->uses_depth = (fp->Base.InputsRead & (1 << FRAG_ATTRIB_WPOS)) != 0;
 106
 107    /* as far as we can tell */
 108    key->computes_depth =
 109       (fp->Base.OutputsWritten & (1 << FRAG_RESULT_DEPTH)) != 0;
 110
 111    /* _NEW_COLOR */
 112    key->uses_kill = fp->UsesKill || ctx->Color.AlphaEnabled;
 113    key->is_glsl = bfp->isGLSL;
 114
 115    /* temporary sanity check assertion */
 116    ASSERT(bfp->isGLSL == brw_wm_is_glsl(fp));
 117
 118    /* _NEW_DEPTH */
 119    key->stats_wm = intel->stats_wm;
 120
 121    /* _NEW_LINE */
 122    key->line_stipple = ctx->Line.StippleFlag;
 123
 124    /* _NEW_POLYGON */
 125    key->offset_enable = ctx->Polygon.OffsetFill;
 126    key->offset_units = ctx->Polygon.OffsetUnits;
 127    key->offset_factor = ctx->Polygon.OffsetFactor;
 128 }
 129
 130 /**
 131  * Setup wm hardware state.  See page 225 of Volume 2
 132  */
 133 static dri_bo *
 134 wm_unit_create_from_key(struct brw_context *brw, struct brw_wm_unit_key *key,
 135                         dri_bo **reloc_bufs)
 136 {
 137    struct brw_wm_unit_state wm;
 138    dri_bo *bo;
 139
 140    memset(&wm, 0, sizeof(wm));
 141
 142    wm.thread0.grf_reg_count = ALIGN(key->total_grf, 16) / 16 - 1;
 143    wm.thread0.kernel_start_pointer = brw->wm.prog_bo->offset >> 6; /* reloc */
 144    wm.thread1.depth_coef_urb_read_offset = 1;
 145    wm.thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754;
 146
 147    if (BRW_IS_IGDNG(brw))
 148       wm.thread1.binding_table_entry_count = 0; /* hardware requirement */
 149    else
 150       wm.thread1.binding_table_entry_count = key->nr_surfaces;
 151
 152    if (key->total_scratch != 0) {
 153       wm.thread2.scratch_space_base_pointer =
 154          brw->wm.scratch_bo->offset >> 10; /* reloc */
 155       wm.thread2.per_thread_scratch_space = key->total_scratch / 1024 - 1;
 156    } else {
 157       wm.thread2.scratch_space_base_pointer = 0;
 158       wm.thread2.per_thread_scratch_space = 0;
 159    }
 160
 161    wm.thread3.dispatch_grf_start_reg = key->dispatch_grf_start_reg;
 162    wm.thread3.urb_entry_read_length = key->urb_entry_read_length;
 163    wm.thread3.urb_entry_read_offset = 0;
 164    wm.thread3.const_urb_entry_read_length = key->curb_entry_read_length;
 165    wm.thread3.const_urb_entry_read_offset = key->curbe_offset * 2;
 166
 167    if (BRW_IS_IGDNG(brw))
 168       wm.wm4.sampler_count = 0; /* hardware requirement */
 169    else
 170       wm.wm4.sampler_count = (key->sampler_count + 1) / 4;
 171
 172    if (brw->wm.sampler_bo != NULL) {
 173       /* reloc */
 174       wm.wm4.sampler_state_pointer = brw->wm.sampler_bo->offset >> 5;
 175    } else {
 176       wm.wm4.sampler_state_pointer = 0;
 177    }
 178
 179    wm.wm5.program_uses_depth = key->uses_depth;
 180    wm.wm5.program_computes_depth = key->computes_depth;
 181    wm.wm5.program_uses_killpixel = key->uses_kill;
 182
 183    if (key->is_glsl)
 184       wm.wm5.enable_8_pix = 1;
 185    else
 186       wm.wm5.enable_16_pix = 1;
 187
 188    wm.wm5.max_threads = key->max_threads - 1;
 189    wm.wm5.thread_dispatch_enable = 1;   /* AKA: color_write */
 190    wm.wm5.legacy_line_rast = 0;
 191    wm.wm5.legacy_global_depth_bias = 0;
 192    wm.wm5.early_depth_test = 1;         /* never need to disable */
 193    wm.wm5.line_aa_region_width = 0;
 194    wm.wm5.line_endcap_aa_region_width = 1;
 195
 196    wm.wm5.polygon_stipple = key->polygon_stipple;
 197
 198    if (key->offset_enable) {
 199       wm.wm5.depth_offset = 1;
 200       /* Something wierd going on with legacy_global_depth_bias,
 201        * offset_constant, scaling and MRD.  This value passes glean
 202        * but gives some odd results elsewere (eg. the
 203        * quad-offset-units test).
 204        */
 205       wm.global_depth_offset_constant = key->offset_units * 2;
 206
 207       /* This is the only value that passes glean:
 208        */
 209       wm.global_depth_offset_scale = key->offset_factor;
 210    }
 211
 212    wm.wm5.line_stipple = key->line_stipple;
 213
 214    if (INTEL_DEBUG & DEBUG_STATS || key->stats_wm)
 215       wm.wm4.stats_enable = 1;
 216
 217    bo = brw_upload_cache(&brw->cache, BRW_WM_UNIT,
 218                          key, sizeof(*key),
 219                          reloc_bufs, 3,
 220                          &wm, sizeof(wm),
 221                          NULL, NULL);
 222
 223    /* Emit WM program relocation */
 224    dri_bo_emit_reloc(bo,
 225                      I915_GEM_DOMAIN_INSTRUCTION, 0,
 226                      wm.thread0.grf_reg_count << 1,
 227                      offsetof(struct brw_wm_unit_state, thread0),
 228                      brw->wm.prog_bo);
 229
 230    /* Emit scratch space relocation */
 231    if (key->total_scratch != 0) {
 232       dri_bo_emit_reloc(bo,
 233                         0, 0,
 234                         wm.thread2.per_thread_scratch_space,
 235                         offsetof(struct brw_wm_unit_state, thread2),
 236                         brw->wm.scratch_bo);
 237    }
 238
 239    /* Emit sampler state relocation */
 240    if (key->sampler_count != 0) {
 241       dri_bo_emit_reloc(bo,
 242                         I915_GEM_DOMAIN_INSTRUCTION, 0,
 243                         wm.wm4.stats_enable | (wm.wm4.sampler_count << 2),
 244                         offsetof(struct brw_wm_unit_state, wm4),
 245                         brw->wm.sampler_bo);
 246    }
 247
 248    return bo;
 249 }
 250
 251
 252 static void upload_wm_unit( struct brw_context *brw )
 253 {
 254    struct intel_context *intel = &brw->intel;
 255    struct brw_wm_unit_key key;
 256    dri_bo *reloc_bufs[3];
 257    wm_unit_populate_key(brw, &key);
 258
 259    /* Allocate the necessary scratch space if we haven't already.  Don't
 260     * bother reducing the allocation later, since we use scratch so
 261     * rarely.
 262     */
 263    assert(key.total_scratch <= 12 * 1024);
 264    if (key.total_scratch) {
 265       GLuint total = key.total_scratch * key.max_threads;
 266
 267       if (brw->wm.scratch_bo && total > brw->wm.scratch_bo->size) {
 268          dri_bo_unreference(brw->wm.scratch_bo);
 269          brw->wm.scratch_bo = NULL;
 270       }
 271       if (brw->wm.scratch_bo == NULL) {
 272          brw->wm.scratch_bo = dri_bo_alloc(intel->bufmgr,
 273                                            "wm scratch",
 274                                            total,
 275                                            4096);
 276       }
 277    }
 278
 279    reloc_bufs[0] = brw->wm.prog_bo;
 280    reloc_bufs[1] = brw->wm.scratch_bo;
 281    reloc_bufs[2] = brw->wm.sampler_bo;
 282
 283    dri_bo_unreference(brw->wm.state_bo);
 284    brw->wm.state_bo = brw_search_cache(&brw->cache, BRW_WM_UNIT,
 285                                        &key, sizeof(key),
 286                                        reloc_bufs, 3,
 287                                        NULL);
 288    if (brw->wm.state_bo == NULL) {
 289       brw->wm.state_bo = wm_unit_create_from_key(brw, &key, reloc_bufs);
 290    }
 291 }
 292
 293 const struct brw_tracked_state brw_wm_unit = {
 294    .dirty = {
 295       .mesa = (_NEW_POLYGON |
 296                _NEW_POLYGONSTIPPLE |
 297                _NEW_LINE |
 298                _NEW_COLOR |
 299                _NEW_DEPTH),
 300
 301       .brw = (BRW_NEW_FRAGMENT_PROGRAM |
 302               BRW_NEW_CURBE_OFFSETS |
 303               BRW_NEW_NR_WM_SURFACES),
 304
 305       .cache = (CACHE_NEW_WM_PROG |
 306                 CACHE_NEW_SAMPLER)
 307    },
 308    .prepare = upload_wm_unit,
 309 };
 310