src/mesa/drivers/dri/i965/brw_wm_state.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33
  34 #include "brw_context.h"
  35 #include "brw_state.h"
  36 #include "brw_defines.h"
  37 #include "brw_wm.h"
  38
  39 /***********************************************************************
  40  * WM unit - fragment programs and rasterization
  41  */
  42
  43 struct brw_wm_unit_key {
  44    unsigned int total_grf, total_scratch;
  45    unsigned int urb_entry_read_length;
  46    unsigned int curb_entry_read_length;
  47    unsigned int dispatch_grf_start_reg;
  48
  49    unsigned int curbe_offset;
  50    unsigned int urb_size;
  51
  52    unsigned int max_threads;
  53
  54    unsigned int nr_surfaces, sampler_count;
  55    GLboolean uses_depth, computes_depth, uses_kill, is_glsl;
  56    GLboolean polygon_stipple, stats_wm, line_stipple, offset_enable;
  57    GLfloat offset_units, offset_factor;
  58 };
  59
  60 static void
  61 wm_unit_populate_key(struct brw_context *brw, struct brw_wm_unit_key *key)
  62 {
  63    GLcontext *ctx = &brw->intel.ctx;
  64    const struct gl_fragment_program *fp = brw->fragment_program;
  65    const struct brw_fragment_program *bfp = (struct brw_fragment_program *) fp;
  66    struct intel_context *intel = &brw->intel;
  67
  68    memset(key, 0, sizeof(*key));
  69
  70    if (INTEL_DEBUG & DEBUG_SINGLE_THREAD)
  71       key->max_threads = 1;
  72    else {
  73       /* WM maximum threads is number of EUs times number of threads per EU. */
  74       if (BRW_IS_IGDNG(brw))
  75          key->max_threads = 12 * 6;
  76       else if (BRW_IS_G4X(brw))
  77          key->max_threads = 10 * 5;
  78       else
  79          key->max_threads = 8 * 4;
  80    }
  81
  82    /* CACHE_NEW_WM_PROG */
  83    key->total_grf = brw->wm.prog_data->total_grf;
  84    key->urb_entry_read_length = brw->wm.prog_data->urb_read_length;
  85    key->curb_entry_read_length = brw->wm.prog_data->curb_read_length;
  86    key->dispatch_grf_start_reg = brw->wm.prog_data->first_curbe_grf;
  87    key->total_scratch = ALIGN(brw->wm.prog_data->total_scratch, 1024);
  88
  89    /* BRW_NEW_URB_FENCE */
  90    key->urb_size = brw->urb.vsize;
  91
  92    /* BRW_NEW_CURBE_OFFSETS */
  93    key->curbe_offset = brw->curbe.wm_start;
  94
  95    /* BRW_NEW_NR_SURFACEs */
  96    key->nr_surfaces = brw->wm.nr_surfaces;
  97
  98    /* CACHE_NEW_SAMPLER */
  99    key->sampler_count = brw->wm.sampler_count;
 100
 101    /* _NEW_POLYGONSTIPPLE */
 102    key->polygon_stipple = ctx->Polygon.StippleFlag;
 103
 104    /* BRW_NEW_FRAGMENT_PROGRAM */
 105    key->uses_depth = (fp->Base.InputsRead & (1 << FRAG_ATTRIB_WPOS)) != 0;
 106
 107    /* as far as we can tell */
 108    key->computes_depth =
 109       (fp->Base.OutputsWritten & (1 << FRAG_RESULT_DEPTH)) != 0;
 110    /* BRW_NEW_DEPTH_BUFFER
 111     * Override for NULL depthbuffer case, required by the Pixel Shader Computed
 112     * Depth field.
 113     */
 114    if (brw->state.depth_region == NULL)
 115       key->computes_depth = 0;
 116
 117    /* _NEW_COLOR */
 118    key->uses_kill = fp->UsesKill || ctx->Color.AlphaEnabled;
 119    key->is_glsl = bfp->isGLSL;
 120
 121    /* temporary sanity check assertion */
 122    ASSERT(bfp->isGLSL == brw_wm_is_glsl(fp));
 123
 124    /* _NEW_DEPTH */
 125    key->stats_wm = intel->stats_wm;
 126
 127    /* _NEW_LINE */
 128    key->line_stipple = ctx->Line.StippleFlag;
 129
 130    /* _NEW_POLYGON */
 131    key->offset_enable = ctx->Polygon.OffsetFill;
 132    key->offset_units = ctx->Polygon.OffsetUnits;
 133    key->offset_factor = ctx->Polygon.OffsetFactor;
 134 }
 135
 136 /**
 137  * Setup wm hardware state.  See page 225 of Volume 2
 138  */
 139 static dri_bo *
 140 wm_unit_create_from_key(struct brw_context *brw, struct brw_wm_unit_key *key,
 141                         dri_bo **reloc_bufs)
 142 {
 143    struct brw_wm_unit_state wm;
 144    dri_bo *bo;
 145
 146    memset(&wm, 0, sizeof(wm));
 147
 148    wm.thread0.grf_reg_count = ALIGN(key->total_grf, 16) / 16 - 1;
 149    wm.thread0.kernel_start_pointer = brw->wm.prog_bo->offset >> 6; /* reloc */
 150    wm.thread1.depth_coef_urb_read_offset = 1;
 151    wm.thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754;
 152
 153    if (BRW_IS_IGDNG(brw))
 154       wm.thread1.binding_table_entry_count = 0; /* hardware requirement */
 155    else
 156       wm.thread1.binding_table_entry_count = key->nr_surfaces;
 157
 158    if (key->total_scratch != 0) {
 159       wm.thread2.scratch_space_base_pointer =
 160          brw->wm.scratch_bo->offset >> 10; /* reloc */
 161       wm.thread2.per_thread_scratch_space = key->total_scratch / 1024 - 1;
 162    } else {
 163       wm.thread2.scratch_space_base_pointer = 0;
 164       wm.thread2.per_thread_scratch_space = 0;
 165    }
 166
 167    wm.thread3.dispatch_grf_start_reg = key->dispatch_grf_start_reg;
 168    wm.thread3.urb_entry_read_length = key->urb_entry_read_length;
 169    wm.thread3.urb_entry_read_offset = 0;
 170    wm.thread3.const_urb_entry_read_length = key->curb_entry_read_length;
 171    wm.thread3.const_urb_entry_read_offset = key->curbe_offset * 2;
 172
 173    if (BRW_IS_IGDNG(brw))
 174       wm.wm4.sampler_count = 0; /* hardware requirement */
 175    else
 176       wm.wm4.sampler_count = (key->sampler_count + 1) / 4;
 177
 178    if (brw->wm.sampler_bo != NULL) {
 179       /* reloc */
 180       wm.wm4.sampler_state_pointer = brw->wm.sampler_bo->offset >> 5;
 181    } else {
 182       wm.wm4.sampler_state_pointer = 0;
 183    }
 184
 185    wm.wm5.program_uses_depth = key->uses_depth;
 186    wm.wm5.program_computes_depth = key->computes_depth;
 187    wm.wm5.program_uses_killpixel = key->uses_kill;
 188
 189    if (key->is_glsl)
 190       wm.wm5.enable_8_pix = 1;
 191    else
 192       wm.wm5.enable_16_pix = 1;
 193
 194    wm.wm5.max_threads = key->max_threads - 1;
 195    wm.wm5.thread_dispatch_enable = 1;   /* AKA: color_write */
 196    wm.wm5.legacy_line_rast = 0;
 197    wm.wm5.legacy_global_depth_bias = 0;
 198    wm.wm5.early_depth_test = 1;         /* never need to disable */
 199    wm.wm5.line_aa_region_width = 0;
 200    wm.wm5.line_endcap_aa_region_width = 1;
 201
 202    wm.wm5.polygon_stipple = key->polygon_stipple;
 203
 204    if (key->offset_enable) {
 205       wm.wm5.depth_offset = 1;
 206       /* Something wierd going on with legacy_global_depth_bias,
 207        * offset_constant, scaling and MRD.  This value passes glean
 208        * but gives some odd results elsewere (eg. the
 209        * quad-offset-units test).
 210        */
 211       wm.global_depth_offset_constant = key->offset_units * 2;
 212
 213       /* This is the only value that passes glean:
 214        */
 215       wm.global_depth_offset_scale = key->offset_factor;
 216    }
 217
 218    wm.wm5.line_stipple = key->line_stipple;
 219
 220    if (INTEL_DEBUG & DEBUG_STATS || key->stats_wm)
 221       wm.wm4.stats_enable = 1;
 222
 223    bo = brw_upload_cache(&brw->cache, BRW_WM_UNIT,
 224                          key, sizeof(*key),
 225                          reloc_bufs, 3,
 226                          &wm, sizeof(wm),
 227                          NULL, NULL);
 228
 229    /* Emit WM program relocation */
 230    dri_bo_emit_reloc(bo,
 231                      I915_GEM_DOMAIN_INSTRUCTION, 0,
 232                      wm.thread0.grf_reg_count << 1,
 233                      offsetof(struct brw_wm_unit_state, thread0),
 234                      brw->wm.prog_bo);
 235
 236    /* Emit scratch space relocation */
 237    if (key->total_scratch != 0) {
 238       dri_bo_emit_reloc(bo,
 239                         0, 0,
 240                         wm.thread2.per_thread_scratch_space,
 241                         offsetof(struct brw_wm_unit_state, thread2),
 242                         brw->wm.scratch_bo);
 243    }
 244
 245    /* Emit sampler state relocation */
 246    if (key->sampler_count != 0) {
 247       dri_bo_emit_reloc(bo,
 248                         I915_GEM_DOMAIN_INSTRUCTION, 0,
 249                         wm.wm4.stats_enable | (wm.wm4.sampler_count << 2),
 250                         offsetof(struct brw_wm_unit_state, wm4),
 251                         brw->wm.sampler_bo);
 252    }
 253
 254    return bo;
 255 }
 256
 257
 258 static void upload_wm_unit( struct brw_context *brw )
 259 {
 260    struct intel_context *intel = &brw->intel;
 261    struct brw_wm_unit_key key;
 262    dri_bo *reloc_bufs[3];
 263    wm_unit_populate_key(brw, &key);
 264
 265    /* Allocate the necessary scratch space if we haven't already.  Don't
 266     * bother reducing the allocation later, since we use scratch so
 267     * rarely.
 268     */
 269    assert(key.total_scratch <= 12 * 1024);
 270    if (key.total_scratch) {
 271       GLuint total = key.total_scratch * key.max_threads;
 272
 273       if (brw->wm.scratch_bo && total > brw->wm.scratch_bo->size) {
 274          dri_bo_unreference(brw->wm.scratch_bo);
 275          brw->wm.scratch_bo = NULL;
 276       }
 277       if (brw->wm.scratch_bo == NULL) {
 278          brw->wm.scratch_bo = dri_bo_alloc(intel->bufmgr,
 279                                            "wm scratch",
 280                                            total,
 281                                            4096);
 282       }
 283    }
 284
 285    reloc_bufs[0] = brw->wm.prog_bo;
 286    reloc_bufs[1] = brw->wm.scratch_bo;
 287    reloc_bufs[2] = brw->wm.sampler_bo;
 288
 289    dri_bo_unreference(brw->wm.state_bo);
 290    brw->wm.state_bo = brw_search_cache(&brw->cache, BRW_WM_UNIT,
 291                                        &key, sizeof(key),
 292                                        reloc_bufs, 3,
 293                                        NULL);
 294    if (brw->wm.state_bo == NULL) {
 295       brw->wm.state_bo = wm_unit_create_from_key(brw, &key, reloc_bufs);
 296    }
 297 }
 298
 299 const struct brw_tracked_state brw_wm_unit = {
 300    .dirty = {
 301       .mesa = (_NEW_POLYGON |
 302                _NEW_POLYGONSTIPPLE |
 303                _NEW_LINE |
 304                _NEW_COLOR |
 305                _NEW_DEPTH),
 306
 307       .brw = (BRW_NEW_FRAGMENT_PROGRAM |
 308               BRW_NEW_CURBE_OFFSETS |
 309               BRW_NEW_DEPTH_BUFFER |
 310               BRW_NEW_NR_WM_SURFACES),
 311
 312       .cache = (CACHE_NEW_WM_PROG |
 313                 CACHE_NEW_SAMPLER)
 314    },
 315    .prepare = upload_wm_unit,
 316 };
 317