src/mesa/drivers/dri/i965/brw_wm_surface_state.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keith@tungstengraphics.com>
  30   */
  31
  32
  33 #include "main/mtypes.h"
  34 #include "main/texstore.h"
  35 #include "program/prog_parameter.h"
  36
  37 #include "intel_mipmap_tree.h"
  38 #include "intel_batchbuffer.h"
  39 #include "intel_tex.h"
  40 #include "intel_fbo.h"
  41
  42 #include "brw_context.h"
  43 #include "brw_state.h"
  44 #include "brw_defines.h"
  45
  46
  47 static GLuint translate_tex_target( GLenum target )
  48 {
  49    switch (target) {
  50    case GL_TEXTURE_1D:
  51       return BRW_SURFACE_1D;
  52
  53    case GL_TEXTURE_RECTANGLE_NV:
  54       return BRW_SURFACE_2D;
  55
  56    case GL_TEXTURE_2D:
  57       return BRW_SURFACE_2D;
  58
  59    case GL_TEXTURE_3D:
  60       return BRW_SURFACE_3D;
  61
  62    case GL_TEXTURE_CUBE_MAP:
  63       return BRW_SURFACE_CUBE;
  64
  65    default:
  66       assert(0);
  67       return 0;
  68    }
  69 }
  70
  71
  72 static GLuint translate_tex_format( gl_format mesa_format,
  73                                     GLenum internal_format,
  74                                     GLenum depth_mode )
  75 {
  76    switch( mesa_format ) {
  77    case MESA_FORMAT_L8:
  78       return BRW_SURFACEFORMAT_L8_UNORM;
  79
  80    case MESA_FORMAT_I8:
  81       return BRW_SURFACEFORMAT_I8_UNORM;
  82
  83    case MESA_FORMAT_A8:
  84       return BRW_SURFACEFORMAT_A8_UNORM;
  85
  86    case MESA_FORMAT_AL88:
  87       return BRW_SURFACEFORMAT_L8A8_UNORM;
  88
  89    case MESA_FORMAT_AL1616:
  90       return BRW_SURFACEFORMAT_L16A16_UNORM;
  91
  92    case MESA_FORMAT_R8:
  93       return BRW_SURFACEFORMAT_R8_UNORM;
  94
  95    case MESA_FORMAT_R16:
  96       return BRW_SURFACEFORMAT_R16_UNORM;
  97
  98    case MESA_FORMAT_RG88:
  99       return BRW_SURFACEFORMAT_R8G8_UNORM;
 100
 101    case MESA_FORMAT_RG1616:
 102       return BRW_SURFACEFORMAT_R16G16_UNORM;
 103
 104    case MESA_FORMAT_RGB888:
 105       assert(0);                /* not supported for sampling */
 106       return BRW_SURFACEFORMAT_R8G8B8_UNORM;
 107
 108    case MESA_FORMAT_ARGB8888:
 109       return BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
 110
 111    case MESA_FORMAT_XRGB8888:
 112       return BRW_SURFACEFORMAT_B8G8R8X8_UNORM;
 113
 114    case MESA_FORMAT_RGBA8888_REV:
 115       _mesa_problem(NULL, "unexpected format in i965:translate_tex_format()");
 116       return BRW_SURFACEFORMAT_R8G8B8A8_UNORM;
 117
 118    case MESA_FORMAT_RGB565:
 119       return BRW_SURFACEFORMAT_B5G6R5_UNORM;
 120
 121    case MESA_FORMAT_ARGB1555:
 122       return BRW_SURFACEFORMAT_B5G5R5A1_UNORM;
 123
 124    case MESA_FORMAT_ARGB4444:
 125       return BRW_SURFACEFORMAT_B4G4R4A4_UNORM;
 126
 127    case MESA_FORMAT_YCBCR_REV:
 128       return BRW_SURFACEFORMAT_YCRCB_NORMAL;
 129
 130    case MESA_FORMAT_YCBCR:
 131       return BRW_SURFACEFORMAT_YCRCB_SWAPUVY;
 132
 133    case MESA_FORMAT_RGB_FXT1:
 134    case MESA_FORMAT_RGBA_FXT1:
 135       return BRW_SURFACEFORMAT_FXT1;
 136
 137    case MESA_FORMAT_Z16:
 138       if (depth_mode == GL_INTENSITY)
 139           return BRW_SURFACEFORMAT_I16_UNORM;
 140       else if (depth_mode == GL_ALPHA)
 141           return BRW_SURFACEFORMAT_A16_UNORM;
 142       else
 143           return BRW_SURFACEFORMAT_L16_UNORM;
 144
 145    case MESA_FORMAT_RGB_DXT1:
 146        return BRW_SURFACEFORMAT_DXT1_RGB;
 147
 148    case MESA_FORMAT_RGBA_DXT1:
 149        return BRW_SURFACEFORMAT_BC1_UNORM;
 150
 151    case MESA_FORMAT_RGBA_DXT3:
 152        return BRW_SURFACEFORMAT_BC2_UNORM;
 153
 154    case MESA_FORMAT_RGBA_DXT5:
 155        return BRW_SURFACEFORMAT_BC3_UNORM;
 156
 157    case MESA_FORMAT_SARGB8:
 158       return BRW_SURFACEFORMAT_B8G8R8A8_UNORM_SRGB;
 159
 160    case MESA_FORMAT_SLA8:
 161       return BRW_SURFACEFORMAT_L8A8_UNORM_SRGB;
 162
 163    case MESA_FORMAT_SL8:
 164       return BRW_SURFACEFORMAT_L8_UNORM_SRGB;
 165
 166    case MESA_FORMAT_SRGB_DXT1:
 167       return BRW_SURFACEFORMAT_BC1_UNORM_SRGB;
 168
 169    case MESA_FORMAT_S8_Z24:
 170       /* XXX: these different surface formats don't seem to
 171        * make any difference for shadow sampler/compares.
 172        */
 173       if (depth_mode == GL_INTENSITY)
 174          return BRW_SURFACEFORMAT_I24X8_UNORM;
 175       else if (depth_mode == GL_ALPHA)
 176          return BRW_SURFACEFORMAT_A24X8_UNORM;
 177       else
 178          return BRW_SURFACEFORMAT_L24X8_UNORM;
 179
 180    case MESA_FORMAT_DUDV8:
 181       return BRW_SURFACEFORMAT_R8G8_SNORM;
 182
 183    case MESA_FORMAT_SIGNED_RGBA8888_REV:
 184       return BRW_SURFACEFORMAT_R8G8B8A8_SNORM;
 185
 186    default:
 187       assert(0);
 188       return 0;
 189    }
 190 }
 191
 192 static void
 193 brw_set_surface_tiling(struct brw_surface_state *surf, uint32_t tiling)
 194 {
 195    switch (tiling) {
 196    case I915_TILING_NONE:
 197       surf->ss3.tiled_surface = 0;
 198       surf->ss3.tile_walk = 0;
 199       break;
 200    case I915_TILING_X:
 201       surf->ss3.tiled_surface = 1;
 202       surf->ss3.tile_walk = BRW_TILEWALK_XMAJOR;
 203       break;
 204    case I915_TILING_Y:
 205       surf->ss3.tiled_surface = 1;
 206       surf->ss3.tile_walk = BRW_TILEWALK_YMAJOR;
 207       break;
 208    }
 209 }
 210
 211 static void
 212 brw_update_texture_surface( struct gl_context *ctx, GLuint unit )
 213 {
 214    struct brw_context *brw = brw_context(ctx);
 215    struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
 216    struct intel_texture_object *intelObj = intel_texture_object(tObj);
 217    struct gl_texture_image *firstImage = tObj->Image[0][intelObj->firstLevel];
 218    const GLuint surf_index = SURF_INDEX_TEXTURE(unit);
 219    struct brw_surface_state surf;
 220    void *map;
 221
 222    memset(&surf, 0, sizeof(surf));
 223
 224    surf.ss0.mipmap_layout_mode = BRW_SURFACE_MIPMAPLAYOUT_BELOW;
 225    surf.ss0.surface_type = translate_tex_target(tObj->Target);
 226    surf.ss0.surface_format = translate_tex_format(firstImage->TexFormat,
 227                                                   firstImage->InternalFormat,
 228                                                   tObj->DepthMode);
 229
 230    /* This is ok for all textures with channel width 8bit or less:
 231     */
 232 /*    surf.ss0.data_return_format = BRW_SURFACERETURNFORMAT_S1; */
 233    surf.ss1.base_addr = intelObj->mt->region->buffer->offset; /* reloc */
 234
 235    surf.ss2.mip_count = intelObj->lastLevel - intelObj->firstLevel;
 236    surf.ss2.width = firstImage->Width - 1;
 237    surf.ss2.height = firstImage->Height - 1;
 238    brw_set_surface_tiling(&surf, intelObj->mt->region->tiling);
 239    surf.ss3.pitch = (intelObj->mt->region->pitch * intelObj->mt->cpp) - 1;
 240    surf.ss3.depth = firstImage->Depth - 1;
 241
 242    surf.ss4.min_lod = 0;
 243
 244    if (tObj->Target == GL_TEXTURE_CUBE_MAP) {
 245       surf.ss0.cube_pos_x = 1;
 246       surf.ss0.cube_pos_y = 1;
 247       surf.ss0.cube_pos_z = 1;
 248       surf.ss0.cube_neg_x = 1;
 249       surf.ss0.cube_neg_y = 1;
 250       surf.ss0.cube_neg_z = 1;
 251    }
 252
 253    map = brw_state_batch(brw, sizeof(surf), 32,
 254                          &brw->wm.surf_bo[surf_index],
 255                          &brw->wm.surf_offset[surf_index]);
 256    memcpy(map, &surf, sizeof(surf));
 257
 258    /* Emit relocation to surface contents */
 259    drm_intel_bo_emit_reloc(brw->wm.surf_bo[surf_index],
 260                            brw->wm.surf_offset[surf_index] +
 261                            offsetof(struct brw_surface_state, ss1),
 262                            intelObj->mt->region->buffer, 0,
 263                            I915_GEM_DOMAIN_SAMPLER, 0);
 264 }
 265
 266 /**
 267  * Create the constant buffer surface.  Vertex/fragment shader constants will be
 268  * read from this buffer with Data Port Read instructions/messages.
 269  */
 270 void
 271 brw_create_constant_surface(struct brw_context *brw,
 272                             drm_intel_bo *bo,
 273                             int width,
 274                             drm_intel_bo **out_bo,
 275                             uint32_t *out_offset)
 276 {
 277    const GLint w = width - 1;
 278    struct brw_surface_state surf;
 279    void *map;
 280
 281    memset(&surf, 0, sizeof(surf));
 282
 283    surf.ss0.mipmap_layout_mode = BRW_SURFACE_MIPMAPLAYOUT_BELOW;
 284    surf.ss0.surface_type = BRW_SURFACE_BUFFER;
 285    surf.ss0.surface_format = BRW_SURFACEFORMAT_R32G32B32A32_FLOAT;
 286
 287    assert(bo);
 288    surf.ss1.base_addr = bo->offset; /* reloc */
 289
 290    surf.ss2.width = w & 0x7f;            /* bits 6:0 of size or width */
 291    surf.ss2.height = (w >> 7) & 0x1fff;  /* bits 19:7 of size or width */
 292    surf.ss3.depth = (w >> 20) & 0x7f;    /* bits 26:20 of size or width */
 293    surf.ss3.pitch = (width * 16) - 1; /* ignored?? */
 294    brw_set_surface_tiling(&surf, I915_TILING_NONE); /* tiling now allowed */
 295
 296    map = brw_state_batch(brw, sizeof(surf), 32, out_bo, out_offset);
 297    memcpy(map, &surf, sizeof(surf));
 298
 299    /* Emit relocation to surface contents.  Section 5.1.1 of the gen4
 300     * bspec ("Data Cache") says that the data cache does not exist as
 301     * a separate cache and is just the sampler cache.
 302     */
 303    drm_intel_bo_emit_reloc(*out_bo, (*out_offset +
 304                                      offsetof(struct brw_surface_state, ss1)),
 305                            bo, 0,
 306                            I915_GEM_DOMAIN_SAMPLER, 0);
 307 }
 308
 309 /* Creates a new WM constant buffer reflecting the current fragment program's
 310  * constants, if needed by the fragment program.
 311  *
 312  * Otherwise, constants go through the CURBEs using the brw_constant_buffer
 313  * state atom.
 314  */
 315 static void
 316 prepare_wm_constants(struct brw_context *brw)
 317 {
 318    struct gl_context *ctx = &brw->intel.ctx;
 319    struct intel_context *intel = &brw->intel;
 320    struct brw_fragment_program *fp =
 321       (struct brw_fragment_program *) brw->fragment_program;
 322    const int size = brw->wm.prog_data->nr_pull_params * sizeof(float);
 323    float *constants;
 324    unsigned int i;
 325
 326    _mesa_load_state_parameters(ctx, fp->program.Base.Parameters);
 327
 328    /* BRW_NEW_FRAGMENT_PROGRAM */
 329    if (brw->wm.prog_data->nr_pull_params == 0) {
 330       if (brw->wm.const_bo) {
 331          drm_intel_bo_unreference(brw->wm.const_bo);
 332          brw->wm.const_bo = NULL;
 333          brw->state.dirty.brw |= BRW_NEW_WM_CONSTBUF;
 334       }
 335       return;
 336    }
 337
 338    drm_intel_bo_unreference(brw->wm.const_bo);
 339    brw->wm.const_bo = drm_intel_bo_alloc(intel->bufmgr, "WM const bo",
 340                                          size, 64);
 341
 342    /* _NEW_PROGRAM_CONSTANTS */
 343    drm_intel_gem_bo_map_gtt(brw->wm.const_bo);
 344    constants = brw->wm.const_bo->virtual;
 345    for (i = 0; i < brw->wm.prog_data->nr_pull_params; i++) {
 346       constants[i] = convert_param(brw->wm.prog_data->pull_param_convert[i],
 347                                    *brw->wm.prog_data->pull_param[i]);
 348    }
 349    drm_intel_gem_bo_unmap_gtt(brw->wm.const_bo);
 350
 351    brw->state.dirty.brw |= BRW_NEW_WM_CONSTBUF;
 352 }
 353
 354 const struct brw_tracked_state brw_wm_constants = {
 355    .dirty = {
 356       .mesa = (_NEW_PROGRAM_CONSTANTS),
 357       .brw = (BRW_NEW_FRAGMENT_PROGRAM),
 358       .cache = 0
 359    },
 360    .prepare = prepare_wm_constants,
 361 };
 362
 363 /**
 364  * Updates surface / buffer for fragment shader constant buffer, if
 365  * one is required.
 366  *
 367  * This consumes the state updates for the constant buffer, and produces
 368  * BRW_NEW_WM_SURFACES to get picked up by brw_prepare_wm_surfaces for
 369  * inclusion in the binding table.
 370  */
 371 static void upload_wm_constant_surface(struct brw_context *brw )
 372 {
 373    GLuint surf = SURF_INDEX_FRAG_CONST_BUFFER;
 374    struct brw_fragment_program *fp =
 375       (struct brw_fragment_program *) brw->fragment_program;
 376    const struct gl_program_parameter_list *params =
 377       fp->program.Base.Parameters;
 378
 379    /* If there's no constant buffer, then no surface BO is needed to point at
 380     * it.
 381     */
 382    if (brw->wm.const_bo == 0) {
 383       if (brw->wm.surf_bo[surf] != NULL) {
 384          drm_intel_bo_unreference(brw->wm.surf_bo[surf]);
 385          brw->wm.surf_bo[surf] = NULL;
 386          brw->state.dirty.brw |= BRW_NEW_WM_SURFACES;
 387       }
 388       return;
 389    }
 390
 391    brw_create_constant_surface(brw, brw->wm.const_bo, params->NumParameters,
 392                                &brw->wm.surf_bo[surf],
 393                                &brw->wm.surf_offset[surf]);
 394    brw->state.dirty.brw |= BRW_NEW_WM_SURFACES;
 395 }
 396
 397 const struct brw_tracked_state brw_wm_constant_surface = {
 398    .dirty = {
 399       .mesa = 0,
 400       .brw = (BRW_NEW_WM_CONSTBUF |
 401               BRW_NEW_BATCH),
 402       .cache = 0
 403    },
 404    .emit = upload_wm_constant_surface,
 405 };
 406
 407
 408 /**
 409  * Sets up a surface state structure to point at the given region.
 410  * While it is only used for the front/back buffer currently, it should be
 411  * usable for further buffers when doing ARB_draw_buffer support.
 412  */
 413 static void
 414 brw_update_renderbuffer_surface(struct brw_context *brw,
 415                                 struct gl_renderbuffer *rb,
 416                                 unsigned int unit)
 417 {
 418    struct intel_context *intel = &brw->intel;
 419    struct gl_context *ctx = &intel->ctx;
 420    drm_intel_bo *region_bo = NULL;
 421    struct intel_renderbuffer *irb = intel_renderbuffer(rb);
 422    struct intel_region *region = irb ? irb->region : NULL;
 423    struct {
 424       unsigned int surface_type;
 425       unsigned int surface_format;
 426       unsigned int width, height, pitch, cpp;
 427       GLubyte color_mask[4];
 428       GLboolean color_blend;
 429       uint32_t tiling;
 430       uint32_t draw_x;
 431       uint32_t draw_y;
 432    } key;
 433    struct brw_surface_state surf;
 434    void *map;
 435
 436    memset(&key, 0, sizeof(key));
 437
 438    if (region != NULL) {
 439       region_bo = region->buffer;
 440
 441       key.surface_type = BRW_SURFACE_2D;
 442       switch (irb->Base.Format) {
 443       /* XRGB and ARGB are treated the same here because the chips in this
 444        * family cannot render to XRGB targets.  This means that we have to
 445        * mask writes to alpha (ala glColorMask) and reconfigure the alpha
 446        * blending hardware to use GL_ONE (or GL_ZERO) for cases where
 447        * GL_DST_ALPHA (or GL_ONE_MINUS_DST_ALPHA) is used.
 448        */
 449       case MESA_FORMAT_ARGB8888:
 450       case MESA_FORMAT_XRGB8888:
 451          key.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
 452          break;
 453       case MESA_FORMAT_SARGB8:
 454          key.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM_SRGB;
 455          break;
 456       case MESA_FORMAT_RGB565:
 457          key.surface_format = BRW_SURFACEFORMAT_B5G6R5_UNORM;
 458          break;
 459       case MESA_FORMAT_ARGB1555:
 460          key.surface_format = BRW_SURFACEFORMAT_B5G5R5A1_UNORM;
 461          break;
 462       case MESA_FORMAT_ARGB4444:
 463          key.surface_format = BRW_SURFACEFORMAT_B4G4R4A4_UNORM;
 464          break;
 465       case MESA_FORMAT_A8:
 466          key.surface_format = BRW_SURFACEFORMAT_A8_UNORM;
 467          break;
 468       case MESA_FORMAT_R8:
 469          key.surface_format = BRW_SURFACEFORMAT_R8_UNORM;
 470          break;
 471       case MESA_FORMAT_R16:
 472          key.surface_format = BRW_SURFACEFORMAT_R16_UNORM;
 473          break;
 474       case MESA_FORMAT_RG88:
 475          key.surface_format = BRW_SURFACEFORMAT_R8G8_UNORM;
 476          break;
 477       case MESA_FORMAT_RG1616:
 478          key.surface_format = BRW_SURFACEFORMAT_R16G16_UNORM;
 479          break;
 480       default:
 481          _mesa_problem(ctx, "Bad renderbuffer format: %d\n", irb->Base.Format);
 482       }
 483       key.tiling = region->tiling;
 484       key.width = rb->Width;
 485       key.height = rb->Height;
 486       key.pitch = region->pitch;
 487       key.cpp = region->cpp;
 488       key.draw_x = region->draw_x;
 489       key.draw_y = region->draw_y;
 490    } else {
 491       key.surface_type = BRW_SURFACE_NULL;
 492       key.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
 493       key.tiling = I915_TILING_X;
 494       key.width = 1;
 495       key.height = 1;
 496       key.cpp = 4;
 497       key.draw_x = 0;
 498       key.draw_y = 0;
 499    }
 500
 501    if (intel->gen < 6) {
 502       /* _NEW_COLOR */
 503       memcpy(key.color_mask, ctx->Color.ColorMask[unit],
 504              sizeof(key.color_mask));
 505
 506       /* As mentioned above, disable writes to the alpha component when the
 507        * renderbuffer is XRGB.
 508        */
 509       if (ctx->DrawBuffer->Visual.alphaBits == 0)
 510          key.color_mask[3] = GL_FALSE;
 511
 512       key.color_blend = (!ctx->Color._LogicOpEnabled &&
 513                          (ctx->Color.BlendEnabled & (1 << unit)));
 514    }
 515
 516    memset(&surf, 0, sizeof(surf));
 517
 518    surf.ss0.surface_format = key.surface_format;
 519    surf.ss0.surface_type = key.surface_type;
 520    if (key.tiling == I915_TILING_NONE) {
 521       surf.ss1.base_addr = (key.draw_x + key.draw_y * key.pitch) * key.cpp;
 522    } else {
 523       uint32_t tile_base, tile_x, tile_y;
 524       uint32_t pitch = key.pitch * key.cpp;
 525
 526       if (key.tiling == I915_TILING_X) {
 527          tile_x = key.draw_x % (512 / key.cpp);
 528          tile_y = key.draw_y % 8;
 529          tile_base = ((key.draw_y / 8) * (8 * pitch));
 530          tile_base += (key.draw_x - tile_x) / (512 / key.cpp) * 4096;
 531       } else {
 532          /* Y */
 533          tile_x = key.draw_x % (128 / key.cpp);
 534          tile_y = key.draw_y % 32;
 535          tile_base = ((key.draw_y / 32) * (32 * pitch));
 536          tile_base += (key.draw_x - tile_x) / (128 / key.cpp) * 4096;
 537       }
 538       assert(brw->has_surface_tile_offset || (tile_x == 0 && tile_y == 0));
 539       assert(tile_x % 4 == 0);
 540       assert(tile_y % 2 == 0);
 541       /* Note that the low bits of these fields are missing, so
 542        * there's the possibility of getting in trouble.
 543        */
 544       surf.ss1.base_addr = tile_base;
 545       surf.ss5.x_offset = tile_x / 4;
 546       surf.ss5.y_offset = tile_y / 2;
 547    }
 548    if (region_bo != NULL)
 549       surf.ss1.base_addr += region_bo->offset; /* reloc */
 550
 551    surf.ss2.width = key.width - 1;
 552    surf.ss2.height = key.height - 1;
 553    brw_set_surface_tiling(&surf, key.tiling);
 554    surf.ss3.pitch = (key.pitch * key.cpp) - 1;
 555
 556    if (intel->gen < 6) {
 557       /* _NEW_COLOR */
 558       surf.ss0.color_blend = key.color_blend;
 559       surf.ss0.writedisable_red =   !key.color_mask[0];
 560       surf.ss0.writedisable_green = !key.color_mask[1];
 561       surf.ss0.writedisable_blue =  !key.color_mask[2];
 562       surf.ss0.writedisable_alpha = !key.color_mask[3];
 563    }
 564
 565    map = brw_state_batch(brw, sizeof(surf), 32,
 566                          &brw->wm.surf_bo[unit],
 567                          &brw->wm.surf_offset[unit]);
 568    memcpy(map, &surf, sizeof(surf));
 569
 570    if (region_bo != NULL) {
 571       drm_intel_bo_emit_reloc(brw->wm.surf_bo[unit],
 572                               brw->wm.surf_offset[unit] +
 573                               offsetof(struct brw_surface_state, ss1),
 574                               region_bo,
 575                               surf.ss1.base_addr - region_bo->offset,
 576                               I915_GEM_DOMAIN_RENDER,
 577                               I915_GEM_DOMAIN_RENDER);
 578    }
 579 }
 580
 581 static void
 582 prepare_wm_surfaces(struct brw_context *brw)
 583 {
 584    struct gl_context *ctx = &brw->intel.ctx;
 585    int i;
 586    int nr_surfaces = 0;
 587
 588    if (ctx->DrawBuffer->_NumColorDrawBuffers >= 1) {
 589       for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) {
 590          struct gl_renderbuffer *rb = ctx->DrawBuffer->_ColorDrawBuffers[i];
 591          struct intel_renderbuffer *irb = intel_renderbuffer(rb);
 592          struct intel_region *region = irb ? irb->region : NULL;
 593
 594          brw_add_validated_bo(brw, region->buffer);
 595          nr_surfaces = SURF_INDEX_DRAW(i) + 1;
 596       }
 597    }
 598
 599    if (brw->wm.const_bo) {
 600       brw_add_validated_bo(brw, brw->wm.const_bo);
 601       nr_surfaces = SURF_INDEX_FRAG_CONST_BUFFER + 1;
 602    }
 603
 604    for (i = 0; i < BRW_MAX_TEX_UNIT; i++) {
 605       const struct gl_texture_unit *texUnit = &ctx->Texture.Unit[i];
 606       struct gl_texture_object *tObj = texUnit->_Current;
 607       struct intel_texture_object *intelObj = intel_texture_object(tObj);
 608
 609       if (texUnit->_ReallyEnabled) {
 610          brw_add_validated_bo(brw, intelObj->mt->region->buffer);
 611          nr_surfaces = SURF_INDEX_TEXTURE(i) + 1;
 612       }
 613    }
 614
 615    /* Have to update this in our prepare, since the unit's prepare
 616     * relies on it.
 617     */
 618    if (brw->wm.nr_surfaces != nr_surfaces) {
 619       brw->wm.nr_surfaces = nr_surfaces;
 620       brw->state.dirty.brw |= BRW_NEW_NR_WM_SURFACES;
 621    }
 622 }
 623
 624 /**
 625  * Constructs the set of surface state objects pointed to by the
 626  * binding table.
 627  */
 628 static void
 629 upload_wm_surfaces(struct brw_context *brw)
 630 {
 631    struct gl_context *ctx = &brw->intel.ctx;
 632    GLuint i;
 633
 634    /* _NEW_BUFFERS | _NEW_COLOR */
 635    /* Update surfaces for drawing buffers */
 636    if (ctx->DrawBuffer->_NumColorDrawBuffers >= 1) {
 637       for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) {
 638          brw_update_renderbuffer_surface(brw,
 639                                          ctx->DrawBuffer->_ColorDrawBuffers[i],
 640                                          i);
 641       }
 642    } else {
 643       brw_update_renderbuffer_surface(brw, NULL, 0);
 644    }
 645
 646    /* Update surfaces for textures */
 647    for (i = 0; i < BRW_MAX_TEX_UNIT; i++) {
 648       const struct gl_texture_unit *texUnit = &ctx->Texture.Unit[i];
 649       const GLuint surf = SURF_INDEX_TEXTURE(i);
 650
 651       /* _NEW_TEXTURE */
 652       if (texUnit->_ReallyEnabled) {
 653          brw_update_texture_surface(ctx, i);
 654       } else {
 655          drm_intel_bo_unreference(brw->wm.surf_bo[surf]);
 656          brw->wm.surf_bo[surf] = NULL;
 657       }
 658    }
 659
 660    brw->state.dirty.brw |= BRW_NEW_WM_SURFACES;
 661 }
 662
 663 const struct brw_tracked_state brw_wm_surfaces = {
 664    .dirty = {
 665       .mesa = (_NEW_COLOR |
 666                _NEW_TEXTURE |
 667                _NEW_BUFFERS),
 668       .brw = (BRW_NEW_BATCH),
 669       .cache = 0
 670    },
 671    .prepare = prepare_wm_surfaces,
 672    .emit = upload_wm_surfaces,
 673 };
 674
 675 /**
 676  * Constructs the binding table for the WM surface state, which maps unit
 677  * numbers to surface state objects.
 678  */
 679 static void
 680 brw_wm_upload_binding_table(struct brw_context *brw)
 681 {
 682    uint32_t *bind;
 683    int i;
 684
 685    /* Might want to calculate nr_surfaces first, to avoid taking up so much
 686     * space for the binding table.
 687     */
 688    bind = brw_state_batch(brw, sizeof(uint32_t) * BRW_WM_MAX_SURF,
 689                           32, &brw->wm.bind_bo, &brw->wm.bind_bo_offset);
 690
 691    for (i = 0; i < BRW_WM_MAX_SURF; i++) {
 692       /* BRW_NEW_WM_SURFACES */
 693       bind[i] = brw->wm.surf_offset[i];
 694       if (brw->wm.surf_bo[i]) {
 695          bind[i] = brw->wm.surf_offset[i];
 696       } else {
 697          bind[i] = 0;
 698       }
 699    }
 700
 701    brw->state.dirty.brw |= BRW_NEW_BINDING_TABLE;
 702 }
 703
 704 const struct brw_tracked_state brw_wm_binding_table = {
 705    .dirty = {
 706       .mesa = 0,
 707       .brw = (BRW_NEW_BATCH |
 708               BRW_NEW_WM_SURFACES),
 709       .cache = 0
 710    },
 711    .emit = brw_wm_upload_binding_table,
 712 };