2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
33 #include "main/context.h"
34 #include "main/blend.h"
35 #include "main/mtypes.h"
36 #include "main/samplerobj.h"
37 #include "main/shaderimage.h"
38 #include "main/teximage.h"
39 #include "program/prog_parameter.h"
40 #include "program/prog_instruction.h"
41 #include "main/framebuffer.h"
45 #include "intel_mipmap_tree.h"
46 #include "intel_batchbuffer.h"
47 #include "intel_tex.h"
48 #include "intel_fbo.h"
49 #include "intel_buffer_objects.h"
51 #include "brw_context.h"
52 #include "brw_state.h"
53 #include "brw_defines.h"
56 struct surface_state_info
{
58 unsigned ss_align
; /* Required alignment of RENDER_SURFACE_STATE in bytes */
60 unsigned aux_reloc_dw
;
65 static const struct surface_state_info surface_state_infos
[] = {
69 [7] = {8, 32, 1, 6, GEN7_MOCS_L3
, GEN7_MOCS_L3
},
70 [8] = {13, 64, 8, 10, BDW_MOCS_WB
, BDW_MOCS_PTE
},
71 [9] = {16, 64, 8, 10, SKL_MOCS_WB
, SKL_MOCS_PTE
},
75 brw_emit_surface_state(struct brw_context
*brw
,
76 struct intel_mipmap_tree
*mt
,
77 const struct isl_view
*view
,
78 uint32_t mocs
, bool for_gather
,
79 uint32_t *surf_offset
, int surf_index
,
80 unsigned read_domains
, unsigned write_domains
)
82 const struct surface_state_info ss_info
= surface_state_infos
[brw
->gen
];
85 intel_miptree_get_isl_surf(brw
, mt
, &surf
);
87 union isl_color_value clear_color
= { .u32
= { 0, 0, 0, 0 } };
89 struct isl_surf
*aux_surf
= NULL
, aux_surf_s
;
90 uint64_t aux_offset
= 0;
91 enum isl_aux_usage aux_usage
= ISL_AUX_USAGE_NONE
;
93 ((view
->usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
) ||
94 mt
->fast_clear_state
!= INTEL_FAST_CLEAR_STATE_RESOLVED
)) {
95 intel_miptree_get_aux_isl_surf(brw
, mt
, &aux_surf_s
, &aux_usage
);
96 aux_surf
= &aux_surf_s
;
97 assert(mt
->mcs_mt
->offset
== 0);
98 aux_offset
= mt
->mcs_mt
->bo
->offset64
;
100 /* We only really need a clear color if we also have an auxiliary
101 * surfacae. Without one, it does nothing.
103 clear_color
= intel_miptree_get_isl_clear_color(brw
, mt
);
106 uint32_t *dw
= __brw_state_batch(brw
, AUB_TRACE_SURFACE_STATE
,
107 ss_info
.num_dwords
* 4, ss_info
.ss_align
,
108 surf_index
, surf_offset
);
110 isl_surf_fill_state(&brw
->isl_dev
, dw
, .surf
= &surf
, .view
= view
,
111 .address
= mt
->bo
->offset64
+ mt
->offset
,
112 .aux_surf
= aux_surf
, .aux_usage
= aux_usage
,
113 .aux_address
= aux_offset
,
114 .mocs
= mocs
, .clear_color
= clear_color
);
116 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
117 *surf_offset
+ 4 * ss_info
.reloc_dw
,
119 read_domains
, write_domains
);
122 /* On gen7 and prior, the upper 20 bits of surface state DWORD 6 are the
123 * upper 20 bits of the GPU address of the MCS buffer; the lower 12 bits
124 * contain other control information. Since buffer addresses are always
125 * on 4k boundaries (and thus have their lower 12 bits zero), we can use
126 * an ordinary reloc to do the necessary address translation.
128 assert((aux_offset
& 0xfff) == 0);
129 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
130 *surf_offset
+ 4 * ss_info
.aux_reloc_dw
,
131 mt
->mcs_mt
->bo
, dw
[ss_info
.aux_reloc_dw
] & 0xfff,
132 read_domains
, write_domains
);
137 brw_update_renderbuffer_surface(struct brw_context
*brw
,
138 struct gl_renderbuffer
*rb
,
139 bool layered
, unsigned unit
/* unused */,
142 struct gl_context
*ctx
= &brw
->ctx
;
143 struct intel_renderbuffer
*irb
= intel_renderbuffer(rb
);
144 struct intel_mipmap_tree
*mt
= irb
->mt
;
146 assert(brw_render_target_supported(brw
, rb
));
147 intel_miptree_used_for_rendering(mt
);
149 mesa_format rb_format
= _mesa_get_render_format(ctx
, intel_rb_format(irb
));
150 if (unlikely(!brw
->format_supported_as_render_target
[rb_format
])) {
151 _mesa_problem(ctx
, "%s: renderbuffer format %s unsupported\n",
152 __func__
, _mesa_get_format_name(rb_format
));
155 const unsigned layer_multiplier
=
156 (irb
->mt
->msaa_layout
== INTEL_MSAA_LAYOUT_UMS
||
157 irb
->mt
->msaa_layout
== INTEL_MSAA_LAYOUT_CMS
) ?
158 MAX2(irb
->mt
->num_samples
, 1) : 1;
160 struct isl_view view
= {
161 .format
= brw
->render_target_format
[rb_format
],
162 .base_level
= irb
->mt_level
- irb
->mt
->first_level
,
164 .base_array_layer
= irb
->mt_layer
/ layer_multiplier
,
165 .array_len
= MAX2(irb
->layer_count
, 1),
167 ISL_CHANNEL_SELECT_RED
,
168 ISL_CHANNEL_SELECT_GREEN
,
169 ISL_CHANNEL_SELECT_BLUE
,
170 ISL_CHANNEL_SELECT_ALPHA
,
172 .usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
,
176 brw_emit_surface_state(brw
, mt
, &view
,
177 surface_state_infos
[brw
->gen
].rb_mocs
, false,
179 I915_GEM_DOMAIN_RENDER
,
180 I915_GEM_DOMAIN_RENDER
);
185 translate_tex_target(GLenum target
)
189 case GL_TEXTURE_1D_ARRAY_EXT
:
190 return BRW_SURFACE_1D
;
192 case GL_TEXTURE_RECTANGLE_NV
:
193 return BRW_SURFACE_2D
;
196 case GL_TEXTURE_2D_ARRAY_EXT
:
197 case GL_TEXTURE_EXTERNAL_OES
:
198 case GL_TEXTURE_2D_MULTISAMPLE
:
199 case GL_TEXTURE_2D_MULTISAMPLE_ARRAY
:
200 return BRW_SURFACE_2D
;
203 return BRW_SURFACE_3D
;
205 case GL_TEXTURE_CUBE_MAP
:
206 case GL_TEXTURE_CUBE_MAP_ARRAY
:
207 return BRW_SURFACE_CUBE
;
210 unreachable("not reached");
215 brw_get_surface_tiling_bits(uint32_t tiling
)
219 return BRW_SURFACE_TILED
;
221 return BRW_SURFACE_TILED
| BRW_SURFACE_TILED_Y
;
229 brw_get_surface_num_multisamples(unsigned num_samples
)
232 return BRW_SURFACE_MULTISAMPLECOUNT_4
;
234 return BRW_SURFACE_MULTISAMPLECOUNT_1
;
238 * Compute the combination of DEPTH_TEXTURE_MODE and EXT_texture_swizzle
242 brw_get_texture_swizzle(const struct gl_context
*ctx
,
243 const struct gl_texture_object
*t
)
245 const struct gl_texture_image
*img
= t
->Image
[0][t
->BaseLevel
];
247 int swizzles
[SWIZZLE_NIL
+ 1] = {
257 if (img
->_BaseFormat
== GL_DEPTH_COMPONENT
||
258 img
->_BaseFormat
== GL_DEPTH_STENCIL
) {
259 GLenum depth_mode
= t
->DepthMode
;
261 /* In ES 3.0, DEPTH_TEXTURE_MODE is expected to be GL_RED for textures
262 * with depth component data specified with a sized internal format.
263 * Otherwise, it's left at the old default, GL_LUMINANCE.
265 if (_mesa_is_gles3(ctx
) &&
266 img
->InternalFormat
!= GL_DEPTH_COMPONENT
&&
267 img
->InternalFormat
!= GL_DEPTH_STENCIL
) {
271 switch (depth_mode
) {
273 swizzles
[0] = SWIZZLE_ZERO
;
274 swizzles
[1] = SWIZZLE_ZERO
;
275 swizzles
[2] = SWIZZLE_ZERO
;
276 swizzles
[3] = SWIZZLE_X
;
279 swizzles
[0] = SWIZZLE_X
;
280 swizzles
[1] = SWIZZLE_X
;
281 swizzles
[2] = SWIZZLE_X
;
282 swizzles
[3] = SWIZZLE_ONE
;
285 swizzles
[0] = SWIZZLE_X
;
286 swizzles
[1] = SWIZZLE_X
;
287 swizzles
[2] = SWIZZLE_X
;
288 swizzles
[3] = SWIZZLE_X
;
291 swizzles
[0] = SWIZZLE_X
;
292 swizzles
[1] = SWIZZLE_ZERO
;
293 swizzles
[2] = SWIZZLE_ZERO
;
294 swizzles
[3] = SWIZZLE_ONE
;
299 GLenum datatype
= _mesa_get_format_datatype(img
->TexFormat
);
301 /* If the texture's format is alpha-only, force R, G, and B to
302 * 0.0. Similarly, if the texture's format has no alpha channel,
303 * force the alpha value read to 1.0. This allows for the
304 * implementation to use an RGBA texture for any of these formats
305 * without leaking any unexpected values.
307 switch (img
->_BaseFormat
) {
309 swizzles
[0] = SWIZZLE_ZERO
;
310 swizzles
[1] = SWIZZLE_ZERO
;
311 swizzles
[2] = SWIZZLE_ZERO
;
314 if (t
->_IsIntegerFormat
|| datatype
== GL_SIGNED_NORMALIZED
) {
315 swizzles
[0] = SWIZZLE_X
;
316 swizzles
[1] = SWIZZLE_X
;
317 swizzles
[2] = SWIZZLE_X
;
318 swizzles
[3] = SWIZZLE_ONE
;
321 case GL_LUMINANCE_ALPHA
:
322 if (datatype
== GL_SIGNED_NORMALIZED
) {
323 swizzles
[0] = SWIZZLE_X
;
324 swizzles
[1] = SWIZZLE_X
;
325 swizzles
[2] = SWIZZLE_X
;
326 swizzles
[3] = SWIZZLE_W
;
330 if (datatype
== GL_SIGNED_NORMALIZED
) {
331 swizzles
[0] = SWIZZLE_X
;
332 swizzles
[1] = SWIZZLE_X
;
333 swizzles
[2] = SWIZZLE_X
;
334 swizzles
[3] = SWIZZLE_X
;
340 if (_mesa_get_format_bits(img
->TexFormat
, GL_ALPHA_BITS
) > 0)
341 swizzles
[3] = SWIZZLE_ONE
;
345 return MAKE_SWIZZLE4(swizzles
[GET_SWZ(t
->_Swizzle
, 0)],
346 swizzles
[GET_SWZ(t
->_Swizzle
, 1)],
347 swizzles
[GET_SWZ(t
->_Swizzle
, 2)],
348 swizzles
[GET_SWZ(t
->_Swizzle
, 3)]);
352 * Convert an swizzle enumeration (i.e. SWIZZLE_X) to one of the Gen7.5+
353 * "Shader Channel Select" enumerations (i.e. HSW_SCS_RED). The mappings are
355 * SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_W, SWIZZLE_ZERO, SWIZZLE_ONE
358 * SCS_RED, SCS_GREEN, SCS_BLUE, SCS_ALPHA, SCS_ZERO, SCS_ONE
360 * which is simply adding 4 then modding by 8 (or anding with 7).
362 * We then may need to apply workarounds for textureGather hardware bugs.
365 swizzle_to_scs(GLenum swizzle
, bool need_green_to_blue
)
367 unsigned scs
= (swizzle
+ 4) & 7;
369 return (need_green_to_blue
&& scs
== HSW_SCS_GREEN
) ? HSW_SCS_BLUE
: scs
;
373 brw_update_texture_surface(struct gl_context
*ctx
,
375 uint32_t *surf_offset
,
379 struct brw_context
*brw
= brw_context(ctx
);
380 struct gl_texture_object
*obj
= ctx
->Texture
.Unit
[unit
]._Current
;
382 if (obj
->Target
== GL_TEXTURE_BUFFER
) {
383 brw_update_buffer_texture_surface(ctx
, unit
, surf_offset
);
386 struct intel_texture_object
*intel_obj
= intel_texture_object(obj
);
387 struct intel_mipmap_tree
*mt
= intel_obj
->mt
;
390 if (mt
->plane
[plane
- 1] == NULL
)
392 mt
= mt
->plane
[plane
- 1];
395 struct gl_sampler_object
*sampler
= _mesa_get_samplerobj(ctx
, unit
);
396 /* If this is a view with restricted NumLayers, then our effective depth
397 * is not just the miptree depth.
399 const unsigned mt_num_layers
=
400 mt
->logical_depth0
* (_mesa_is_cube_map_texture(mt
->target
) ? 6 : 1);
401 const unsigned view_num_layers
=
402 (obj
->Immutable
&& obj
->Target
!= GL_TEXTURE_3D
) ? obj
->NumLayers
:
405 /* Handling GL_ALPHA as a surface format override breaks 1.30+ style
406 * texturing functions that return a float, as our code generation always
407 * selects the .x channel (which would always be 0).
409 struct gl_texture_image
*firstImage
= obj
->Image
[0][obj
->BaseLevel
];
410 const bool alpha_depth
= obj
->DepthMode
== GL_ALPHA
&&
411 (firstImage
->_BaseFormat
== GL_DEPTH_COMPONENT
||
412 firstImage
->_BaseFormat
== GL_DEPTH_STENCIL
);
413 const unsigned swizzle
= (unlikely(alpha_depth
) ? SWIZZLE_XYZW
:
414 brw_get_texture_swizzle(&brw
->ctx
, obj
));
416 mesa_format mesa_fmt
= plane
== 0 ? intel_obj
->_Format
: mt
->format
;
417 unsigned format
= translate_tex_format(brw
, mesa_fmt
,
418 sampler
->sRGBDecode
);
420 /* Implement gen6 and gen7 gather work-around */
421 bool need_green_to_blue
= false;
423 if (brw
->gen
== 7 && format
== BRW_SURFACEFORMAT_R32G32_FLOAT
) {
424 format
= BRW_SURFACEFORMAT_R32G32_FLOAT_LD
;
425 need_green_to_blue
= brw
->is_haswell
;
426 } else if (brw
->gen
== 6) {
427 /* Sandybridge's gather4 message is broken for integer formats.
428 * To work around this, we pretend the surface is UNORM for
429 * 8 or 16-bit formats, and emit shader instructions to recover
430 * the real INT/UINT value. For 32-bit formats, we pretend
431 * the surface is FLOAT, and simply reinterpret the resulting
435 case BRW_SURFACEFORMAT_R8_SINT
:
436 case BRW_SURFACEFORMAT_R8_UINT
:
437 format
= BRW_SURFACEFORMAT_R8_UNORM
;
440 case BRW_SURFACEFORMAT_R16_SINT
:
441 case BRW_SURFACEFORMAT_R16_UINT
:
442 format
= BRW_SURFACEFORMAT_R16_UNORM
;
445 case BRW_SURFACEFORMAT_R32_SINT
:
446 case BRW_SURFACEFORMAT_R32_UINT
:
447 format
= BRW_SURFACEFORMAT_R32_FLOAT
;
456 if (obj
->StencilSampling
&& firstImage
->_BaseFormat
== GL_DEPTH_STENCIL
) {
457 assert(brw
->gen
>= 8);
459 format
= BRW_SURFACEFORMAT_R8_UINT
;
462 const int surf_index
= surf_offset
- &brw
->wm
.base
.surf_offset
[0];
464 struct isl_view view
= {
466 .base_level
= obj
->MinLevel
+ obj
->BaseLevel
,
467 .levels
= intel_obj
->_MaxLevel
- obj
->BaseLevel
+ 1,
468 .base_array_layer
= obj
->MinLayer
,
469 .array_len
= view_num_layers
,
471 swizzle_to_scs(GET_SWZ(swizzle
, 0), need_green_to_blue
),
472 swizzle_to_scs(GET_SWZ(swizzle
, 1), need_green_to_blue
),
473 swizzle_to_scs(GET_SWZ(swizzle
, 2), need_green_to_blue
),
474 swizzle_to_scs(GET_SWZ(swizzle
, 3), need_green_to_blue
),
476 .usage
= ISL_SURF_USAGE_TEXTURE_BIT
,
479 if (obj
->Target
== GL_TEXTURE_CUBE_MAP
||
480 obj
->Target
== GL_TEXTURE_CUBE_MAP_ARRAY
)
481 view
.usage
|= ISL_SURF_USAGE_CUBE_BIT
;
483 brw_emit_surface_state(brw
, mt
, &view
,
484 surface_state_infos
[brw
->gen
].tex_mocs
, for_gather
,
485 surf_offset
, surf_index
,
486 I915_GEM_DOMAIN_SAMPLER
, 0);
491 brw_emit_buffer_surface_state(struct brw_context
*brw
,
492 uint32_t *out_offset
,
494 unsigned buffer_offset
,
495 unsigned surface_format
,
496 unsigned buffer_size
,
500 const struct surface_state_info ss_info
= surface_state_infos
[brw
->gen
];
502 uint32_t *dw
= brw_state_batch(brw
, AUB_TRACE_SURFACE_STATE
,
503 ss_info
.num_dwords
* 4, ss_info
.ss_align
,
506 isl_buffer_fill_state(&brw
->isl_dev
, dw
,
507 .address
= (bo
? bo
->offset64
: 0) + buffer_offset
,
509 .format
= surface_format
,
511 .mocs
= ss_info
.tex_mocs
);
514 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
515 *out_offset
+ 4 * ss_info
.reloc_dw
,
517 I915_GEM_DOMAIN_SAMPLER
,
518 (rw
? I915_GEM_DOMAIN_SAMPLER
: 0));
523 brw_update_buffer_texture_surface(struct gl_context
*ctx
,
525 uint32_t *surf_offset
)
527 struct brw_context
*brw
= brw_context(ctx
);
528 struct gl_texture_object
*tObj
= ctx
->Texture
.Unit
[unit
]._Current
;
529 struct intel_buffer_object
*intel_obj
=
530 intel_buffer_object(tObj
->BufferObject
);
531 uint32_t size
= tObj
->BufferSize
;
532 drm_intel_bo
*bo
= NULL
;
533 mesa_format format
= tObj
->_BufferObjectFormat
;
534 uint32_t brw_format
= brw_format_for_mesa_format(format
);
535 int texel_size
= _mesa_get_format_bytes(format
);
538 size
= MIN2(size
, intel_obj
->Base
.Size
);
539 bo
= intel_bufferobj_buffer(brw
, intel_obj
, tObj
->BufferOffset
, size
);
542 if (brw_format
== 0 && format
!= MESA_FORMAT_RGBA_FLOAT32
) {
543 _mesa_problem(NULL
, "bad format %s for texture buffer\n",
544 _mesa_get_format_name(format
));
547 brw_emit_buffer_surface_state(brw
, surf_offset
, bo
,
556 * Create the constant buffer surface. Vertex/fragment shader constants will be
557 * read from this buffer with Data Port Read instructions/messages.
560 brw_create_constant_surface(struct brw_context
*brw
,
564 uint32_t *out_offset
)
566 brw_emit_buffer_surface_state(brw
, out_offset
, bo
, offset
,
567 BRW_SURFACEFORMAT_R32G32B32A32_FLOAT
,
572 * Create the buffer surface. Shader buffer variables will be
573 * read from / write to this buffer with Data Port Read/Write
574 * instructions/messages.
577 brw_create_buffer_surface(struct brw_context
*brw
,
581 uint32_t *out_offset
)
583 /* Use a raw surface so we can reuse existing untyped read/write/atomic
584 * messages. We need these specifically for the fragment shader since they
585 * include a pixel mask header that we need to ensure correct behavior
586 * with helper invocations, which cannot write to the buffer.
588 brw_emit_buffer_surface_state(brw
, out_offset
, bo
, offset
,
589 BRW_SURFACEFORMAT_RAW
,
594 * Set up a binding table entry for use by stream output logic (transform
597 * buffer_size_minus_1 must be less than BRW_MAX_NUM_BUFFER_ENTRIES.
600 brw_update_sol_surface(struct brw_context
*brw
,
601 struct gl_buffer_object
*buffer_obj
,
602 uint32_t *out_offset
, unsigned num_vector_components
,
603 unsigned stride_dwords
, unsigned offset_dwords
)
605 struct intel_buffer_object
*intel_bo
= intel_buffer_object(buffer_obj
);
606 uint32_t offset_bytes
= 4 * offset_dwords
;
607 drm_intel_bo
*bo
= intel_bufferobj_buffer(brw
, intel_bo
,
609 buffer_obj
->Size
- offset_bytes
);
610 uint32_t *surf
= brw_state_batch(brw
, AUB_TRACE_SURFACE_STATE
, 6 * 4, 32,
612 uint32_t pitch_minus_1
= 4*stride_dwords
- 1;
613 size_t size_dwords
= buffer_obj
->Size
/ 4;
614 uint32_t buffer_size_minus_1
, width
, height
, depth
, surface_format
;
616 /* FIXME: can we rely on core Mesa to ensure that the buffer isn't
617 * too big to map using a single binding table entry?
619 assert((size_dwords
- offset_dwords
) / stride_dwords
620 <= BRW_MAX_NUM_BUFFER_ENTRIES
);
622 if (size_dwords
> offset_dwords
+ num_vector_components
) {
623 /* There is room for at least 1 transform feedback output in the buffer.
624 * Compute the number of additional transform feedback outputs the
625 * buffer has room for.
627 buffer_size_minus_1
=
628 (size_dwords
- offset_dwords
- num_vector_components
) / stride_dwords
;
630 /* There isn't even room for a single transform feedback output in the
631 * buffer. We can't configure the binding table entry to prevent output
632 * entirely; we'll have to rely on the geometry shader to detect
633 * overflow. But to minimize the damage in case of a bug, set up the
634 * binding table entry to just allow a single output.
636 buffer_size_minus_1
= 0;
638 width
= buffer_size_minus_1
& 0x7f;
639 height
= (buffer_size_minus_1
& 0xfff80) >> 7;
640 depth
= (buffer_size_minus_1
& 0x7f00000) >> 20;
642 switch (num_vector_components
) {
644 surface_format
= BRW_SURFACEFORMAT_R32_FLOAT
;
647 surface_format
= BRW_SURFACEFORMAT_R32G32_FLOAT
;
650 surface_format
= BRW_SURFACEFORMAT_R32G32B32_FLOAT
;
653 surface_format
= BRW_SURFACEFORMAT_R32G32B32A32_FLOAT
;
656 unreachable("Invalid vector size for transform feedback output");
659 surf
[0] = BRW_SURFACE_BUFFER
<< BRW_SURFACE_TYPE_SHIFT
|
660 BRW_SURFACE_MIPMAPLAYOUT_BELOW
<< BRW_SURFACE_MIPLAYOUT_SHIFT
|
661 surface_format
<< BRW_SURFACE_FORMAT_SHIFT
|
662 BRW_SURFACE_RC_READ_WRITE
;
663 surf
[1] = bo
->offset64
+ offset_bytes
; /* reloc */
664 surf
[2] = (width
<< BRW_SURFACE_WIDTH_SHIFT
|
665 height
<< BRW_SURFACE_HEIGHT_SHIFT
);
666 surf
[3] = (depth
<< BRW_SURFACE_DEPTH_SHIFT
|
667 pitch_minus_1
<< BRW_SURFACE_PITCH_SHIFT
);
671 /* Emit relocation to surface contents. */
672 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
675 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
);
678 /* Creates a new WM constant buffer reflecting the current fragment program's
679 * constants, if needed by the fragment program.
681 * Otherwise, constants go through the CURBEs using the brw_constant_buffer
685 brw_upload_wm_pull_constants(struct brw_context
*brw
)
687 struct brw_stage_state
*stage_state
= &brw
->wm
.base
;
688 /* BRW_NEW_FRAGMENT_PROGRAM */
689 struct brw_fragment_program
*fp
=
690 (struct brw_fragment_program
*) brw
->fragment_program
;
691 /* BRW_NEW_FS_PROG_DATA */
692 struct brw_stage_prog_data
*prog_data
= &brw
->wm
.prog_data
->base
;
694 /* _NEW_PROGRAM_CONSTANTS */
695 brw_upload_pull_constants(brw
, BRW_NEW_SURFACES
, &fp
->program
.Base
,
696 stage_state
, prog_data
);
699 const struct brw_tracked_state brw_wm_pull_constants
= {
701 .mesa
= _NEW_PROGRAM_CONSTANTS
,
702 .brw
= BRW_NEW_BATCH
|
704 BRW_NEW_FRAGMENT_PROGRAM
|
705 BRW_NEW_FS_PROG_DATA
,
707 .emit
= brw_upload_wm_pull_constants
,
711 * Creates a null renderbuffer surface.
713 * This is used when the shader doesn't write to any color output. An FB
714 * write to target 0 will still be emitted, because that's how the thread is
715 * terminated (and computed depth is returned), so we need to have the
716 * hardware discard the target 0 color output..
719 brw_emit_null_surface_state(struct brw_context
*brw
,
723 uint32_t *out_offset
)
725 /* From the Sandy bridge PRM, Vol4 Part1 p71 (Surface Type: Programming
728 * A null surface will be used in instances where an actual surface is
729 * not bound. When a write message is generated to a null surface, no
730 * actual surface is written to. When a read message (including any
731 * sampling engine message) is generated to a null surface, the result
732 * is all zeros. Note that a null surface type is allowed to be used
733 * with all messages, even if it is not specificially indicated as
734 * supported. All of the remaining fields in surface state are ignored
735 * for null surfaces, with the following exceptions:
737 * - [DevSNB+]: Width, Height, Depth, and LOD fields must match the
738 * depth buffer’s corresponding state for all render target surfaces,
741 * - Surface Format must be R8G8B8A8_UNORM.
743 unsigned surface_type
= BRW_SURFACE_NULL
;
744 drm_intel_bo
*bo
= NULL
;
745 unsigned pitch_minus_1
= 0;
746 uint32_t multisampling_state
= 0;
747 uint32_t *surf
= brw_state_batch(brw
, AUB_TRACE_SURFACE_STATE
, 6 * 4, 32,
751 /* On Gen6, null render targets seem to cause GPU hangs when
752 * multisampling. So work around this problem by rendering into dummy
755 * To decrease the amount of memory needed by the workaround buffer, we
756 * set its pitch to 128 bytes (the width of a Y tile). This means that
757 * the amount of memory needed for the workaround buffer is
758 * (width_in_tiles + height_in_tiles - 1) tiles.
760 * Note that since the workaround buffer will be interpreted by the
761 * hardware as an interleaved multisampled buffer, we need to compute
762 * width_in_tiles and height_in_tiles by dividing the width and height
763 * by 16 rather than the normal Y-tile size of 32.
765 unsigned width_in_tiles
= ALIGN(width
, 16) / 16;
766 unsigned height_in_tiles
= ALIGN(height
, 16) / 16;
767 unsigned size_needed
= (width_in_tiles
+ height_in_tiles
- 1) * 4096;
768 brw_get_scratch_bo(brw
, &brw
->wm
.multisampled_null_render_target_bo
,
770 bo
= brw
->wm
.multisampled_null_render_target_bo
;
771 surface_type
= BRW_SURFACE_2D
;
773 multisampling_state
= brw_get_surface_num_multisamples(samples
);
776 surf
[0] = (surface_type
<< BRW_SURFACE_TYPE_SHIFT
|
777 BRW_SURFACEFORMAT_B8G8R8A8_UNORM
<< BRW_SURFACE_FORMAT_SHIFT
);
779 surf
[0] |= (1 << BRW_SURFACE_WRITEDISABLE_R_SHIFT
|
780 1 << BRW_SURFACE_WRITEDISABLE_G_SHIFT
|
781 1 << BRW_SURFACE_WRITEDISABLE_B_SHIFT
|
782 1 << BRW_SURFACE_WRITEDISABLE_A_SHIFT
);
784 surf
[1] = bo
? bo
->offset64
: 0;
785 surf
[2] = ((width
- 1) << BRW_SURFACE_WIDTH_SHIFT
|
786 (height
- 1) << BRW_SURFACE_HEIGHT_SHIFT
);
788 /* From Sandy bridge PRM, Vol4 Part1 p82 (Tiled Surface: Programming
791 * If Surface Type is SURFTYPE_NULL, this field must be TRUE
793 surf
[3] = (BRW_SURFACE_TILED
| BRW_SURFACE_TILED_Y
|
794 pitch_minus_1
<< BRW_SURFACE_PITCH_SHIFT
);
795 surf
[4] = multisampling_state
;
799 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
802 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
);
807 * Sets up a surface state structure to point at the given region.
808 * While it is only used for the front/back buffer currently, it should be
809 * usable for further buffers when doing ARB_draw_buffer support.
812 gen4_update_renderbuffer_surface(struct brw_context
*brw
,
813 struct gl_renderbuffer
*rb
,
814 bool layered
, unsigned unit
,
817 struct gl_context
*ctx
= &brw
->ctx
;
818 struct intel_renderbuffer
*irb
= intel_renderbuffer(rb
);
819 struct intel_mipmap_tree
*mt
= irb
->mt
;
821 uint32_t tile_x
, tile_y
;
825 mesa_format rb_format
= _mesa_get_render_format(ctx
, intel_rb_format(irb
));
826 /* BRW_NEW_FS_PROG_DATA */
830 if (rb
->TexImage
&& !brw
->has_surface_tile_offset
) {
831 intel_renderbuffer_get_tile_offsets(irb
, &tile_x
, &tile_y
);
833 if (tile_x
!= 0 || tile_y
!= 0) {
834 /* Original gen4 hardware couldn't draw to a non-tile-aligned
835 * destination in a miptree unless you actually setup your renderbuffer
836 * as a miptree and used the fragile lod/array_index/etc. controls to
837 * select the image. So, instead, we just make a new single-level
838 * miptree and render into that.
840 intel_renderbuffer_move_to_temp(brw
, irb
, false);
845 intel_miptree_used_for_rendering(irb
->mt
);
847 surf
= brw_state_batch(brw
, AUB_TRACE_SURFACE_STATE
, 6 * 4, 32, &offset
);
849 format
= brw
->render_target_format
[rb_format
];
850 if (unlikely(!brw
->format_supported_as_render_target
[rb_format
])) {
851 _mesa_problem(ctx
, "%s: renderbuffer format %s unsupported\n",
852 __func__
, _mesa_get_format_name(rb_format
));
855 surf
[0] = (BRW_SURFACE_2D
<< BRW_SURFACE_TYPE_SHIFT
|
856 format
<< BRW_SURFACE_FORMAT_SHIFT
);
859 assert(mt
->offset
% mt
->cpp
== 0);
860 surf
[1] = (intel_renderbuffer_get_tile_offsets(irb
, &tile_x
, &tile_y
) +
861 mt
->bo
->offset64
+ mt
->offset
);
863 surf
[2] = ((rb
->Width
- 1) << BRW_SURFACE_WIDTH_SHIFT
|
864 (rb
->Height
- 1) << BRW_SURFACE_HEIGHT_SHIFT
);
866 surf
[3] = (brw_get_surface_tiling_bits(mt
->tiling
) |
867 (mt
->pitch
- 1) << BRW_SURFACE_PITCH_SHIFT
);
869 surf
[4] = brw_get_surface_num_multisamples(mt
->num_samples
);
871 assert(brw
->has_surface_tile_offset
|| (tile_x
== 0 && tile_y
== 0));
872 /* Note that the low bits of these fields are missing, so
873 * there's the possibility of getting in trouble.
875 assert(tile_x
% 4 == 0);
876 assert(tile_y
% 2 == 0);
877 surf
[5] = ((tile_x
/ 4) << BRW_SURFACE_X_OFFSET_SHIFT
|
878 (tile_y
/ 2) << BRW_SURFACE_Y_OFFSET_SHIFT
|
879 (mt
->valign
== 4 ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE
: 0));
883 if (!ctx
->Color
.ColorLogicOpEnabled
&&
884 (ctx
->Color
.BlendEnabled
& (1 << unit
)))
885 surf
[0] |= BRW_SURFACE_BLEND_ENABLED
;
887 if (!ctx
->Color
.ColorMask
[unit
][0])
888 surf
[0] |= 1 << BRW_SURFACE_WRITEDISABLE_R_SHIFT
;
889 if (!ctx
->Color
.ColorMask
[unit
][1])
890 surf
[0] |= 1 << BRW_SURFACE_WRITEDISABLE_G_SHIFT
;
891 if (!ctx
->Color
.ColorMask
[unit
][2])
892 surf
[0] |= 1 << BRW_SURFACE_WRITEDISABLE_B_SHIFT
;
894 /* As mentioned above, disable writes to the alpha component when the
895 * renderbuffer is XRGB.
897 if (ctx
->DrawBuffer
->Visual
.alphaBits
== 0 ||
898 !ctx
->Color
.ColorMask
[unit
][3]) {
899 surf
[0] |= 1 << BRW_SURFACE_WRITEDISABLE_A_SHIFT
;
903 drm_intel_bo_emit_reloc(brw
->batch
.bo
,
906 surf
[1] - mt
->bo
->offset64
,
907 I915_GEM_DOMAIN_RENDER
,
908 I915_GEM_DOMAIN_RENDER
);
914 * Construct SURFACE_STATE objects for renderbuffers/draw buffers.
917 brw_update_renderbuffer_surfaces(struct brw_context
*brw
,
918 const struct gl_framebuffer
*fb
,
919 uint32_t render_target_start
,
920 uint32_t *surf_offset
)
923 const unsigned int w
= _mesa_geometric_width(fb
);
924 const unsigned int h
= _mesa_geometric_height(fb
);
925 const unsigned int s
= _mesa_geometric_samples(fb
);
927 /* Update surfaces for drawing buffers */
928 if (fb
->_NumColorDrawBuffers
>= 1) {
929 for (i
= 0; i
< fb
->_NumColorDrawBuffers
; i
++) {
930 const uint32_t surf_index
= render_target_start
+ i
;
932 if (intel_renderbuffer(fb
->_ColorDrawBuffers
[i
])) {
933 surf_offset
[surf_index
] =
934 brw
->vtbl
.update_renderbuffer_surface(
935 brw
, fb
->_ColorDrawBuffers
[i
],
936 _mesa_geometric_layers(fb
) > 0, i
, surf_index
);
938 brw
->vtbl
.emit_null_surface_state(brw
, w
, h
, s
,
939 &surf_offset
[surf_index
]);
943 const uint32_t surf_index
= render_target_start
;
944 brw
->vtbl
.emit_null_surface_state(brw
, w
, h
, s
,
945 &surf_offset
[surf_index
]);
950 update_renderbuffer_surfaces(struct brw_context
*brw
)
952 const struct gl_context
*ctx
= &brw
->ctx
;
954 /* _NEW_BUFFERS | _NEW_COLOR */
955 const struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
956 brw_update_renderbuffer_surfaces(
958 brw
->wm
.prog_data
->binding_table
.render_target_start
,
959 brw
->wm
.base
.surf_offset
);
960 brw
->ctx
.NewDriverState
|= BRW_NEW_SURFACES
;
963 const struct brw_tracked_state brw_renderbuffer_surfaces
= {
965 .mesa
= _NEW_BUFFERS
|
967 .brw
= BRW_NEW_BATCH
|
969 BRW_NEW_FS_PROG_DATA
,
971 .emit
= update_renderbuffer_surfaces
,
974 const struct brw_tracked_state gen6_renderbuffer_surfaces
= {
976 .mesa
= _NEW_BUFFERS
,
977 .brw
= BRW_NEW_BATCH
|
980 .emit
= update_renderbuffer_surfaces
,
985 update_stage_texture_surfaces(struct brw_context
*brw
,
986 const struct gl_program
*prog
,
987 struct brw_stage_state
*stage_state
,
988 bool for_gather
, uint32_t plane
)
993 struct gl_context
*ctx
= &brw
->ctx
;
995 uint32_t *surf_offset
= stage_state
->surf_offset
;
997 /* BRW_NEW_*_PROG_DATA */
999 surf_offset
+= stage_state
->prog_data
->binding_table
.gather_texture_start
;
1001 surf_offset
+= stage_state
->prog_data
->binding_table
.plane_start
[plane
];
1003 unsigned num_samplers
= _mesa_fls(prog
->SamplersUsed
);
1004 for (unsigned s
= 0; s
< num_samplers
; s
++) {
1007 if (prog
->SamplersUsed
& (1 << s
)) {
1008 const unsigned unit
= prog
->SamplerUnits
[s
];
1011 if (ctx
->Texture
.Unit
[unit
]._Current
) {
1012 brw_update_texture_surface(ctx
, unit
, surf_offset
+ s
, for_gather
, plane
);
1020 * Construct SURFACE_STATE objects for enabled textures.
1023 brw_update_texture_surfaces(struct brw_context
*brw
)
1025 /* BRW_NEW_VERTEX_PROGRAM */
1026 struct gl_program
*vs
= (struct gl_program
*) brw
->vertex_program
;
1028 /* BRW_NEW_TESS_PROGRAMS */
1029 struct gl_program
*tcs
= (struct gl_program
*) brw
->tess_ctrl_program
;
1030 struct gl_program
*tes
= (struct gl_program
*) brw
->tess_eval_program
;
1032 /* BRW_NEW_GEOMETRY_PROGRAM */
1033 struct gl_program
*gs
= (struct gl_program
*) brw
->geometry_program
;
1035 /* BRW_NEW_FRAGMENT_PROGRAM */
1036 struct gl_program
*fs
= (struct gl_program
*) brw
->fragment_program
;
1039 update_stage_texture_surfaces(brw
, vs
, &brw
->vs
.base
, false, 0);
1040 update_stage_texture_surfaces(brw
, tcs
, &brw
->tcs
.base
, false, 0);
1041 update_stage_texture_surfaces(brw
, tes
, &brw
->tes
.base
, false, 0);
1042 update_stage_texture_surfaces(brw
, gs
, &brw
->gs
.base
, false, 0);
1043 update_stage_texture_surfaces(brw
, fs
, &brw
->wm
.base
, false, 0);
1045 /* emit alternate set of surface state for gather. this
1046 * allows the surface format to be overriden for only the
1047 * gather4 messages. */
1049 if (vs
&& vs
->UsesGather
)
1050 update_stage_texture_surfaces(brw
, vs
, &brw
->vs
.base
, true, 0);
1051 if (tcs
&& tcs
->UsesGather
)
1052 update_stage_texture_surfaces(brw
, tcs
, &brw
->tcs
.base
, true, 0);
1053 if (tes
&& tes
->UsesGather
)
1054 update_stage_texture_surfaces(brw
, tes
, &brw
->tes
.base
, true, 0);
1055 if (gs
&& gs
->UsesGather
)
1056 update_stage_texture_surfaces(brw
, gs
, &brw
->gs
.base
, true, 0);
1057 if (fs
&& fs
->UsesGather
)
1058 update_stage_texture_surfaces(brw
, fs
, &brw
->wm
.base
, true, 0);
1062 update_stage_texture_surfaces(brw
, fs
, &brw
->wm
.base
, false, 1);
1063 update_stage_texture_surfaces(brw
, fs
, &brw
->wm
.base
, false, 2);
1066 brw
->ctx
.NewDriverState
|= BRW_NEW_SURFACES
;
1069 const struct brw_tracked_state brw_texture_surfaces
= {
1071 .mesa
= _NEW_TEXTURE
,
1072 .brw
= BRW_NEW_BATCH
|
1074 BRW_NEW_FRAGMENT_PROGRAM
|
1075 BRW_NEW_FS_PROG_DATA
|
1076 BRW_NEW_GEOMETRY_PROGRAM
|
1077 BRW_NEW_GS_PROG_DATA
|
1078 BRW_NEW_TESS_PROGRAMS
|
1079 BRW_NEW_TCS_PROG_DATA
|
1080 BRW_NEW_TES_PROG_DATA
|
1081 BRW_NEW_TEXTURE_BUFFER
|
1082 BRW_NEW_VERTEX_PROGRAM
|
1083 BRW_NEW_VS_PROG_DATA
,
1085 .emit
= brw_update_texture_surfaces
,
1089 brw_update_cs_texture_surfaces(struct brw_context
*brw
)
1091 /* BRW_NEW_COMPUTE_PROGRAM */
1092 struct gl_program
*cs
= (struct gl_program
*) brw
->compute_program
;
1095 update_stage_texture_surfaces(brw
, cs
, &brw
->cs
.base
, false, 0);
1097 /* emit alternate set of surface state for gather. this
1098 * allows the surface format to be overriden for only the
1102 if (cs
&& cs
->UsesGather
)
1103 update_stage_texture_surfaces(brw
, cs
, &brw
->cs
.base
, true, 0);
1106 brw
->ctx
.NewDriverState
|= BRW_NEW_SURFACES
;
1109 const struct brw_tracked_state brw_cs_texture_surfaces
= {
1111 .mesa
= _NEW_TEXTURE
,
1112 .brw
= BRW_NEW_BATCH
|
1114 BRW_NEW_COMPUTE_PROGRAM
,
1116 .emit
= brw_update_cs_texture_surfaces
,
1121 brw_upload_ubo_surfaces(struct brw_context
*brw
,
1122 struct gl_linked_shader
*shader
,
1123 struct brw_stage_state
*stage_state
,
1124 struct brw_stage_prog_data
*prog_data
)
1126 struct gl_context
*ctx
= &brw
->ctx
;
1131 uint32_t *ubo_surf_offsets
=
1132 &stage_state
->surf_offset
[prog_data
->binding_table
.ubo_start
];
1134 for (int i
= 0; i
< shader
->NumUniformBlocks
; i
++) {
1135 struct gl_uniform_buffer_binding
*binding
=
1136 &ctx
->UniformBufferBindings
[shader
->UniformBlocks
[i
]->Binding
];
1138 if (binding
->BufferObject
== ctx
->Shared
->NullBufferObj
) {
1139 brw
->vtbl
.emit_null_surface_state(brw
, 1, 1, 1, &ubo_surf_offsets
[i
]);
1141 struct intel_buffer_object
*intel_bo
=
1142 intel_buffer_object(binding
->BufferObject
);
1143 GLsizeiptr size
= binding
->BufferObject
->Size
- binding
->Offset
;
1144 if (!binding
->AutomaticSize
)
1145 size
= MIN2(size
, binding
->Size
);
1147 intel_bufferobj_buffer(brw
, intel_bo
,
1150 brw_create_constant_surface(brw
, bo
, binding
->Offset
,
1152 &ubo_surf_offsets
[i
]);
1156 uint32_t *ssbo_surf_offsets
=
1157 &stage_state
->surf_offset
[prog_data
->binding_table
.ssbo_start
];
1159 for (int i
= 0; i
< shader
->NumShaderStorageBlocks
; i
++) {
1160 struct gl_shader_storage_buffer_binding
*binding
=
1161 &ctx
->ShaderStorageBufferBindings
[shader
->ShaderStorageBlocks
[i
]->Binding
];
1163 if (binding
->BufferObject
== ctx
->Shared
->NullBufferObj
) {
1164 brw
->vtbl
.emit_null_surface_state(brw
, 1, 1, 1, &ssbo_surf_offsets
[i
]);
1166 struct intel_buffer_object
*intel_bo
=
1167 intel_buffer_object(binding
->BufferObject
);
1168 GLsizeiptr size
= binding
->BufferObject
->Size
- binding
->Offset
;
1169 if (!binding
->AutomaticSize
)
1170 size
= MIN2(size
, binding
->Size
);
1172 intel_bufferobj_buffer(brw
, intel_bo
,
1175 brw_create_buffer_surface(brw
, bo
, binding
->Offset
,
1177 &ssbo_surf_offsets
[i
]);
1181 if (shader
->NumUniformBlocks
|| shader
->NumShaderStorageBlocks
)
1182 brw
->ctx
.NewDriverState
|= BRW_NEW_SURFACES
;
1186 brw_upload_wm_ubo_surfaces(struct brw_context
*brw
)
1188 struct gl_context
*ctx
= &brw
->ctx
;
1190 struct gl_shader_program
*prog
= ctx
->_Shader
->_CurrentFragmentProgram
;
1195 /* BRW_NEW_FS_PROG_DATA */
1196 brw_upload_ubo_surfaces(brw
, prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
],
1197 &brw
->wm
.base
, &brw
->wm
.prog_data
->base
);
1200 const struct brw_tracked_state brw_wm_ubo_surfaces
= {
1202 .mesa
= _NEW_PROGRAM
,
1203 .brw
= BRW_NEW_BATCH
|
1205 BRW_NEW_FS_PROG_DATA
|
1206 BRW_NEW_UNIFORM_BUFFER
,
1208 .emit
= brw_upload_wm_ubo_surfaces
,
1212 brw_upload_cs_ubo_surfaces(struct brw_context
*brw
)
1214 struct gl_context
*ctx
= &brw
->ctx
;
1216 struct gl_shader_program
*prog
=
1217 ctx
->_Shader
->CurrentProgram
[MESA_SHADER_COMPUTE
];
1222 /* BRW_NEW_CS_PROG_DATA */
1223 brw_upload_ubo_surfaces(brw
, prog
->_LinkedShaders
[MESA_SHADER_COMPUTE
],
1224 &brw
->cs
.base
, &brw
->cs
.prog_data
->base
);
1227 const struct brw_tracked_state brw_cs_ubo_surfaces
= {
1229 .mesa
= _NEW_PROGRAM
,
1230 .brw
= BRW_NEW_BATCH
|
1232 BRW_NEW_CS_PROG_DATA
|
1233 BRW_NEW_UNIFORM_BUFFER
,
1235 .emit
= brw_upload_cs_ubo_surfaces
,
1239 brw_upload_abo_surfaces(struct brw_context
*brw
,
1240 struct gl_linked_shader
*shader
,
1241 struct brw_stage_state
*stage_state
,
1242 struct brw_stage_prog_data
*prog_data
)
1244 struct gl_context
*ctx
= &brw
->ctx
;
1245 uint32_t *surf_offsets
=
1246 &stage_state
->surf_offset
[prog_data
->binding_table
.abo_start
];
1248 if (shader
&& shader
->NumAtomicBuffers
) {
1249 for (unsigned i
= 0; i
< shader
->NumAtomicBuffers
; i
++) {
1250 struct gl_atomic_buffer_binding
*binding
=
1251 &ctx
->AtomicBufferBindings
[shader
->AtomicBuffers
[i
]->Binding
];
1252 struct intel_buffer_object
*intel_bo
=
1253 intel_buffer_object(binding
->BufferObject
);
1254 drm_intel_bo
*bo
= intel_bufferobj_buffer(
1255 brw
, intel_bo
, binding
->Offset
, intel_bo
->Base
.Size
- binding
->Offset
);
1257 brw_emit_buffer_surface_state(brw
, &surf_offsets
[i
], bo
,
1258 binding
->Offset
, BRW_SURFACEFORMAT_RAW
,
1259 bo
->size
- binding
->Offset
, 1, true);
1262 brw
->ctx
.NewDriverState
|= BRW_NEW_SURFACES
;
1267 brw_upload_wm_abo_surfaces(struct brw_context
*brw
)
1269 struct gl_context
*ctx
= &brw
->ctx
;
1271 struct gl_shader_program
*prog
= ctx
->_Shader
->_CurrentFragmentProgram
;
1274 /* BRW_NEW_FS_PROG_DATA */
1275 brw_upload_abo_surfaces(brw
, prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
],
1276 &brw
->wm
.base
, &brw
->wm
.prog_data
->base
);
1280 const struct brw_tracked_state brw_wm_abo_surfaces
= {
1282 .mesa
= _NEW_PROGRAM
,
1283 .brw
= BRW_NEW_ATOMIC_BUFFER
|
1286 BRW_NEW_FS_PROG_DATA
,
1288 .emit
= brw_upload_wm_abo_surfaces
,
1292 brw_upload_cs_abo_surfaces(struct brw_context
*brw
)
1294 struct gl_context
*ctx
= &brw
->ctx
;
1296 struct gl_shader_program
*prog
=
1297 ctx
->_Shader
->CurrentProgram
[MESA_SHADER_COMPUTE
];
1300 /* BRW_NEW_CS_PROG_DATA */
1301 brw_upload_abo_surfaces(brw
, prog
->_LinkedShaders
[MESA_SHADER_COMPUTE
],
1302 &brw
->cs
.base
, &brw
->cs
.prog_data
->base
);
1306 const struct brw_tracked_state brw_cs_abo_surfaces
= {
1308 .mesa
= _NEW_PROGRAM
,
1309 .brw
= BRW_NEW_ATOMIC_BUFFER
|
1312 BRW_NEW_CS_PROG_DATA
,
1314 .emit
= brw_upload_cs_abo_surfaces
,
1318 brw_upload_cs_image_surfaces(struct brw_context
*brw
)
1320 struct gl_context
*ctx
= &brw
->ctx
;
1322 struct gl_shader_program
*prog
=
1323 ctx
->_Shader
->CurrentProgram
[MESA_SHADER_COMPUTE
];
1326 /* BRW_NEW_CS_PROG_DATA, BRW_NEW_IMAGE_UNITS, _NEW_TEXTURE */
1327 brw_upload_image_surfaces(brw
, prog
->_LinkedShaders
[MESA_SHADER_COMPUTE
],
1328 &brw
->cs
.base
, &brw
->cs
.prog_data
->base
);
1332 const struct brw_tracked_state brw_cs_image_surfaces
= {
1334 .mesa
= _NEW_TEXTURE
| _NEW_PROGRAM
,
1335 .brw
= BRW_NEW_BATCH
|
1337 BRW_NEW_CS_PROG_DATA
|
1340 .emit
= brw_upload_cs_image_surfaces
,
1344 get_image_format(struct brw_context
*brw
, mesa_format format
, GLenum access
)
1346 const struct brw_device_info
*devinfo
= brw
->intelScreen
->devinfo
;
1347 uint32_t hw_format
= brw_format_for_mesa_format(format
);
1348 if (access
== GL_WRITE_ONLY
) {
1350 } else if (isl_has_matching_typed_storage_image_format(devinfo
, hw_format
)) {
1351 /* Typed surface reads support a very limited subset of the shader
1352 * image formats. Translate it into the closest format the
1353 * hardware supports.
1355 return isl_lower_storage_image_format(devinfo
, hw_format
);
1357 /* The hardware doesn't actually support a typed format that we can use
1358 * so we have to fall back to untyped read/write messages.
1360 return BRW_SURFACEFORMAT_RAW
;
1365 update_default_image_param(struct brw_context
*brw
,
1366 struct gl_image_unit
*u
,
1367 unsigned surface_idx
,
1368 struct brw_image_param
*param
)
1370 memset(param
, 0, sizeof(*param
));
1371 param
->surface_idx
= surface_idx
;
1372 /* Set the swizzling shifts to all-ones to effectively disable swizzling --
1373 * See emit_address_calculation() in brw_fs_surface_builder.cpp for a more
1374 * detailed explanation of these parameters.
1376 param
->swizzling
[0] = 0xff;
1377 param
->swizzling
[1] = 0xff;
1381 update_buffer_image_param(struct brw_context
*brw
,
1382 struct gl_image_unit
*u
,
1383 unsigned surface_idx
,
1384 struct brw_image_param
*param
)
1386 struct gl_buffer_object
*obj
= u
->TexObj
->BufferObject
;
1388 update_default_image_param(brw
, u
, surface_idx
, param
);
1390 param
->size
[0] = obj
->Size
/ _mesa_get_format_bytes(u
->_ActualFormat
);
1391 param
->stride
[0] = _mesa_get_format_bytes(u
->_ActualFormat
);
1395 update_texture_image_param(struct brw_context
*brw
,
1396 struct gl_image_unit
*u
,
1397 unsigned surface_idx
,
1398 struct brw_image_param
*param
)
1400 struct intel_mipmap_tree
*mt
= intel_texture_object(u
->TexObj
)->mt
;
1402 update_default_image_param(brw
, u
, surface_idx
, param
);
1404 param
->size
[0] = minify(mt
->logical_width0
, u
->Level
);
1405 param
->size
[1] = minify(mt
->logical_height0
, u
->Level
);
1406 param
->size
[2] = (!u
->Layered
? 1 :
1407 u
->TexObj
->Target
== GL_TEXTURE_CUBE_MAP
? 6 :
1408 u
->TexObj
->Target
== GL_TEXTURE_3D
?
1409 minify(mt
->logical_depth0
, u
->Level
) :
1410 mt
->logical_depth0
);
1412 intel_miptree_get_image_offset(mt
, u
->Level
, u
->_Layer
,
1416 param
->stride
[0] = mt
->cpp
;
1417 param
->stride
[1] = mt
->pitch
/ mt
->cpp
;
1419 brw_miptree_get_horizontal_slice_pitch(brw
, mt
, u
->Level
);
1421 brw_miptree_get_vertical_slice_pitch(brw
, mt
, u
->Level
);
1423 if (mt
->tiling
== I915_TILING_X
) {
1424 /* An X tile is a rectangular block of 512x8 bytes. */
1425 param
->tiling
[0] = _mesa_logbase2(512 / mt
->cpp
);
1426 param
->tiling
[1] = _mesa_logbase2(8);
1428 if (brw
->has_swizzling
) {
1429 /* Right shifts required to swizzle bits 9 and 10 of the memory
1430 * address with bit 6.
1432 param
->swizzling
[0] = 3;
1433 param
->swizzling
[1] = 4;
1435 } else if (mt
->tiling
== I915_TILING_Y
) {
1436 /* The layout of a Y-tiled surface in memory isn't really fundamentally
1437 * different to the layout of an X-tiled surface, we simply pretend that
1438 * the surface is broken up in a number of smaller 16Bx32 tiles, each
1439 * one arranged in X-major order just like is the case for X-tiling.
1441 param
->tiling
[0] = _mesa_logbase2(16 / mt
->cpp
);
1442 param
->tiling
[1] = _mesa_logbase2(32);
1444 if (brw
->has_swizzling
) {
1445 /* Right shift required to swizzle bit 9 of the memory address with
1448 param
->swizzling
[0] = 3;
1452 /* 3D textures are arranged in 2D in memory with 2^lod slices per row. The
1453 * address calculation algorithm (emit_address_calculation() in
1454 * brw_fs_surface_builder.cpp) handles this as a sort of tiling with
1455 * modulus equal to the LOD.
1457 param
->tiling
[2] = (u
->TexObj
->Target
== GL_TEXTURE_3D
? u
->Level
:
1462 update_image_surface(struct brw_context
*brw
,
1463 struct gl_image_unit
*u
,
1465 unsigned surface_idx
,
1466 uint32_t *surf_offset
,
1467 struct brw_image_param
*param
)
1469 if (_mesa_is_image_unit_valid(&brw
->ctx
, u
)) {
1470 struct gl_texture_object
*obj
= u
->TexObj
;
1471 const unsigned format
= get_image_format(brw
, u
->_ActualFormat
, access
);
1473 if (obj
->Target
== GL_TEXTURE_BUFFER
) {
1474 struct intel_buffer_object
*intel_obj
=
1475 intel_buffer_object(obj
->BufferObject
);
1476 const unsigned texel_size
= (format
== BRW_SURFACEFORMAT_RAW
? 1 :
1477 _mesa_get_format_bytes(u
->_ActualFormat
));
1479 brw_emit_buffer_surface_state(
1480 brw
, surf_offset
, intel_obj
->buffer
, obj
->BufferOffset
,
1481 format
, intel_obj
->Base
.Size
, texel_size
,
1482 access
!= GL_READ_ONLY
);
1484 update_buffer_image_param(brw
, u
, surface_idx
, param
);
1487 struct intel_texture_object
*intel_obj
= intel_texture_object(obj
);
1488 struct intel_mipmap_tree
*mt
= intel_obj
->mt
;
1490 if (format
== BRW_SURFACEFORMAT_RAW
) {
1491 brw_emit_buffer_surface_state(
1492 brw
, surf_offset
, mt
->bo
, mt
->offset
,
1493 format
, mt
->bo
->size
- mt
->offset
, 1 /* pitch */,
1494 access
!= GL_READ_ONLY
);
1497 const unsigned num_layers
= (!u
->Layered
? 1 :
1498 obj
->Target
== GL_TEXTURE_CUBE_MAP
? 6 :
1499 mt
->logical_depth0
);
1501 struct isl_view view
= {
1503 .base_level
= obj
->MinLevel
+ u
->Level
,
1505 .base_array_layer
= obj
->MinLayer
+ u
->_Layer
,
1506 .array_len
= num_layers
,
1508 ISL_CHANNEL_SELECT_RED
,
1509 ISL_CHANNEL_SELECT_GREEN
,
1510 ISL_CHANNEL_SELECT_BLUE
,
1511 ISL_CHANNEL_SELECT_ALPHA
,
1513 .usage
= ISL_SURF_USAGE_STORAGE_BIT
,
1516 const int surf_index
= surf_offset
- &brw
->wm
.base
.surf_offset
[0];
1518 brw_emit_surface_state(brw
, mt
, &view
,
1519 surface_state_infos
[brw
->gen
].tex_mocs
, false,
1520 surf_offset
, surf_index
,
1521 I915_GEM_DOMAIN_SAMPLER
,
1522 access
== GL_READ_ONLY
? 0 :
1523 I915_GEM_DOMAIN_SAMPLER
);
1526 update_texture_image_param(brw
, u
, surface_idx
, param
);
1530 brw
->vtbl
.emit_null_surface_state(brw
, 1, 1, 1, surf_offset
);
1531 update_default_image_param(brw
, u
, surface_idx
, param
);
1536 brw_upload_image_surfaces(struct brw_context
*brw
,
1537 struct gl_linked_shader
*shader
,
1538 struct brw_stage_state
*stage_state
,
1539 struct brw_stage_prog_data
*prog_data
)
1541 struct gl_context
*ctx
= &brw
->ctx
;
1543 if (shader
&& shader
->NumImages
) {
1544 for (unsigned i
= 0; i
< shader
->NumImages
; i
++) {
1545 struct gl_image_unit
*u
= &ctx
->ImageUnits
[shader
->ImageUnits
[i
]];
1546 const unsigned surf_idx
= prog_data
->binding_table
.image_start
+ i
;
1548 update_image_surface(brw
, u
, shader
->ImageAccess
[i
],
1550 &stage_state
->surf_offset
[surf_idx
],
1551 &prog_data
->image_param
[i
]);
1554 brw
->ctx
.NewDriverState
|= BRW_NEW_SURFACES
;
1555 /* This may have changed the image metadata dependent on the context
1556 * image unit state and passed to the program as uniforms, make sure
1557 * that push and pull constants are reuploaded.
1559 brw
->NewGLState
|= _NEW_PROGRAM_CONSTANTS
;
1564 brw_upload_wm_image_surfaces(struct brw_context
*brw
)
1566 struct gl_context
*ctx
= &brw
->ctx
;
1567 /* BRW_NEW_FRAGMENT_PROGRAM */
1568 struct gl_shader_program
*prog
= ctx
->_Shader
->_CurrentFragmentProgram
;
1571 /* BRW_NEW_FS_PROG_DATA, BRW_NEW_IMAGE_UNITS, _NEW_TEXTURE */
1572 brw_upload_image_surfaces(brw
, prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
],
1573 &brw
->wm
.base
, &brw
->wm
.prog_data
->base
);
1577 const struct brw_tracked_state brw_wm_image_surfaces
= {
1579 .mesa
= _NEW_TEXTURE
,
1580 .brw
= BRW_NEW_BATCH
|
1582 BRW_NEW_FRAGMENT_PROGRAM
|
1583 BRW_NEW_FS_PROG_DATA
|
1586 .emit
= brw_upload_wm_image_surfaces
,
1590 gen4_init_vtable_surface_functions(struct brw_context
*brw
)
1592 brw
->vtbl
.update_renderbuffer_surface
= gen4_update_renderbuffer_surface
;
1593 brw
->vtbl
.emit_null_surface_state
= brw_emit_null_surface_state
;
1597 gen6_init_vtable_surface_functions(struct brw_context
*brw
)
1599 gen4_init_vtable_surface_functions(brw
);
1600 brw
->vtbl
.update_renderbuffer_surface
= brw_update_renderbuffer_surface
;
1604 brw_upload_cs_work_groups_surface(struct brw_context
*brw
)
1606 struct gl_context
*ctx
= &brw
->ctx
;
1608 struct gl_shader_program
*prog
=
1609 ctx
->_Shader
->CurrentProgram
[MESA_SHADER_COMPUTE
];
1611 if (prog
&& brw
->cs
.prog_data
->uses_num_work_groups
) {
1612 const unsigned surf_idx
=
1613 brw
->cs
.prog_data
->binding_table
.work_groups_start
;
1614 uint32_t *surf_offset
= &brw
->cs
.base
.surf_offset
[surf_idx
];
1618 if (brw
->compute
.num_work_groups_bo
== NULL
) {
1620 intel_upload_data(brw
,
1621 (void *)brw
->compute
.num_work_groups
,
1627 bo
= brw
->compute
.num_work_groups_bo
;
1628 bo_offset
= brw
->compute
.num_work_groups_offset
;
1631 brw_emit_buffer_surface_state(brw
, surf_offset
,
1633 BRW_SURFACEFORMAT_RAW
,
1634 3 * sizeof(GLuint
), 1, true);
1635 brw
->ctx
.NewDriverState
|= BRW_NEW_SURFACES
;
1639 const struct brw_tracked_state brw_cs_work_groups_surface
= {
1641 .brw
= BRW_NEW_BLORP
|
1642 BRW_NEW_CS_WORK_GROUPS
1644 .emit
= brw_upload_cs_work_groups_surface
,