src/mesa/drivers/dri/i965/gen6_depthstencil.c

   1 /*
   2  * Copyright © 2009 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include "intel_batchbuffer.h"
  29 #include "intel_fbo.h"
  30 #include "brw_context.h"
  31 #include "brw_defines.h"
  32 #include "brw_state.h"
  33
  34 static void
  35 gen6_upload_depth_stencil_state(struct brw_context *brw)
  36 {
  37    struct gl_context *ctx = &brw->ctx;
  38    struct gen6_depth_stencil_state *ds;
  39    struct intel_renderbuffer *depth_irb;
  40
  41    /* _NEW_BUFFERS */
  42    depth_irb = intel_get_renderbuffer(ctx->DrawBuffer, BUFFER_DEPTH);
  43
  44    ds = brw_state_batch(brw, AUB_TRACE_DEPTH_STENCIL_STATE,
  45                         sizeof(*ds), 64,
  46                         &brw->cc.depth_stencil_state_offset);
  47    memset(ds, 0, sizeof(*ds));
  48
  49    /* _NEW_STENCIL | _NEW_BUFFERS */
  50    if (ctx->Stencil._Enabled) {
  51       int back = ctx->Stencil._BackFace;
  52
  53       ds->ds0.stencil_enable = 1;
  54       ds->ds0.stencil_func =
  55          intel_translate_compare_func(ctx->Stencil.Function[0]);
  56       ds->ds0.stencil_fail_op =
  57          intel_translate_stencil_op(ctx->Stencil.FailFunc[0]);
  58       ds->ds0.stencil_pass_depth_fail_op =
  59          intel_translate_stencil_op(ctx->Stencil.ZFailFunc[0]);
  60       ds->ds0.stencil_pass_depth_pass_op =
  61          intel_translate_stencil_op(ctx->Stencil.ZPassFunc[0]);
  62       ds->ds1.stencil_write_mask = ctx->Stencil.WriteMask[0];
  63       ds->ds1.stencil_test_mask = ctx->Stencil.ValueMask[0];
  64
  65       if (ctx->Stencil._TestTwoSide) {
  66          ds->ds0.bf_stencil_enable = 1;
  67          ds->ds0.bf_stencil_func =
  68             intel_translate_compare_func(ctx->Stencil.Function[back]);
  69          ds->ds0.bf_stencil_fail_op =
  70             intel_translate_stencil_op(ctx->Stencil.FailFunc[back]);
  71          ds->ds0.bf_stencil_pass_depth_fail_op =
  72             intel_translate_stencil_op(ctx->Stencil.ZFailFunc[back]);
  73          ds->ds0.bf_stencil_pass_depth_pass_op =
  74             intel_translate_stencil_op(ctx->Stencil.ZPassFunc[back]);
  75          ds->ds1.bf_stencil_write_mask = ctx->Stencil.WriteMask[back];
  76          ds->ds1.bf_stencil_test_mask = ctx->Stencil.ValueMask[back];
  77       }
  78
  79       ds->ds0.stencil_write_enable = ctx->Stencil._WriteEnabled;
  80    }
  81
  82    /* _NEW_DEPTH */
  83    if (ctx->Depth.Test && depth_irb) {
  84       ds->ds2.depth_test_enable = ctx->Depth.Test;
  85       ds->ds2.depth_test_func = intel_translate_compare_func(ctx->Depth.Func);
  86       ds->ds2.depth_write_enable = brw_depth_writes_enabled(brw);
  87    }
  88
  89    /* Point the GPU at the new indirect state. */
  90    if (brw->gen == 6) {
  91       BEGIN_BATCH(4);
  92       OUT_BATCH(_3DSTATE_CC_STATE_POINTERS << 16 | (4 - 2));
  93       OUT_BATCH(0);
  94       OUT_BATCH(brw->cc.depth_stencil_state_offset | 1);
  95       OUT_BATCH(0);
  96       ADVANCE_BATCH();
  97    } else {
  98       BEGIN_BATCH(2);
  99       OUT_BATCH(_3DSTATE_DEPTH_STENCIL_STATE_POINTERS << 16 | (2 - 2));
 100       OUT_BATCH(brw->cc.depth_stencil_state_offset | 1);
 101       ADVANCE_BATCH();
 102    }
 103 }
 104
 105 const struct brw_tracked_state gen6_depth_stencil_state = {
 106    .dirty = {
 107       .mesa = _NEW_BUFFERS |
 108               _NEW_DEPTH |
 109               _NEW_STENCIL,
 110       .brw  = BRW_NEW_BATCH |
 111               BRW_NEW_BLORP |
 112               BRW_NEW_STATE_BASE_ADDRESS,
 113    },
 114    .emit = gen6_upload_depth_stencil_state,
 115 };