src/mesa/drivers/dri/i965/gen6_sf_state.c

   1 /*
   2  * Copyright © 2009 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include "brw_context.h"
  29 #include "brw_state.h"
  30 #include "brw_defines.h"
  31 #include "brw_util.h"
  32 #include "main/macros.h"
  33 #include "intel_batchbuffer.h"
  34
  35 static uint32_t
  36 get_attr_override(struct brw_context *brw, int fs_attr)
  37 {
  38    int attr_index = 0, i, vs_attr;
  39
  40    if (fs_attr <= FRAG_ATTRIB_TEX7)
  41       vs_attr = fs_attr;
  42    else if (fs_attr == FRAG_ATTRIB_FACE)
  43       vs_attr = 0; /* XXX */
  44    else if (fs_attr == FRAG_ATTRIB_PNTC)
  45       vs_attr = 0; /* XXX */
  46    else {
  47       assert(fs_attr >= FRAG_ATTRIB_VAR0);
  48       vs_attr = fs_attr - FRAG_ATTRIB_VAR0 + VERT_RESULT_VAR0;
  49    }
  50
  51    /* Find the source index (0 = first attribute after the 4D position)
  52     * for this output attribute.  attr is currently a VERT_RESULT_* but should
  53     * be FRAG_ATTRIB_*.
  54     */
  55    for (i = 0; i < vs_attr; i++) {
  56       if (brw->vs.prog_data->outputs_written & BITFIELD64_BIT(i))
  57          attr_index++;
  58    }
  59
  60    return attr_index;
  61 }
  62
  63 static void
  64 upload_sf_state(struct brw_context *brw)
  65 {
  66    struct intel_context *intel = &brw->intel;
  67    GLcontext *ctx = &intel->ctx;
  68    /* CACHE_NEW_VS_PROG */
  69    uint32_t num_inputs = brw_count_bits(brw->vs.prog_data->outputs_written);
  70    uint32_t num_outputs = brw_count_bits(brw->fragment_program->Base.InputsRead);
  71    uint32_t dw1, dw2, dw3, dw4, dw16;
  72    int i;
  73    /* _NEW_BUFFER */
  74    GLboolean render_to_fbo = brw->intel.ctx.DrawBuffer->Name != 0;
  75    int attr = 0;
  76
  77    dw1 =
  78       num_outputs << GEN6_SF_NUM_OUTPUTS_SHIFT |
  79       (num_inputs + 1) / 2 << GEN6_SF_URB_ENTRY_READ_LENGTH_SHIFT |
  80       1 << GEN6_SF_URB_ENTRY_READ_OFFSET_SHIFT;
  81    dw2 = GEN6_SF_VIEWPORT_TRANSFORM_ENABLE |
  82       GEN6_SF_STATISTICS_ENABLE;
  83    dw3 = 0;
  84    dw4 = 0;
  85    dw16 = 0;
  86
  87    /* _NEW_POLYGON */
  88    if ((ctx->Polygon.FrontFace == GL_CCW) ^ render_to_fbo)
  89       dw2 |= GEN6_SF_WINDING_CCW;
  90
  91    if (ctx->Polygon.OffsetFill)
  92        dw2 |= GEN6_SF_GLOBAL_DEPTH_OFFSET_SOLID;
  93
  94    /* _NEW_SCISSOR */
  95    if (ctx->Scissor.Enabled)
  96       dw3 |= GEN6_SF_SCISSOR_ENABLE;
  97
  98    /* _NEW_POLYGON */
  99    if (ctx->Polygon.CullFlag) {
 100       switch (ctx->Polygon.CullFaceMode) {
 101       case GL_FRONT:
 102          dw3 |= GEN6_SF_CULL_FRONT;
 103          break;
 104       case GL_BACK:
 105          dw3 |= GEN6_SF_CULL_BACK;
 106          break;
 107       case GL_FRONT_AND_BACK:
 108          dw3 |= GEN6_SF_CULL_BOTH;
 109          break;
 110       default:
 111          assert(0);
 112          break;
 113       }
 114    } else {
 115       dw3 |= GEN6_SF_CULL_NONE;
 116    }
 117
 118    /* _NEW_LINE */
 119    dw3 |= U_FIXED(CLAMP(ctx->Line.Width, 0.0, 7.99), 7) <<
 120       GEN6_SF_LINE_WIDTH_SHIFT;
 121    if (ctx->Line.SmoothFlag) {
 122       dw3 |= GEN6_SF_LINE_AA_ENABLE;
 123       dw3 |= GEN6_SF_LINE_AA_MODE_TRUE;
 124       dw3 |= GEN6_SF_LINE_END_CAP_WIDTH_1_0;
 125    }
 126
 127    /* _NEW_POINT */
 128    if (ctx->Point._Attenuated)
 129       dw4 |= GEN6_SF_USE_STATE_POINT_WIDTH;
 130
 131    dw4 |= U_FIXED(CLAMP(ctx->Point.Size, 0.125, 225.875), 3) <<
 132       GEN6_SF_POINT_WIDTH_SHIFT;
 133    if (ctx->Point.SpriteOrigin == GL_LOWER_LEFT)
 134       dw1 |= GEN6_SF_POINT_SPRITE_LOWERLEFT;
 135
 136    /* _NEW_LIGHT */
 137    if (ctx->Light.ProvokingVertex != GL_FIRST_VERTEX_CONVENTION) {
 138       dw4 |=
 139          (2 << GEN6_SF_TRI_PROVOKE_SHIFT) |
 140          (2 << GEN6_SF_TRIFAN_PROVOKE_SHIFT) |
 141          (1 << GEN6_SF_LINE_PROVOKE_SHIFT);
 142    } else {
 143       dw4 |=
 144          (1 << GEN6_SF_TRIFAN_PROVOKE_SHIFT);
 145    }
 146
 147    if (ctx->Point.PointSprite) {
 148        for (i = 0; i < 8; i++) {
 149            if (ctx->Point.CoordReplace[i])
 150                dw16 |= (1 << i);
 151        }
 152    }
 153
 154    BEGIN_BATCH(20);
 155    OUT_BATCH(CMD_3D_SF_STATE << 16 | (20 - 2));
 156    OUT_BATCH(dw1);
 157    OUT_BATCH(dw2);
 158    OUT_BATCH(dw3);
 159    OUT_BATCH(dw4);
 160    OUT_BATCH_F(ctx->Polygon.OffsetUnits * 2); /* constant.  copied from gen4 */
 161    OUT_BATCH_F(ctx->Polygon.OffsetFactor); /* scale */
 162    OUT_BATCH_F(0.0); /* XXX: global depth offset clamp */
 163    for (i = 0; i < 8; i++) {
 164       uint32_t attr_overrides = 0;
 165
 166       for (; attr < 64; attr++) {
 167          if (brw->fragment_program->Base.InputsRead & BITFIELD64_BIT(attr)) {
 168             attr_overrides |= get_attr_override(brw, attr);
 169             attr++;
 170             break;
 171          }
 172       }
 173
 174       for (; attr < 64; attr++) {
 175          if (brw->fragment_program->Base.InputsRead & BITFIELD64_BIT(attr)) {
 176             attr_overrides |= get_attr_override(brw, attr) << 16;
 177             attr++;
 178             break;
 179          }
 180       }
 181       OUT_BATCH(attr_overrides);
 182    }
 183    OUT_BATCH(dw16); /* point sprite texcoord bitmask */
 184    OUT_BATCH(0); /* constant interp bitmask */
 185    OUT_BATCH(0); /* wrapshortest enables 0-7 */
 186    OUT_BATCH(0); /* wrapshortest enables 8-15 */
 187    ADVANCE_BATCH();
 188
 189    intel_batchbuffer_emit_mi_flush(intel->batch);
 190 }
 191
 192 const struct brw_tracked_state gen6_sf_state = {
 193    .dirty = {
 194       .mesa  = (_NEW_LIGHT |
 195                 _NEW_POLYGON |
 196                 _NEW_LINE |
 197                 _NEW_SCISSOR |
 198                 _NEW_BUFFERS),
 199       .brw   = BRW_NEW_CONTEXT,
 200       .cache = CACHE_NEW_VS_PROG
 201    },
 202    .emit = upload_sf_state,
 203 };