src/mesa/drivers/dri/i965/gen6_vs_state.c

   1 /*
   2  * Copyright © 2009 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include "brw_context.h"
  29 #include "brw_state.h"
  30 #include "brw_defines.h"
  31 #include "brw_util.h"
  32 #include "shader/prog_parameter.h"
  33 #include "shader/prog_statevars.h"
  34 #include "intel_batchbuffer.h"
  35
  36 static void
  37 upload_vs_state(struct brw_context *brw)
  38 {
  39    struct intel_context *intel = &brw->intel;
  40    GLcontext *ctx = &intel->ctx;
  41    const struct brw_vertex_program *vp =
  42       brw_vertex_program_const(brw->vertex_program);
  43    unsigned int nr_params = vp->program.Base.Parameters->NumParameters;
  44    drm_intel_bo *constant_bo;
  45    int i;
  46
  47    if (vp->use_const_buffer || nr_params == 0) {
  48       /* Disable the push constant buffers. */
  49       BEGIN_BATCH(5);
  50       OUT_BATCH(CMD_3D_CONSTANT_VS_STATE << 16 | (5 - 2));
  51       OUT_BATCH(0);
  52       OUT_BATCH(0);
  53       OUT_BATCH(0);
  54       OUT_BATCH(0);
  55       ADVANCE_BATCH();
  56    } else {
  57       if (brw->vertex_program->IsNVProgram)
  58          _mesa_load_tracked_matrices(ctx);
  59
  60       /* Updates the ParamaterValues[i] pointers for all parameters of the
  61        * basic type of PROGRAM_STATE_VAR.
  62        */
  63       _mesa_load_state_parameters(ctx, vp->program.Base.Parameters);
  64
  65       constant_bo = drm_intel_bo_alloc(intel->bufmgr, "VS constant_bo",
  66                                        nr_params * 4 * sizeof(float),
  67                                        4096);
  68       drm_intel_gem_bo_map_gtt(constant_bo);
  69       for (i = 0; i < nr_params; i++) {
  70          memcpy((char *)constant_bo->virtual + i * 4 * sizeof(float),
  71                 vp->program.Base.Parameters->ParameterValues[i],
  72                 4 * sizeof(float));
  73       }
  74       drm_intel_gem_bo_unmap_gtt(constant_bo);
  75
  76       BEGIN_BATCH(5);
  77       OUT_BATCH(CMD_3D_CONSTANT_VS_STATE << 16 |
  78                 GEN6_CONSTANT_BUFFER_0_ENABLE |
  79                 (5 - 2));
  80       OUT_RELOC(constant_bo,
  81                 I915_GEM_DOMAIN_RENDER, 0, /* XXX: bad domain */
  82                 ALIGN(nr_params, 2) / 2 - 1);
  83       OUT_BATCH(0);
  84       OUT_BATCH(0);
  85       OUT_BATCH(0);
  86       ADVANCE_BATCH();
  87
  88       drm_intel_bo_unreference(constant_bo);
  89    }
  90
  91    intel_batchbuffer_emit_mi_flush(intel->batch);
  92
  93    BEGIN_BATCH(6);
  94    OUT_BATCH(CMD_3D_VS_STATE << 16 | (6 - 2));
  95    OUT_RELOC(brw->vs.prog_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
  96    OUT_BATCH((0 << GEN6_VS_SAMPLER_COUNT_SHIFT) |
  97              (brw->vs.nr_surfaces << GEN6_VS_BINDING_TABLE_ENTRY_COUNT_SHIFT));
  98    OUT_BATCH(0); /* scratch space base offset */
  99    OUT_BATCH((1 << GEN6_VS_DISPATCH_START_GRF_SHIFT) |
 100              (brw->vs.prog_data->urb_read_length << GEN6_VS_URB_READ_LENGTH_SHIFT) |
 101              (0 << GEN6_VS_URB_ENTRY_READ_OFFSET_SHIFT));
 102    OUT_BATCH((0 << GEN6_VS_MAX_THREADS_SHIFT) |
 103              GEN6_VS_STATISTICS_ENABLE |
 104              GEN6_VS_ENABLE);
 105    ADVANCE_BATCH();
 106
 107    intel_batchbuffer_emit_mi_flush(intel->batch);
 108 }
 109
 110 const struct brw_tracked_state gen6_vs_state = {
 111    .dirty = {
 112       .mesa  = _NEW_TRANSFORM | _NEW_PROGRAM_CONSTANTS,
 113       .brw   = (BRW_NEW_CURBE_OFFSETS |
 114                 BRW_NEW_NR_VS_SURFACES |
 115                 BRW_NEW_URB_FENCE |
 116                 BRW_NEW_CONTEXT),
 117       .cache = CACHE_NEW_VS_PROG
 118    },
 119    .emit = upload_vs_state,
 120 };