src/mesa/drivers/dri/i965/gen6_wm_state.c

   1 /*
   2  * Copyright © 2009 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include "brw_context.h"
  29 #include "brw_state.h"
  30 #include "brw_defines.h"
  31 #include "brw_util.h"
  32 #include "brw_wm.h"
  33 #include "program/program.h"
  34 #include "program/prog_parameter.h"
  35 #include "program/prog_statevars.h"
  36 #include "intel_batchbuffer.h"
  37
  38 static void
  39 gen6_upload_wm_push_constants(struct brw_context *brw)
  40 {
  41    struct gl_context *ctx = &brw->ctx;
  42    /* BRW_NEW_FRAGMENT_PROGRAM */
  43    const struct brw_fragment_program *fp =
  44       brw_fragment_program_const(brw->fragment_program);
  45    /* CACHE_NEW_WM_PROG */
  46    const struct brw_wm_prog_data *prog_data = brw->wm.prog_data;
  47
  48    /* Updates the ParameterValues[i] pointers for all parameters of the
  49     * basic type of PROGRAM_STATE_VAR.
  50     */
  51    /* XXX: Should this happen somewhere before to get our state flag set? */
  52    _mesa_load_state_parameters(ctx, fp->program.Base.Parameters);
  53
  54    if (prog_data->nr_params == 0) {
  55       brw->wm.base.push_const_size = 0;
  56    } else {
  57       float *constants;
  58       unsigned int i;
  59
  60       constants = brw_state_batch(brw, AUB_TRACE_WM_CONSTANTS,
  61                                   prog_data->nr_params * sizeof(float),
  62                                   32, &brw->wm.base.push_const_offset);
  63
  64       for (i = 0; i < prog_data->nr_params; i++) {
  65          constants[i] = *prog_data->param[i];
  66       }
  67
  68       if (0) {
  69          printf("WM constants:\n");
  70          for (i = 0; i < prog_data->nr_params; i++) {
  71             if ((i & 7) == 0)
  72                printf("g%d: ", prog_data->first_curbe_grf + i / 8);
  73             printf("%8f ", constants[i]);
  74             if ((i & 7) == 7)
  75                printf("\n");
  76          }
  77          if ((i & 7) != 0)
  78             printf("\n");
  79          printf("\n");
  80       }
  81
  82       brw->wm.base.push_const_size = ALIGN(prog_data->nr_params, 8) / 8;
  83    }
  84 }
  85
  86 const struct brw_tracked_state gen6_wm_push_constants = {
  87    .dirty = {
  88       .mesa  = _NEW_PROGRAM_CONSTANTS,
  89       .brw   = (BRW_NEW_BATCH |
  90                 BRW_NEW_FRAGMENT_PROGRAM),
  91       .cache = CACHE_NEW_WM_PROG,
  92    },
  93    .emit = gen6_upload_wm_push_constants,
  94 };
  95
  96 static void
  97 upload_wm_state(struct brw_context *brw)
  98 {
  99    struct gl_context *ctx = &brw->ctx;
 100    const struct brw_fragment_program *fp =
 101       brw_fragment_program_const(brw->fragment_program);
 102    uint32_t dw2, dw4, dw5, dw6;
 103
 104    /* _NEW_BUFFERS */
 105    bool multisampled_fbo = ctx->DrawBuffer->Visual.samples > 1;
 106
 107     /* CACHE_NEW_WM_PROG */
 108    if (brw->wm.prog_data->nr_params == 0) {
 109       /* Disable the push constant buffers. */
 110       BEGIN_BATCH(5);
 111       OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 | (5 - 2));
 112       OUT_BATCH(0);
 113       OUT_BATCH(0);
 114       OUT_BATCH(0);
 115       OUT_BATCH(0);
 116       ADVANCE_BATCH();
 117    } else {
 118       BEGIN_BATCH(5);
 119       OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 |
 120                 GEN6_CONSTANT_BUFFER_0_ENABLE |
 121                 (5 - 2));
 122       /* Pointer to the WM constant buffer.  Covered by the set of
 123        * state flags from gen6_upload_wm_push_constants.
 124        */
 125       OUT_BATCH(brw->wm.base.push_const_offset +
 126                 brw->wm.base.push_const_size - 1);
 127       OUT_BATCH(0);
 128       OUT_BATCH(0);
 129       OUT_BATCH(0);
 130       ADVANCE_BATCH();
 131    }
 132
 133    dw2 = dw4 = dw5 = dw6 = 0;
 134    dw4 |= GEN6_WM_STATISTICS_ENABLE;
 135    dw5 |= GEN6_WM_LINE_AA_WIDTH_1_0;
 136    dw5 |= GEN6_WM_LINE_END_CAP_AA_WIDTH_0_5;
 137
 138    /* Use ALT floating point mode for ARB fragment programs, because they
 139     * require 0^0 == 1.  Even though _CurrentFragmentProgram is used for
 140     * rendering, CurrentFragmentProgram is used for this check to
 141     * differentiate between the GLSL and non-GLSL cases.
 142     */
 143    if (ctx->Shader.CurrentProgram[MESA_SHADER_FRAGMENT] == NULL)
 144       dw2 |= GEN6_WM_FLOATING_POINT_MODE_ALT;
 145
 146    /* CACHE_NEW_SAMPLER */
 147    dw2 |= (ALIGN(brw->wm.base.sampler_count, 4) / 4) <<
 148            GEN6_WM_SAMPLER_COUNT_SHIFT;
 149
 150    /* CACHE_NEW_WM_PROG */
 151    dw2 |= ((brw->wm.prog_data->base.binding_table.size_bytes / 4) <<
 152            GEN6_WM_BINDING_TABLE_ENTRY_COUNT_SHIFT);
 153
 154    dw5 |= (brw->max_wm_threads - 1) << GEN6_WM_MAX_THREADS_SHIFT;
 155
 156    /* CACHE_NEW_WM_PROG */
 157
 158    /* In case of non 1x per sample shading, only one of SIMD8 and SIMD16
 159     * should be enabled. We do 'SIMD16 only' dispatch if a SIMD16 shader
 160     * is successfully compiled. In majority of the cases that bring us
 161     * better performance than 'SIMD8 only' dispatch.
 162     */
 163    int min_inv_per_frag =
 164       _mesa_get_min_invocations_per_fragment(ctx, brw->fragment_program, false);
 165    assert(min_inv_per_frag >= 1);
 166
 167    if (brw->wm.prog_data->prog_offset_16) {
 168       dw5 |= GEN6_WM_16_DISPATCH_ENABLE;
 169
 170       if (min_inv_per_frag == 1) {
 171          dw5 |= GEN6_WM_8_DISPATCH_ENABLE;
 172          dw4 |= (brw->wm.prog_data->first_curbe_grf <<
 173                  GEN6_WM_DISPATCH_START_GRF_SHIFT_0);
 174          dw4 |= (brw->wm.prog_data->first_curbe_grf_16 <<
 175                  GEN6_WM_DISPATCH_START_GRF_SHIFT_2);
 176       } else
 177          dw4 |= (brw->wm.prog_data->first_curbe_grf_16 <<
 178                 GEN6_WM_DISPATCH_START_GRF_SHIFT_0);
 179    }
 180    else {
 181       dw5 |= GEN6_WM_8_DISPATCH_ENABLE;
 182       dw4 |= (brw->wm.prog_data->first_curbe_grf <<
 183               GEN6_WM_DISPATCH_START_GRF_SHIFT_0);
 184    }
 185
 186    /* CACHE_NEW_WM_PROG | _NEW_COLOR */
 187    if (brw->wm.prog_data->dual_src_blend &&
 188        (ctx->Color.BlendEnabled & 1) &&
 189        ctx->Color.Blend[0]._UsesDualSrc) {
 190       dw5 |= GEN6_WM_DUAL_SOURCE_BLEND_ENABLE;
 191    }
 192
 193    /* _NEW_LINE */
 194    if (ctx->Line.StippleFlag)
 195       dw5 |= GEN6_WM_LINE_STIPPLE_ENABLE;
 196
 197    /* _NEW_POLYGON */
 198    if (ctx->Polygon.StippleFlag)
 199       dw5 |= GEN6_WM_POLYGON_STIPPLE_ENABLE;
 200
 201    /* BRW_NEW_FRAGMENT_PROGRAM */
 202    if (fp->program.Base.InputsRead & VARYING_BIT_POS)
 203       dw5 |= GEN6_WM_USES_SOURCE_DEPTH | GEN6_WM_USES_SOURCE_W;
 204    if (fp->program.Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH))
 205       dw5 |= GEN6_WM_COMPUTED_DEPTH;
 206    /* CACHE_NEW_WM_PROG */
 207    dw6 |= brw->wm.prog_data->barycentric_interp_modes <<
 208       GEN6_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT;
 209
 210    /* _NEW_COLOR, _NEW_MULTISAMPLE */
 211    if (fp->program.UsesKill || ctx->Color.AlphaEnabled ||
 212        ctx->Multisample.SampleAlphaToCoverage ||
 213        brw->wm.prog_data->uses_omask)
 214       dw5 |= GEN6_WM_KILL_ENABLE;
 215
 216    if (brw_color_buffer_write_enabled(brw) ||
 217        dw5 & (GEN6_WM_KILL_ENABLE | GEN6_WM_COMPUTED_DEPTH)) {
 218       dw5 |= GEN6_WM_DISPATCH_ENABLE;
 219    }
 220
 221    /* From the SNB PRM, volume 2 part 1, page 278:
 222     * "This bit is inserted in the PS payload header and made available to
 223     * the DataPort (either via the message header or via header bypass) to
 224     * indicate that oMask data (one or two phases) is included in Render
 225     * Target Write messages. If present, the oMask data is used to mask off
 226     * samples."
 227     */
 228     if(brw->wm.prog_data->uses_omask)
 229       dw5 |= GEN6_WM_OMASK_TO_RENDER_TARGET;
 230
 231    /* CACHE_NEW_WM_PROG */
 232    dw6 |= brw->wm.prog_data->num_varying_inputs <<
 233       GEN6_WM_NUM_SF_OUTPUTS_SHIFT;
 234    if (multisampled_fbo) {
 235       /* _NEW_MULTISAMPLE */
 236       if (ctx->Multisample.Enabled)
 237          dw6 |= GEN6_WM_MSRAST_ON_PATTERN;
 238       else
 239          dw6 |= GEN6_WM_MSRAST_OFF_PIXEL;
 240
 241       if (min_inv_per_frag > 1)
 242          dw6 |= GEN6_WM_MSDISPMODE_PERSAMPLE;
 243       else {
 244          dw6 |= GEN6_WM_MSDISPMODE_PERPIXEL;
 245
 246          /* From the Sandy Bridge PRM, Vol 2 part 1, 7.7.1 ("Pixel Grouping
 247           * (Dispatch Size) Control"), p.334:
 248           *
 249           *     Note: in the table below, the Valid column indicates which
 250           *     products that combination is supported on. Combinations of
 251           *     dispatch enables not listed in the table are not available on
 252           *     any product.
 253           *
 254           *     A: Valid on all products
 255           *
 256           *     B: Not valid on [DevSNB] if 4x PERPIXEL mode with pixel shader
 257           *     computed depth.
 258           *
 259           *     D: Valid on all products, except when in non-1x PERSAMPLE mode
 260           *     (applies to [DevSNB+] only). Not valid on [DevSNB] if 4x
 261           *     PERPIXEL mode with pixel shader computed depth.
 262           *
 263           *     E: Not valid on [DevSNB] if 4x PERPIXEL mode with pixel shader
 264           *     computed depth.
 265           *
 266           *     F: Valid on all products, except not valid on [DevSNB] if 4x
 267           *     PERPIXEL mode with pixel shader computed depth.
 268           *
 269           * In the table that follows, the only entry with "A" in the Valid
 270           * column is the entry where only 8 pixel dispatch is enabled.
 271           * Therefore, when we are in PERPIXEL mode with pixel shader computed
 272           * depth, we need to disable SIMD16 dispatch.
 273           */
 274          if (dw5 & GEN6_WM_COMPUTED_DEPTH)
 275             dw5 &= ~GEN6_WM_16_DISPATCH_ENABLE;
 276       }
 277    } else {
 278       dw6 |= GEN6_WM_MSRAST_OFF_PIXEL;
 279       dw6 |= GEN6_WM_MSDISPMODE_PERSAMPLE;
 280    }
 281
 282    /* _NEW_BUFFERS, _NEW_MULTISAMPLE */
 283    /* From the SNB PRM, volume 2 part 1, page 281:
 284     * "If the PS kernel does not need the Position XY Offsets
 285     * to compute a Position XY value, then this field should be
 286     * programmed to POSOFFSET_NONE."
 287     *
 288     * "SW Recommendation: If the PS kernel needs the Position Offsets
 289     * to compute a Position XY value, this field should match Position
 290     * ZW Interpolation Mode to ensure a consistent position.xyzw
 291     * computation."
 292     * We only require XY sample offsets. So, this recommendation doesn't
 293     * look useful at the moment. We might need this in future.
 294     */
 295    if (brw->wm.prog_data->uses_pos_offset)
 296       dw6 |= GEN6_WM_POSOFFSET_SAMPLE;
 297    else
 298       dw6 |= GEN6_WM_POSOFFSET_NONE;
 299
 300    BEGIN_BATCH(9);
 301    OUT_BATCH(_3DSTATE_WM << 16 | (9 - 2));
 302    if (brw->wm.prog_data->prog_offset_16 && min_inv_per_frag > 1)
 303       OUT_BATCH(brw->wm.base.prog_offset + brw->wm.prog_data->prog_offset_16);
 304    else
 305       OUT_BATCH(brw->wm.base.prog_offset);
 306    OUT_BATCH(dw2);
 307    if (brw->wm.prog_data->total_scratch) {
 308       OUT_RELOC(brw->wm.base.scratch_bo,
 309                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 310                 ffs(brw->wm.prog_data->total_scratch) - 11);
 311    } else {
 312       OUT_BATCH(0);
 313    }
 314    OUT_BATCH(dw4);
 315    OUT_BATCH(dw5);
 316    OUT_BATCH(dw6);
 317    OUT_BATCH(0); /* kernel 1 pointer */
 318    /* kernel 2 pointer */
 319    OUT_BATCH(brw->wm.base.prog_offset + brw->wm.prog_data->prog_offset_16);
 320    ADVANCE_BATCH();
 321 }
 322
 323 const struct brw_tracked_state gen6_wm_state = {
 324    .dirty = {
 325       .mesa  = (_NEW_LINE |
 326                 _NEW_COLOR |
 327                 _NEW_BUFFERS |
 328                 _NEW_PROGRAM_CONSTANTS |
 329                 _NEW_POLYGON |
 330                 _NEW_MULTISAMPLE),
 331       .brw   = (BRW_NEW_FRAGMENT_PROGRAM |
 332                 BRW_NEW_BATCH |
 333                 BRW_NEW_PUSH_CONSTANT_ALLOCATION),
 334       .cache = (CACHE_NEW_SAMPLER |
 335                 CACHE_NEW_WM_PROG)
 336    },
 337    .emit = upload_wm_state,
 338 };