src/mesa/drivers/dri/i965/gen7_blorp.c

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <assert.h>
  25
  26 #include "intel_batchbuffer.h"
  27 #include "intel_mipmap_tree.h"
  28
  29 #include "brw_context.h"
  30 #include "brw_defines.h"
  31 #include "brw_state.h"
  32
  33 #include "blorp_priv.h"
  34
  35
  36 /* 3DSTATE_DEPTH_STENCIL_STATE_POINTERS
  37  *
  38  * The offset is relative to CMD_STATE_BASE_ADDRESS.DynamicStateBaseAddress.
  39  */
  40 static void
  41 gen7_blorp_emit_depth_stencil_state_pointers(struct brw_context *brw,
  42                                              uint32_t depthstencil_offset)
  43 {
  44    BEGIN_BATCH(2);
  45    OUT_BATCH(_3DSTATE_DEPTH_STENCIL_STATE_POINTERS << 16 | (2 - 2));
  46    OUT_BATCH(depthstencil_offset | 1);
  47    ADVANCE_BATCH();
  48 }
  49
  50
  51 /* Hardware seems to try to fetch the constants even though the corresponding
  52  * stage gets disabled. Therefore make sure the settings for the constant
  53  * buffer are valid.
  54  */
  55 static void
  56 gen7_blorp_disable_constant_state(struct brw_context *brw,
  57                                        unsigned opcode)
  58 {
  59    BEGIN_BATCH(7);
  60    OUT_BATCH(opcode << 16 | (7 - 2));
  61    OUT_BATCH(0);
  62    OUT_BATCH(0);
  63    OUT_BATCH(0);
  64    OUT_BATCH(0);
  65    OUT_BATCH(0);
  66    OUT_BATCH(0);
  67    ADVANCE_BATCH();
  68 }
  69
  70 /* 3DSTATE_VS
  71  *
  72  * Disable vertex shader.
  73  */
  74 static void
  75 gen7_blorp_emit_vs_disable(struct brw_context *brw)
  76 {
  77    BEGIN_BATCH(6);
  78    OUT_BATCH(_3DSTATE_VS << 16 | (6 - 2));
  79    OUT_BATCH(0);
  80    OUT_BATCH(0);
  81    OUT_BATCH(0);
  82    OUT_BATCH(0);
  83    OUT_BATCH(0);
  84    ADVANCE_BATCH();
  85 }
  86
  87
  88 /* 3DSTATE_HS
  89  *
  90  * Disable the hull shader.
  91  */
  92 static void
  93 gen7_blorp_emit_hs_disable(struct brw_context *brw)
  94 {
  95    BEGIN_BATCH(7);
  96    OUT_BATCH(_3DSTATE_HS << 16 | (7 - 2));
  97    OUT_BATCH(0);
  98    OUT_BATCH(0);
  99    OUT_BATCH(0);
 100    OUT_BATCH(0);
 101    OUT_BATCH(0);
 102    OUT_BATCH(0);
 103    ADVANCE_BATCH();
 104 }
 105
 106
 107 /* 3DSTATE_DS
 108  *
 109  * Disable the domain shader.
 110  */
 111 static void
 112 gen7_blorp_emit_ds_disable(struct brw_context *brw)
 113 {
 114    BEGIN_BATCH(6);
 115    OUT_BATCH(_3DSTATE_DS << 16 | (6 - 2));
 116    OUT_BATCH(0);
 117    OUT_BATCH(0);
 118    OUT_BATCH(0);
 119    OUT_BATCH(0);
 120    OUT_BATCH(0);
 121    ADVANCE_BATCH();
 122 }
 123
 124 /* 3DSTATE_GS
 125  *
 126  * Disable the geometry shader.
 127  */
 128 static void
 129 gen7_blorp_emit_gs_disable(struct brw_context *brw)
 130 {
 131    /**
 132     * From Graphics BSpec: 3D-Media-GPGPU Engine > 3D Pipeline Stages >
 133     * Geometry > Geometry Shader > State:
 134     *
 135     *     "Note: Because of corruption in IVB:GT2, software needs to flush the
 136     *     whole fixed function pipeline when the GS enable changes value in
 137     *     the 3DSTATE_GS."
 138     *
 139     * The hardware architects have clarified that in this context "flush the
 140     * whole fixed function pipeline" means to emit a PIPE_CONTROL with the "CS
 141     * Stall" bit set.
 142     */
 143    if (brw->gen < 8 && !brw->is_haswell && brw->gt == 2 && brw->gs.enabled)
 144       gen7_emit_cs_stall_flush(brw);
 145
 146    BEGIN_BATCH(7);
 147    OUT_BATCH(_3DSTATE_GS << 16 | (7 - 2));
 148    OUT_BATCH(0);
 149    OUT_BATCH(0);
 150    OUT_BATCH(0);
 151    OUT_BATCH(0);
 152    OUT_BATCH(0);
 153    OUT_BATCH(0);
 154    ADVANCE_BATCH();
 155    brw->gs.enabled = false;
 156 }
 157
 158 /* 3DSTATE_STREAMOUT
 159  *
 160  * Disable streamout.
 161  */
 162 static void
 163 gen7_blorp_emit_streamout_disable(struct brw_context *brw)
 164 {
 165    BEGIN_BATCH(3);
 166    OUT_BATCH(_3DSTATE_STREAMOUT << 16 | (3 - 2));
 167    OUT_BATCH(0);
 168    OUT_BATCH(0);
 169    ADVANCE_BATCH();
 170 }
 171
 172
 173 static void
 174 gen7_blorp_emit_sf_config(struct brw_context *brw,
 175                           const struct brw_blorp_params *params)
 176 {
 177    /* 3DSTATE_SF
 178     *
 179     * Disable ViewportTransformEnable (dw1.1)
 180     *
 181     * From the SandyBridge PRM, Volume 2, Part 1, Section 1.3, "3D
 182     * Primitives Overview":
 183     *     RECTLIST: Viewport Mapping must be DISABLED (as is typical with the
 184     *     use of screen- space coordinates).
 185     *
 186     * A solid rectangle must be rendered, so set FrontFaceFillMode (dw1.6:5)
 187     * and BackFaceFillMode (dw1.4:3) to SOLID(0).
 188     *
 189     * From the Sandy Bridge PRM, Volume 2, Part 1, Section
 190     * 6.4.1.1 3DSTATE_SF, Field FrontFaceFillMode:
 191     *     SOLID: Any triangle or rectangle object found to be front-facing
 192     *     is rendered as a solid object. This setting is required when
 193     *     (rendering rectangle (RECTLIST) objects.
 194     */
 195    {
 196       BEGIN_BATCH(7);
 197       OUT_BATCH(_3DSTATE_SF << 16 | (7 - 2));
 198       OUT_BATCH(params->depth_format <<
 199                 GEN7_SF_DEPTH_BUFFER_SURFACE_FORMAT_SHIFT);
 200       OUT_BATCH(params->dst.surf.samples > 1 ? GEN6_SF_MSRAST_ON_PATTERN : 0);
 201       OUT_BATCH(0);
 202       OUT_BATCH(0);
 203       OUT_BATCH(0);
 204       OUT_BATCH(0);
 205       ADVANCE_BATCH();
 206    }
 207
 208    /* 3DSTATE_SBE */
 209    {
 210       const unsigned num_varyings =
 211          params->wm_prog_data ? params->wm_prog_data->num_varying_inputs : 0;
 212       const unsigned urb_read_length =
 213          brw_blorp_get_urb_length(params->wm_prog_data);
 214
 215       BEGIN_BATCH(14);
 216       OUT_BATCH(_3DSTATE_SBE << 16 | (14 - 2));
 217
 218       /* There is no need for swizzling (GEN7_SBE_SWIZZLE_ENABLE). All the
 219        * vertex data coming from vertex fetcher is taken as unmodified
 220        * (i.e., passed through). Vertex shader state is disabled and vertex
 221        * fetcher builds complete vertex entries including VUE header.
 222        * This is for unknown reason really needed to be disabled when more
 223        * than one vec4 worth of vertex attributes are needed.
 224        */
 225       OUT_BATCH(num_varyings << GEN7_SBE_NUM_OUTPUTS_SHIFT |
 226                 urb_read_length << GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT |
 227                 BRW_SF_URB_ENTRY_READ_OFFSET <<
 228                    GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT);
 229       for (int i = 0; i < 9; ++i)
 230          OUT_BATCH(0);
 231       OUT_BATCH(params->wm_prog_data ? params->wm_prog_data->flat_inputs : 0);
 232       OUT_BATCH(0);
 233       OUT_BATCH(0);
 234       ADVANCE_BATCH();
 235    }
 236 }
 237
 238
 239 /**
 240  * Disable thread dispatch (dw5.19) and enable the HiZ op.
 241  */
 242 static void
 243 gen7_blorp_emit_wm_config(struct brw_context *brw,
 244                           const struct brw_blorp_params *params)
 245 {
 246    const struct brw_blorp_prog_data *prog_data = params->wm_prog_data;
 247    uint32_t dw1 = 0, dw2 = 0;
 248
 249    switch (params->hiz_op) {
 250    case GEN6_HIZ_OP_DEPTH_CLEAR:
 251       dw1 |= GEN7_WM_DEPTH_CLEAR;
 252       break;
 253    case GEN6_HIZ_OP_DEPTH_RESOLVE:
 254       dw1 |= GEN7_WM_DEPTH_RESOLVE;
 255       break;
 256    case GEN6_HIZ_OP_HIZ_RESOLVE:
 257       dw1 |= GEN7_WM_HIERARCHICAL_DEPTH_RESOLVE;
 258       break;
 259    case GEN6_HIZ_OP_NONE:
 260       break;
 261    default:
 262       unreachable("not reached");
 263    }
 264    dw1 |= 0 << GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT; /* No interp */
 265
 266    if (params->wm_prog_data)
 267       dw1 |= GEN7_WM_DISPATCH_ENABLE; /* We are rendering */
 268
 269    if (params->src.bo)
 270       dw1 |= GEN7_WM_KILL_ENABLE; /* TODO: temporarily smash on */
 271
 272    if (params->dst.surf.samples > 1) {
 273       dw1 |= GEN7_WM_MSRAST_ON_PATTERN;
 274       if (prog_data && prog_data->persample_msaa_dispatch)
 275          dw2 |= GEN7_WM_MSDISPMODE_PERSAMPLE;
 276       else
 277          dw2 |= GEN7_WM_MSDISPMODE_PERPIXEL;
 278    } else {
 279       dw1 |= GEN7_WM_MSRAST_OFF_PIXEL;
 280       dw2 |= GEN7_WM_MSDISPMODE_PERSAMPLE;
 281    }
 282
 283    BEGIN_BATCH(3);
 284    OUT_BATCH(_3DSTATE_WM << 16 | (3 - 2));
 285    OUT_BATCH(dw1);
 286    OUT_BATCH(dw2);
 287    ADVANCE_BATCH();
 288 }
 289
 290
 291 /**
 292  * 3DSTATE_PS
 293  *
 294  * Pixel shader dispatch is disabled above in 3DSTATE_WM, dw1.29. Despite
 295  * that, thread dispatch info must still be specified.
 296  *     - Maximum Number of Threads (dw4.24:31) must be nonzero, as the
 297  *       valid range for this field is [0x3, 0x2f].
 298  *     - A dispatch mode must be given; that is, at least one of the
 299  *       "N Pixel Dispatch Enable" (N=8,16,32) fields must be set. This was
 300  *       discovered through simulator error messages.
 301  */
 302 static void
 303 gen7_blorp_emit_ps_config(struct brw_context *brw,
 304                           const struct brw_blorp_params *params)
 305 {
 306    const struct brw_blorp_prog_data *prog_data = params->wm_prog_data;
 307    uint32_t dw2, dw4, dw5, ksp0, ksp2;
 308    const int max_threads_shift = brw->is_haswell ?
 309       HSW_PS_MAX_THREADS_SHIFT : IVB_PS_MAX_THREADS_SHIFT;
 310
 311    dw2 = dw4 = dw5 = ksp0 = ksp2 = 0;
 312    dw4 |= (brw->max_wm_threads - 1) << max_threads_shift;
 313
 314    if (brw->is_haswell)
 315       dw4 |= SET_FIELD(1, HSW_PS_SAMPLE_MASK); /* 1 sample for now */
 316    if (params->wm_prog_data) {
 317       dw5 |= prog_data->first_curbe_grf_0 << GEN7_PS_DISPATCH_START_GRF_SHIFT_0;
 318       dw5 |= prog_data->first_curbe_grf_2 << GEN7_PS_DISPATCH_START_GRF_SHIFT_2;
 319
 320       ksp0 = params->wm_prog_kernel;
 321       ksp2 = params->wm_prog_kernel + params->wm_prog_data->ksp_offset_2;
 322
 323       if (params->wm_prog_data->dispatch_8)
 324          dw4 |= GEN7_PS_8_DISPATCH_ENABLE;
 325       if (params->wm_prog_data->dispatch_16)
 326          dw4 |= GEN7_PS_16_DISPATCH_ENABLE;
 327       if (params->wm_prog_data->num_varying_inputs)
 328          dw4 |= GEN7_PS_ATTRIBUTE_ENABLE;
 329    } else {
 330       /* The hardware gets angry if we don't enable at least one dispatch
 331        * mode, so just enable 16-pixel dispatch if we don't have a program.
 332        */
 333       dw4 |= GEN7_PS_16_DISPATCH_ENABLE;
 334    }
 335
 336    if (params->src.bo)
 337       dw2 |= 1 << GEN7_PS_SAMPLER_COUNT_SHIFT; /* Up to 4 samplers */
 338
 339    dw4 |= params->fast_clear_op;
 340
 341    BEGIN_BATCH(8);
 342    OUT_BATCH(_3DSTATE_PS << 16 | (8 - 2));
 343    OUT_BATCH(ksp0);
 344    OUT_BATCH(dw2);
 345    OUT_BATCH(0);
 346    OUT_BATCH(dw4);
 347    OUT_BATCH(dw5);
 348    OUT_BATCH(0); /* kernel 1 pointer */
 349    OUT_BATCH(ksp2);
 350    ADVANCE_BATCH();
 351 }
 352
 353
 354 static void
 355 gen7_blorp_emit_depth_stencil_config(struct brw_context *brw,
 356                                      const struct brw_blorp_params *params)
 357 {
 358    const uint8_t mocs = GEN7_MOCS_L3;
 359    uint32_t surftype;
 360
 361    switch (params->depth.surf.dim) {
 362    case ISL_SURF_DIM_1D:
 363       surftype = BRW_SURFACE_1D;
 364       break;
 365    case ISL_SURF_DIM_2D:
 366       surftype = BRW_SURFACE_2D;
 367       break;
 368    case ISL_SURF_DIM_3D:
 369       surftype = BRW_SURFACE_3D;
 370       break;
 371    }
 372
 373    /* 3DSTATE_DEPTH_BUFFER */
 374    {
 375       brw_emit_depth_stall_flushes(brw);
 376
 377       unsigned depth = MAX2(params->depth.surf.logical_level0_px.depth,
 378                             params->depth.surf.logical_level0_px.array_len);
 379
 380       BEGIN_BATCH(7);
 381       OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
 382       OUT_BATCH((params->depth.surf.row_pitch - 1) |
 383                 params->depth_format << 18 |
 384                 1 << 22 | /* hiz enable */
 385                 1 << 28 | /* depth write */
 386                 surftype << 29);
 387       OUT_RELOC(params->depth.bo,
 388                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 389                 params->depth.offset);
 390       OUT_BATCH((params->depth.surf.logical_level0_px.width - 1) << 4 |
 391                 (params->depth.surf.logical_level0_px.height - 1) << 18 |
 392                 params->depth.view.base_level);
 393       OUT_BATCH(((depth - 1) << 21) |
 394                 (params->depth.view.base_array_layer << 10) |
 395                 mocs);
 396       OUT_BATCH(0);
 397       OUT_BATCH((depth - 1) << 21);
 398       ADVANCE_BATCH();
 399    }
 400
 401    /* 3DSTATE_HIER_DEPTH_BUFFER */
 402    {
 403       BEGIN_BATCH(3);
 404       OUT_BATCH((GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
 405       OUT_BATCH((mocs << 25) |
 406                 (params->depth.aux_surf.row_pitch - 1));
 407       OUT_RELOC(params->depth.aux_bo,
 408                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 409                 params->depth.aux_offset);
 410       ADVANCE_BATCH();
 411    }
 412
 413    /* 3DSTATE_STENCIL_BUFFER */
 414    {
 415       BEGIN_BATCH(3);
 416       OUT_BATCH((GEN7_3DSTATE_STENCIL_BUFFER << 16) | (3 - 2));
 417       OUT_BATCH(0);
 418       OUT_BATCH(0);
 419       ADVANCE_BATCH();
 420    }
 421 }
 422
 423
 424 static void
 425 gen7_blorp_emit_depth_disable(struct brw_context *brw)
 426 {
 427    brw_emit_depth_stall_flushes(brw);
 428
 429    BEGIN_BATCH(7);
 430    OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
 431    OUT_BATCH(BRW_DEPTHFORMAT_D32_FLOAT << 18 | (BRW_SURFACE_NULL << 29));
 432    OUT_BATCH(0);
 433    OUT_BATCH(0);
 434    OUT_BATCH(0);
 435    OUT_BATCH(0);
 436    OUT_BATCH(0);
 437    ADVANCE_BATCH();
 438
 439    BEGIN_BATCH(3);
 440    OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (3 - 2));
 441    OUT_BATCH(0);
 442    OUT_BATCH(0);
 443    ADVANCE_BATCH();
 444
 445    BEGIN_BATCH(3);
 446    OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (3 - 2));
 447    OUT_BATCH(0);
 448    OUT_BATCH(0);
 449    ADVANCE_BATCH();
 450 }
 451
 452
 453 /**
 454  * \copydoc gen6_blorp_exec()
 455  */
 456 void
 457 gen7_blorp_exec(struct brw_context *brw,
 458                 const struct brw_blorp_params *params)
 459 {
 460    if (brw->gen >= 8)
 461       return;
 462
 463    uint32_t cc_blend_state_offset = 0;
 464    uint32_t cc_state_offset = 0;
 465    uint32_t depthstencil_offset;
 466    uint32_t wm_bind_bo_offset = 0;
 467
 468    brw_upload_state_base_address(brw);
 469    gen6_blorp_emit_vertices(brw, params);
 470    gen7_blorp_emit_urb_config(brw, params);
 471    if (params->wm_prog_data) {
 472       cc_blend_state_offset = gen6_blorp_emit_blend_state(brw, params);
 473       cc_state_offset = gen6_blorp_emit_cc_state(brw);
 474       gen7_blorp_emit_blend_state_pointer(brw, cc_blend_state_offset);
 475       gen7_blorp_emit_cc_state_pointer(brw, cc_state_offset);
 476    }
 477    depthstencil_offset = gen6_blorp_emit_depth_stencil_state(brw, params);
 478    gen7_blorp_emit_depth_stencil_state_pointers(brw, depthstencil_offset);
 479
 480    gen7_blorp_disable_constant_state(brw, _3DSTATE_CONSTANT_VS);
 481    gen7_blorp_disable_constant_state(brw, _3DSTATE_CONSTANT_HS);
 482    gen7_blorp_disable_constant_state(brw, _3DSTATE_CONSTANT_DS);
 483    gen7_blorp_disable_constant_state(brw, _3DSTATE_CONSTANT_GS);
 484    gen7_blorp_disable_constant_state(brw, _3DSTATE_CONSTANT_PS);
 485
 486    if (brw->use_resource_streamer)
 487       gen7_disable_hw_binding_tables(brw);
 488    if (params->wm_prog_data) {
 489       uint32_t wm_surf_offset_renderbuffer;
 490       uint32_t wm_surf_offset_texture = 0;
 491
 492       wm_surf_offset_renderbuffer =
 493          brw_blorp_emit_surface_state(brw, &params->dst,
 494                                       I915_GEM_DOMAIN_RENDER,
 495                                       I915_GEM_DOMAIN_RENDER,
 496                                       true /* is_render_target */);
 497       if (params->src.bo) {
 498          wm_surf_offset_texture =
 499             brw_blorp_emit_surface_state(brw, &params->src,
 500                                          I915_GEM_DOMAIN_SAMPLER, 0,
 501                                          false /* is_render_target */);
 502       }
 503       wm_bind_bo_offset =
 504          gen6_blorp_emit_binding_table(brw,
 505                                        wm_surf_offset_renderbuffer,
 506                                        wm_surf_offset_texture);
 507       gen7_blorp_emit_binding_table_pointers_ps(brw, wm_bind_bo_offset);
 508    }
 509
 510    if (params->src.bo) {
 511       const uint32_t sampler_offset =
 512          gen6_blorp_emit_sampler_state(brw, BRW_MAPFILTER_LINEAR, 0, true);
 513       gen7_blorp_emit_sampler_state_pointers_ps(brw, sampler_offset);
 514    }
 515
 516    gen6_emit_3dstate_multisample(brw, params->dst.surf.samples);
 517    gen6_emit_3dstate_sample_mask(brw,
 518                                  params->dst.surf.samples > 1 ?
 519                                  (1 << params->dst.surf.samples) - 1 : 1);
 520
 521    gen7_blorp_emit_vs_disable(brw);
 522    gen7_blorp_emit_hs_disable(brw);
 523    gen7_blorp_emit_te_disable(brw);
 524    gen7_blorp_emit_ds_disable(brw);
 525    gen7_blorp_emit_gs_disable(brw);
 526    gen7_blorp_emit_streamout_disable(brw);
 527    gen6_blorp_emit_clip_disable(brw);
 528    gen7_blorp_emit_sf_config(brw, params);
 529    gen7_blorp_emit_wm_config(brw, params);
 530    gen7_blorp_emit_ps_config(brw, params);
 531    gen7_blorp_emit_cc_viewport(brw);
 532
 533    if (params->depth.bo)
 534       gen7_blorp_emit_depth_stencil_config(brw, params);
 535    else
 536       gen7_blorp_emit_depth_disable(brw);
 537    gen7_blorp_emit_clear_params(brw, params);
 538    gen6_blorp_emit_drawing_rectangle(brw, params);
 539    gen7_blorp_emit_primitive(brw, params);
 540 }