src/mesa/drivers/dri/i965/gen7_blorp.cpp

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <assert.h>
  25
  26 #include "intel_batchbuffer.h"
  27 #include "intel_fbo.h"
  28 #include "intel_mipmap_tree.h"
  29
  30 #include "brw_context.h"
  31 #include "brw_defines.h"
  32 #include "brw_state.h"
  33
  34 #include "brw_blorp.h"
  35 #include "gen7_blorp.h"
  36
  37
  38 /* 3DSTATE_URB_VS
  39  * 3DSTATE_URB_HS
  40  * 3DSTATE_URB_DS
  41  * 3DSTATE_URB_GS
  42  *
  43  * If the 3DSTATE_URB_VS is emitted, than the others must be also. From the
  44  * BSpec, Volume 2a "3D Pipeline Overview", Section 1.7.1 3DSTATE_URB_VS:
  45  *     3DSTATE_URB_HS, 3DSTATE_URB_DS, and 3DSTATE_URB_GS must also be
  46  *     programmed in order for the programming of this state to be
  47  *     valid.
  48  */
  49 static void
  50 gen7_blorp_emit_urb_config(struct brw_context *brw,
  51                            const brw_blorp_params *params)
  52 {
  53    struct intel_context *intel = &brw->intel;
  54
  55    /* The minimum valid value is 32. See 3DSTATE_URB_VS,
  56     * Dword 1.15:0 "VS Number of URB Entries".
  57     */
  58    int num_vs_entries = 32;
  59
  60    BEGIN_BATCH(2);
  61    OUT_BATCH(_3DSTATE_URB_VS << 16 | (2 - 2));
  62    OUT_BATCH(1 << GEN7_URB_ENTRY_SIZE_SHIFT |
  63              0 << GEN7_URB_STARTING_ADDRESS_SHIFT |
  64              num_vs_entries);
  65    ADVANCE_BATCH();
  66
  67    BEGIN_BATCH(2);
  68    OUT_BATCH(_3DSTATE_URB_GS << 16 | (2 - 2));
  69    OUT_BATCH(0);
  70    ADVANCE_BATCH();
  71
  72    BEGIN_BATCH(2);
  73    OUT_BATCH(_3DSTATE_URB_HS << 16 | (2 - 2));
  74    OUT_BATCH(0);
  75    ADVANCE_BATCH();
  76
  77    BEGIN_BATCH(2);
  78    OUT_BATCH(_3DSTATE_URB_DS << 16 | (2 - 2));
  79    OUT_BATCH(0);
  80    ADVANCE_BATCH();
  81 }
  82
  83
  84 /* 3DSTATE_BLEND_STATE_POINTERS */
  85 static void
  86 gen7_blorp_emit_blend_state_pointer(struct brw_context *brw,
  87                                     const brw_blorp_params *params,
  88                                     uint32_t cc_blend_state_offset)
  89 {
  90    struct intel_context *intel = &brw->intel;
  91
  92    BEGIN_BATCH(2);
  93    OUT_BATCH(_3DSTATE_BLEND_STATE_POINTERS << 16 | (2 - 2));
  94    OUT_BATCH(cc_blend_state_offset | 1);
  95    ADVANCE_BATCH();
  96 }
  97
  98
  99 /* 3DSTATE_CC_STATE_POINTERS */
 100 static void
 101 gen7_blorp_emit_cc_state_pointer(struct brw_context *brw,
 102                                  const brw_blorp_params *params,
 103                                  uint32_t cc_state_offset)
 104 {
 105    struct intel_context *intel = &brw->intel;
 106
 107    BEGIN_BATCH(2);
 108    OUT_BATCH(_3DSTATE_CC_STATE_POINTERS << 16 | (2 - 2));
 109    OUT_BATCH(cc_state_offset | 1);
 110    ADVANCE_BATCH();
 111 }
 112
 113
 114 /* 3DSTATE_DEPTH_STENCIL_STATE_POINTERS
 115  *
 116  * The offset is relative to CMD_STATE_BASE_ADDRESS.DynamicStateBaseAddress.
 117  */
 118 static void
 119 gen7_blorp_emit_depth_stencil_state_pointers(struct brw_context *brw,
 120                                              const brw_blorp_params *params,
 121                                              uint32_t depthstencil_offset)
 122 {
 123    struct intel_context *intel = &brw->intel;
 124
 125    BEGIN_BATCH(2);
 126    OUT_BATCH(_3DSTATE_DEPTH_STENCIL_STATE_POINTERS << 16 | (2 - 2));
 127    OUT_BATCH(depthstencil_offset | 1);
 128    ADVANCE_BATCH();
 129 }
 130
 131
 132 /* SURFACE_STATE for renderbuffer or texture surface (see
 133  * brw_update_renderbuffer_surface and brw_update_texture_surface)
 134  */
 135 static uint32_t
 136 gen7_blorp_emit_surface_state(struct brw_context *brw,
 137                               const brw_blorp_params *params,
 138                               const brw_blorp_surface_info *surface,
 139                               uint32_t read_domains, uint32_t write_domain)
 140 {
 141    struct intel_context *intel = &brw->intel;
 142
 143    uint32_t wm_surf_offset;
 144    uint32_t width, height;
 145    surface->get_miplevel_dims(&width, &height);
 146    if (surface->num_samples > 0) { /* TODO: wrong for 8x */
 147       width /= 2;
 148       height /= 2;
 149    }
 150    if (surface->map_stencil_as_y_tiled) {
 151       width *= 2;
 152       height /= 2;
 153    }
 154    struct intel_region *region = surface->mt->region;
 155
 156    /* TODO: handle other formats */
 157    uint32_t format = surface->map_stencil_as_y_tiled
 158       ? BRW_SURFACEFORMAT_R8_UNORM : BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
 159
 160    struct gen7_surface_state *surf = (struct gen7_surface_state *)
 161       brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, sizeof(*surf), 32,
 162                       &wm_surf_offset);
 163    memset(surf, 0, sizeof(*surf));
 164
 165    if (surface->mt->align_h == 4)
 166       surf->ss0.vertical_alignment = 1;
 167    if (surface->mt->align_w == 8)
 168       surf->ss0.horizontal_alignment = 1;
 169
 170    surf->ss0.surface_format = format;
 171    surf->ss0.surface_type = BRW_SURFACE_2D;
 172
 173    /* reloc */
 174    surf->ss1.base_addr = region->bo->offset; /* No tile offsets needed */
 175
 176    surf->ss2.width = width - 1;
 177    surf->ss2.height = height - 1;
 178
 179    uint32_t tiling = surface->map_stencil_as_y_tiled
 180       ? I915_TILING_Y : region->tiling;
 181    gen7_set_surface_tiling(surf, tiling);
 182
 183    uint32_t pitch_bytes = region->pitch * region->cpp;
 184    if (surface->map_stencil_as_y_tiled)
 185       pitch_bytes *= 2;
 186    surf->ss3.pitch = pitch_bytes - 1;
 187
 188    gen7_set_surface_num_multisamples(surf, surface->num_samples);
 189
 190    if (intel->is_haswell) {
 191       surf->ss7.shader_chanel_select_r = HSW_SCS_RED;
 192       surf->ss7.shader_chanel_select_g = HSW_SCS_GREEN;
 193       surf->ss7.shader_chanel_select_b = HSW_SCS_BLUE;
 194       surf->ss7.shader_chanel_select_a = HSW_SCS_ALPHA;
 195    }
 196
 197    /* Emit relocation to surface contents */
 198    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
 199                            wm_surf_offset +
 200                            offsetof(struct gen7_surface_state, ss1),
 201                            region->bo,
 202                            surf->ss1.base_addr - region->bo->offset,
 203                            read_domains, write_domain);
 204
 205    return wm_surf_offset;
 206 }
 207
 208
 209 /**
 210  * SAMPLER_STATE.  See gen7_update_sampler_state().
 211  */
 212 static uint32_t
 213 gen7_blorp_emit_sampler_state(struct brw_context *brw,
 214                               const brw_blorp_params *params)
 215 {
 216    uint32_t sampler_offset;
 217
 218    struct gen7_sampler_state *sampler = (struct gen7_sampler_state *)
 219       brw_state_batch(brw, AUB_TRACE_SAMPLER_STATE,
 220                       sizeof(struct gen7_sampler_state),
 221                       32, &sampler_offset);
 222    memset(sampler, 0, sizeof(*sampler));
 223
 224    sampler->ss0.min_filter = BRW_MAPFILTER_LINEAR;
 225    sampler->ss0.mip_filter = BRW_MIPFILTER_NONE;
 226    sampler->ss0.mag_filter = BRW_MAPFILTER_LINEAR;
 227
 228    sampler->ss3.r_wrap_mode = BRW_TEXCOORDMODE_CLAMP;
 229    sampler->ss3.s_wrap_mode = BRW_TEXCOORDMODE_CLAMP;
 230    sampler->ss3.t_wrap_mode = BRW_TEXCOORDMODE_CLAMP;
 231
 232    //   sampler->ss0.min_mag_neq = 1;
 233
 234    /* Set LOD bias:
 235     */
 236    sampler->ss0.lod_bias = 0;
 237
 238    sampler->ss0.lod_preclamp = 1; /* OpenGL mode */
 239    sampler->ss0.default_color_mode = 0; /* OpenGL/DX10 mode */
 240
 241    /* Set BaseMipLevel, MaxLOD, MinLOD:
 242     *
 243     * XXX: I don't think that using firstLevel, lastLevel works,
 244     * because we always setup the surface state as if firstLevel ==
 245     * level zero.  Probably have to subtract firstLevel from each of
 246     * these:
 247     */
 248    sampler->ss0.base_level = U_FIXED(0, 1);
 249
 250    sampler->ss1.max_lod = U_FIXED(0, 8);
 251    sampler->ss1.min_lod = U_FIXED(0, 8);
 252
 253    sampler->ss3.non_normalized_coord = 1;
 254
 255    sampler->ss3.address_round |= BRW_ADDRESS_ROUNDING_ENABLE_U_MIN |
 256       BRW_ADDRESS_ROUNDING_ENABLE_V_MIN |
 257       BRW_ADDRESS_ROUNDING_ENABLE_R_MIN;
 258    sampler->ss3.address_round |= BRW_ADDRESS_ROUNDING_ENABLE_U_MAG |
 259       BRW_ADDRESS_ROUNDING_ENABLE_V_MAG |
 260       BRW_ADDRESS_ROUNDING_ENABLE_R_MAG;
 261
 262    return sampler_offset;
 263 }
 264
 265
 266 /* 3DSTATE_HS
 267  *
 268  * Disable the hull shader.
 269  */
 270 static void
 271 gen7_blorp_emit_hs_disable(struct brw_context *brw,
 272                            const brw_blorp_params *params)
 273 {
 274    struct intel_context *intel = &brw->intel;
 275
 276    BEGIN_BATCH(7);
 277    OUT_BATCH(_3DSTATE_HS << 16 | (7 - 2));
 278    OUT_BATCH(0);
 279    OUT_BATCH(0);
 280    OUT_BATCH(0);
 281    OUT_BATCH(0);
 282    OUT_BATCH(0);
 283    OUT_BATCH(0);
 284    ADVANCE_BATCH();
 285 }
 286
 287
 288 /* 3DSTATE_TE
 289  *
 290  * Disable the tesselation engine.
 291  */
 292 static void
 293 gen7_blorp_emit_te_disable(struct brw_context *brw,
 294                            const brw_blorp_params *params)
 295 {
 296    struct intel_context *intel = &brw->intel;
 297
 298    BEGIN_BATCH(4);
 299    OUT_BATCH(_3DSTATE_TE << 16 | (4 - 2));
 300    OUT_BATCH(0);
 301    OUT_BATCH(0);
 302    OUT_BATCH(0);
 303    ADVANCE_BATCH();
 304 }
 305
 306
 307 /* 3DSTATE_DS
 308  *
 309  * Disable the domain shader.
 310  */
 311 static void
 312 gen7_blorp_emit_ds_disable(struct brw_context *brw,
 313                            const brw_blorp_params *params)
 314 {
 315    struct intel_context *intel = &brw->intel;
 316
 317    BEGIN_BATCH(6);
 318    OUT_BATCH(_3DSTATE_DS << 16 | (6 - 2));
 319    OUT_BATCH(0);
 320    OUT_BATCH(0);
 321    OUT_BATCH(0);
 322    OUT_BATCH(0);
 323    OUT_BATCH(0);
 324    ADVANCE_BATCH();
 325 }
 326
 327
 328 /* 3DSTATE_STREAMOUT
 329  *
 330  * Disable streamout.
 331  */
 332 static void
 333 gen7_blorp_emit_streamout_disable(struct brw_context *brw,
 334                                   const brw_blorp_params *params)
 335 {
 336    struct intel_context *intel = &brw->intel;
 337
 338    BEGIN_BATCH(3);
 339    OUT_BATCH(_3DSTATE_STREAMOUT << 16 | (3 - 2));
 340    OUT_BATCH(0);
 341    OUT_BATCH(0);
 342    ADVANCE_BATCH();
 343 }
 344
 345
 346 static void
 347 gen7_blorp_emit_sf_config(struct brw_context *brw,
 348                           const brw_blorp_params *params)
 349 {
 350    struct intel_context *intel = &brw->intel;
 351
 352    /* 3DSTATE_SF
 353     *
 354     * Disable ViewportTransformEnable (dw1.1)
 355     *
 356     * From the SandyBridge PRM, Volume 2, Part 1, Section 1.3, "3D
 357     * Primitives Overview":
 358     *     RECTLIST: Viewport Mapping must be DISABLED (as is typical with the
 359     *     use of screen- space coordinates).
 360     *
 361     * A solid rectangle must be rendered, so set FrontFaceFillMode (dw1.6:5)
 362     * and BackFaceFillMode (dw1.4:3) to SOLID(0).
 363     *
 364     * From the Sandy Bridge PRM, Volume 2, Part 1, Section
 365     * 6.4.1.1 3DSTATE_SF, Field FrontFaceFillMode:
 366     *     SOLID: Any triangle or rectangle object found to be front-facing
 367     *     is rendered as a solid object. This setting is required when
 368     *     (rendering rectangle (RECTLIST) objects.
 369     */
 370    {
 371       BEGIN_BATCH(7);
 372       OUT_BATCH(_3DSTATE_SF << 16 | (7 - 2));
 373       OUT_BATCH(params->depth_format <<
 374                 GEN7_SF_DEPTH_BUFFER_SURFACE_FORMAT_SHIFT);
 375       OUT_BATCH(params->num_samples > 0 ? GEN6_SF_MSRAST_ON_PATTERN : 0);
 376       OUT_BATCH(0);
 377       OUT_BATCH(0);
 378       OUT_BATCH(0);
 379       OUT_BATCH(0);
 380       ADVANCE_BATCH();
 381    }
 382
 383    /* 3DSTATE_SBE */
 384    {
 385       BEGIN_BATCH(14);
 386       OUT_BATCH(_3DSTATE_SBE << 16 | (14 - 2));
 387       OUT_BATCH((1 - 1) << GEN7_SBE_NUM_OUTPUTS_SHIFT | /* only position */
 388                 1 << GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT |
 389                 0 << GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT);
 390       for (int i = 0; i < 12; ++i)
 391          OUT_BATCH(0);
 392       ADVANCE_BATCH();
 393    }
 394 }
 395
 396
 397 /**
 398  * Disable thread dispatch (dw5.19) and enable the HiZ op.
 399  */
 400 static void
 401 gen7_blorp_emit_wm_config(struct brw_context *brw,
 402                           const brw_blorp_params *params)
 403 {
 404    struct intel_context *intel = &brw->intel;
 405
 406    uint32_t dw1 = 0, dw2 = 0;
 407
 408    switch (params->hiz_op) {
 409    case GEN6_HIZ_OP_DEPTH_CLEAR:
 410       assert(!"not implemented");
 411       dw1 |= GEN7_WM_DEPTH_CLEAR;
 412       break;
 413    case GEN6_HIZ_OP_DEPTH_RESOLVE:
 414       dw1 |= GEN7_WM_DEPTH_RESOLVE;
 415       break;
 416    case GEN6_HIZ_OP_HIZ_RESOLVE:
 417       dw1 |= GEN7_WM_HIERARCHICAL_DEPTH_RESOLVE;
 418       break;
 419    default:
 420       assert(0);
 421       break;
 422    }
 423    dw1 |= GEN7_WM_STATISTICS_ENABLE;
 424    dw1 |= GEN7_WM_LINE_AA_WIDTH_1_0;
 425    dw1 |= GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5;
 426    dw1 |= 0 << GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT; /* No interp */
 427    if (params->use_wm_prog) {
 428       dw1 |= GEN7_WM_KILL_ENABLE; /* TODO: temporarily smash on */
 429       dw1 |= GEN7_WM_DISPATCH_ENABLE; /* We are rendering */
 430    }
 431
 432       if (params->num_samples > 0) {
 433          dw1 |= GEN7_WM_MSRAST_ON_PATTERN;
 434          dw2 |= GEN7_WM_MSDISPMODE_PERPIXEL;
 435       } else {
 436          dw1 |= GEN7_WM_MSRAST_OFF_PIXEL;
 437          dw2 |= GEN7_WM_MSDISPMODE_PERSAMPLE;
 438       }
 439
 440    BEGIN_BATCH(3);
 441    OUT_BATCH(_3DSTATE_WM << 16 | (3 - 2));
 442    OUT_BATCH(dw1);
 443    OUT_BATCH(dw2);
 444    ADVANCE_BATCH();
 445 }
 446
 447
 448 /**
 449  * 3DSTATE_PS
 450  *
 451  * Pixel shader dispatch is disabled above in 3DSTATE_WM, dw1.29. Despite
 452  * that, thread dispatch info must still be specified.
 453  *     - Maximum Number of Threads (dw4.24:31) must be nonzero, as the BSpec
 454  *       states that the valid range for this field is [0x3, 0x2f].
 455  *     - A dispatch mode must be given; that is, at least one of the
 456  *       "N Pixel Dispatch Enable" (N=8,16,32) fields must be set. This was
 457  *       discovered through simulator error messages.
 458  */
 459 static void
 460 gen7_blorp_emit_ps_config(struct brw_context *brw,
 461                           const brw_blorp_params *params,
 462                           uint32_t prog_offset,
 463                           brw_blorp_prog_data *prog_data)
 464 {
 465    struct intel_context *intel = &brw->intel;
 466    uint32_t dw2, dw4, dw5;
 467    const int max_threads_shift = brw->intel.is_haswell ?
 468       HSW_PS_MAX_THREADS_SHIFT : IVB_PS_MAX_THREADS_SHIFT;
 469
 470    dw2 = dw4 = dw5 = 0;
 471    dw4 |= (brw->max_wm_threads - 1) << max_threads_shift;
 472    dw4 |= GEN7_PS_32_DISPATCH_ENABLE;
 473    if (intel->is_haswell)
 474       dw4 |= SET_FIELD(1, HSW_PS_SAMPLE_MASK); /* 1 sample for now */
 475    if (params->use_wm_prog) {
 476       dw2 |= 1 << GEN7_PS_SAMPLER_COUNT_SHIFT; /* Up to 4 samplers */
 477       dw4 |= GEN7_PS_PUSH_CONSTANT_ENABLE;
 478       dw5 |= prog_data->first_curbe_grf << GEN7_PS_DISPATCH_START_GRF_SHIFT_0;
 479    }
 480
 481    BEGIN_BATCH(8);
 482    OUT_BATCH(_3DSTATE_PS << 16 | (8 - 2));
 483    OUT_BATCH(params->use_wm_prog ? prog_offset : 0);
 484    OUT_BATCH(dw2);
 485    OUT_BATCH(0);
 486    OUT_BATCH(dw4);
 487    OUT_BATCH(dw5);
 488    OUT_BATCH(0);
 489    OUT_BATCH(0);
 490    ADVANCE_BATCH();
 491 }
 492
 493
 494 static void
 495 gen7_blorp_emit_binding_table_pointers_ps(struct brw_context *brw,
 496                                           const brw_blorp_params *params,
 497                                           uint32_t wm_bind_bo_offset)
 498 {
 499    struct intel_context *intel = &brw->intel;
 500
 501    BEGIN_BATCH(2);
 502    OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_PS << 16 | (2 - 2));
 503    OUT_BATCH(wm_bind_bo_offset);
 504    ADVANCE_BATCH();
 505 }
 506
 507
 508 static void
 509 gen7_blorp_emit_sampler_state_pointers_ps(struct brw_context *brw,
 510                                           const brw_blorp_params *params,
 511                                           uint32_t sampler_offset)
 512 {
 513    struct intel_context *intel = &brw->intel;
 514
 515    BEGIN_BATCH(2);
 516    OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS_PS << 16 | (2 - 2));
 517    OUT_BATCH(sampler_offset);
 518    ADVANCE_BATCH();
 519 }
 520
 521
 522 static void
 523 gen7_blorp_emit_constant_ps(struct brw_context *brw,
 524                             const brw_blorp_params *params,
 525                             uint32_t wm_push_const_offset)
 526 {
 527    struct intel_context *intel = &brw->intel;
 528
 529    /* Make sure the push constants fill an exact integer number of
 530     * registers.
 531     */
 532    assert(sizeof(brw_blorp_wm_push_constants) % 32 == 0);
 533
 534    /* There must be at least one register worth of push constant data. */
 535    assert(BRW_BLORP_NUM_PUSH_CONST_REGS > 0);
 536
 537    /* Enable push constant buffer 0. */
 538    BEGIN_BATCH(7);
 539    OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 |
 540              (7 - 2));
 541    OUT_BATCH(BRW_BLORP_NUM_PUSH_CONST_REGS);
 542    OUT_BATCH(0);
 543    OUT_BATCH(wm_push_const_offset);
 544    OUT_BATCH(0);
 545    OUT_BATCH(0);
 546    OUT_BATCH(0);
 547    ADVANCE_BATCH();
 548 }
 549
 550
 551 static void
 552 gen7_blorp_emit_depth_stencil_config(struct brw_context *brw,
 553                                      const brw_blorp_params *params)
 554 {
 555    struct intel_context *intel = &brw->intel;
 556    uint32_t draw_x, draw_y;
 557    uint32_t tile_mask_x, tile_mask_y;
 558
 559    if (params->depth.mt) {
 560       params->depth.get_draw_offsets(&draw_x, &draw_y);
 561       gen6_blorp_compute_tile_masks(params, &tile_mask_x, &tile_mask_y);
 562    }
 563
 564    /* 3DSTATE_DEPTH_BUFFER */
 565    {
 566       uint32_t width, height;
 567       params->depth.get_miplevel_dims(&width, &height);
 568
 569       uint32_t tile_x = draw_x & tile_mask_x;
 570       uint32_t tile_y = draw_y & tile_mask_y;
 571       uint32_t offset =
 572          intel_region_get_aligned_offset(params->depth.mt->region,
 573                                          draw_x & ~tile_mask_x,
 574                                          draw_y & ~tile_mask_y);
 575
 576       /* According to the Sandy Bridge PRM, volume 2 part 1, pp326-327
 577        * (3DSTATE_DEPTH_BUFFER dw5), in the documentation for "Depth
 578        * Coordinate Offset X/Y":
 579        *
 580        *   "The 3 LSBs of both offsets must be zero to ensure correct
 581        *   alignment"
 582        *
 583        * We have no guarantee that tile_x and tile_y are correctly aligned,
 584        * since they are determined by the mipmap layout, which is only aligned
 585        * to multiples of 4.
 586        *
 587        * So, to avoid hanging the GPU, just smash the low order 3 bits of
 588        * tile_x and tile_y to 0.  This is a temporary workaround until we come
 589        * up with a better solution.
 590        */
 591       tile_x &= ~7;
 592       tile_y &= ~7;
 593
 594       intel_emit_depth_stall_flushes(intel);
 595
 596       BEGIN_BATCH(7);
 597       OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
 598       uint32_t pitch_bytes =
 599          params->depth.mt->region->pitch * params->depth.mt->region->cpp;
 600       OUT_BATCH((pitch_bytes - 1) |
 601                 params->depth_format << 18 |
 602                 1 << 22 | /* hiz enable */
 603                 1 << 28 | /* depth write */
 604                 BRW_SURFACE_2D << 29);
 605       OUT_RELOC(params->depth.mt->region->bo,
 606                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 607                 offset);
 608       OUT_BATCH((width + tile_x - 1) << 4 |
 609                 (height + tile_y - 1) << 18);
 610       OUT_BATCH(0);
 611       OUT_BATCH(tile_x |
 612                 tile_y << 16);
 613       OUT_BATCH(0);
 614       ADVANCE_BATCH();
 615    }
 616
 617    /* 3DSTATE_HIER_DEPTH_BUFFER */
 618    {
 619       struct intel_region *hiz_region = params->depth.mt->hiz_mt->region;
 620       uint32_t hiz_offset =
 621          intel_region_get_aligned_offset(hiz_region,
 622                                          draw_x & ~tile_mask_x,
 623                                          (draw_y & ~tile_mask_y) / 2);
 624
 625       BEGIN_BATCH(3);
 626       OUT_BATCH((GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
 627       OUT_BATCH(hiz_region->pitch * hiz_region->cpp - 1);
 628       OUT_RELOC(hiz_region->bo,
 629                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 630                 hiz_offset);
 631       ADVANCE_BATCH();
 632    }
 633
 634    /* 3DSTATE_STENCIL_BUFFER */
 635    {
 636       BEGIN_BATCH(3);
 637       OUT_BATCH((GEN7_3DSTATE_STENCIL_BUFFER << 16) | (3 - 2));
 638       OUT_BATCH(0);
 639       OUT_BATCH(0);
 640       ADVANCE_BATCH();
 641    }
 642 }
 643
 644
 645 static void
 646 gen7_blorp_emit_depth_disable(struct brw_context *brw,
 647                               const brw_blorp_params *params)
 648 {
 649    struct intel_context *intel = &brw->intel;
 650
 651    BEGIN_BATCH(7);
 652    OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
 653    OUT_BATCH(BRW_DEPTHFORMAT_D32_FLOAT << 18 | (BRW_SURFACE_NULL << 29));
 654    OUT_BATCH(0);
 655    OUT_BATCH(0);
 656    OUT_BATCH(0);
 657    OUT_BATCH(0);
 658    OUT_BATCH(0);
 659    ADVANCE_BATCH();
 660 }
 661
 662
 663 /* 3DSTATE_CLEAR_PARAMS
 664  *
 665  * From the BSpec, Volume 2a.11 Windower, Section 1.5.6.3.2
 666  * 3DSTATE_CLEAR_PARAMS:
 667  *    [DevIVB] 3DSTATE_CLEAR_PARAMS must always be programmed in the along
 668  *    with the other Depth/Stencil state commands(i.e.  3DSTATE_DEPTH_BUFFER,
 669  *    3DSTATE_STENCIL_BUFFER, or 3DSTATE_HIER_DEPTH_BUFFER).
 670  */
 671 static void
 672 gen7_blorp_emit_clear_params(struct brw_context *brw,
 673                              const brw_blorp_params *params)
 674 {
 675    struct intel_context *intel = &brw->intel;
 676
 677    BEGIN_BATCH(3);
 678    OUT_BATCH(GEN7_3DSTATE_CLEAR_PARAMS << 16 | (3 - 2));
 679    OUT_BATCH(0);
 680    OUT_BATCH(0);
 681    ADVANCE_BATCH();
 682 }
 683
 684
 685 /* 3DPRIMITIVE */
 686 static void
 687 gen7_blorp_emit_primitive(struct brw_context *brw,
 688                           const brw_blorp_params *params)
 689 {
 690    struct intel_context *intel = &brw->intel;
 691
 692    BEGIN_BATCH(7);
 693    OUT_BATCH(CMD_3D_PRIM << 16 | (7 - 2));
 694    OUT_BATCH(GEN7_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL |
 695              _3DPRIM_RECTLIST);
 696    OUT_BATCH(3); /* vertex count per instance */
 697    OUT_BATCH(0);
 698    OUT_BATCH(1); /* instance count */
 699    OUT_BATCH(0);
 700    OUT_BATCH(0);
 701    ADVANCE_BATCH();
 702 }
 703
 704
 705 /**
 706  * \copydoc gen6_blorp_exec()
 707  */
 708 void
 709 gen7_blorp_exec(struct intel_context *intel,
 710                 const brw_blorp_params *params)
 711 {
 712    struct gl_context *ctx = &intel->ctx;
 713    struct brw_context *brw = brw_context(ctx);
 714    brw_blorp_prog_data *prog_data = NULL;
 715    uint32_t cc_blend_state_offset = 0;
 716    uint32_t cc_state_offset = 0;
 717    uint32_t depthstencil_offset;
 718    uint32_t wm_push_const_offset = 0;
 719    uint32_t wm_bind_bo_offset = 0;
 720    uint32_t sampler_offset = 0;
 721
 722    uint32_t prog_offset = params->get_wm_prog(brw, &prog_data);
 723    gen6_blorp_emit_batch_head(brw, params);
 724    gen6_blorp_emit_vertices(brw, params);
 725    gen7_blorp_emit_urb_config(brw, params);
 726    if (params->use_wm_prog) {
 727       cc_blend_state_offset = gen6_blorp_emit_blend_state(brw, params);
 728       cc_state_offset = gen6_blorp_emit_cc_state(brw, params);
 729       gen7_blorp_emit_blend_state_pointer(brw, params, cc_blend_state_offset);
 730       gen7_blorp_emit_cc_state_pointer(brw, params, cc_state_offset);
 731    }
 732    depthstencil_offset = gen6_blorp_emit_depth_stencil_state(brw, params);
 733    gen7_blorp_emit_depth_stencil_state_pointers(brw, params,
 734                                                 depthstencil_offset);
 735    if (params->use_wm_prog) {
 736       uint32_t wm_surf_offset_renderbuffer;
 737       uint32_t wm_surf_offset_texture;
 738       wm_push_const_offset = gen6_blorp_emit_wm_constants(brw, params);
 739       wm_surf_offset_renderbuffer =
 740          gen7_blorp_emit_surface_state(brw, params, &params->dst,
 741                                        I915_GEM_DOMAIN_RENDER,
 742                                        I915_GEM_DOMAIN_RENDER);
 743       wm_surf_offset_texture =
 744          gen7_blorp_emit_surface_state(brw, params, &params->src,
 745                                        I915_GEM_DOMAIN_SAMPLER, 0);
 746       wm_bind_bo_offset =
 747          gen6_blorp_emit_binding_table(brw, params,
 748                                        wm_surf_offset_renderbuffer,
 749                                        wm_surf_offset_texture);
 750       sampler_offset = gen7_blorp_emit_sampler_state(brw, params);
 751    }
 752    gen6_blorp_emit_vs_disable(brw, params);
 753    gen7_blorp_emit_hs_disable(brw, params);
 754    gen7_blorp_emit_te_disable(brw, params);
 755    gen7_blorp_emit_ds_disable(brw, params);
 756    gen6_blorp_emit_gs_disable(brw, params);
 757    gen7_blorp_emit_streamout_disable(brw, params);
 758    gen6_blorp_emit_clip_disable(brw, params);
 759    gen7_blorp_emit_sf_config(brw, params);
 760    gen7_blorp_emit_wm_config(brw, params);
 761    if (params->use_wm_prog) {
 762       gen7_blorp_emit_binding_table_pointers_ps(brw, params,
 763                                                 wm_bind_bo_offset);
 764       gen7_blorp_emit_sampler_state_pointers_ps(brw, params, sampler_offset);
 765       gen7_blorp_emit_constant_ps(brw, params, wm_push_const_offset);
 766    }
 767    gen7_blorp_emit_ps_config(brw, params, prog_offset, prog_data);
 768
 769    if (params->depth.mt)
 770       gen7_blorp_emit_depth_stencil_config(brw, params);
 771    else
 772       gen7_blorp_emit_depth_disable(brw, params);
 773    gen7_blorp_emit_clear_params(brw, params);
 774    gen6_blorp_emit_drawing_rectangle(brw, params);
 775    gen7_blorp_emit_primitive(brw, params);
 776
 777    /* See comments above at first invocation of intel_flush() in
 778     * gen6_blorp_emit_batch_head().
 779     */
 780    intel_flush(ctx);
 781
 782    /* Be safe. */
 783    brw->state.dirty.brw = ~0;
 784    brw->state.dirty.cache = ~0;
 785 }