src/mesa/drivers/dri/i965/gen7_blorp.cpp

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <assert.h>
  25
  26 #include "intel_batchbuffer.h"
  27 #include "intel_fbo.h"
  28 #include "intel_mipmap_tree.h"
  29
  30 #include "brw_context.h"
  31 #include "brw_defines.h"
  32 #include "brw_state.h"
  33
  34 #include "brw_blorp.h"
  35 #include "gen7_blorp.h"
  36
  37
  38 /* 3DSTATE_URB_VS
  39  * 3DSTATE_URB_HS
  40  * 3DSTATE_URB_DS
  41  * 3DSTATE_URB_GS
  42  *
  43  * If the 3DSTATE_URB_VS is emitted, than the others must be also. From the
  44  * BSpec, Volume 2a "3D Pipeline Overview", Section 1.7.1 3DSTATE_URB_VS:
  45  *     3DSTATE_URB_HS, 3DSTATE_URB_DS, and 3DSTATE_URB_GS must also be
  46  *     programmed in order for the programming of this state to be
  47  *     valid.
  48  */
  49 static void
  50 gen7_blorp_emit_urb_config(struct brw_context *brw,
  51                            const brw_blorp_params *params)
  52 {
  53    /* The minimum valid value is 32. See 3DSTATE_URB_VS,
  54     * Dword 1.15:0 "VS Number of URB Entries".
  55     */
  56    int num_vs_entries = 32;
  57    int vs_size = 2;
  58    int vs_start = 2; /* skip over push constants */
  59
  60    gen7_emit_urb_state(brw, num_vs_entries, vs_size, vs_start);
  61 }
  62
  63
  64 /* 3DSTATE_BLEND_STATE_POINTERS */
  65 static void
  66 gen7_blorp_emit_blend_state_pointer(struct brw_context *brw,
  67                                     const brw_blorp_params *params,
  68                                     uint32_t cc_blend_state_offset)
  69 {
  70    struct intel_context *intel = &brw->intel;
  71
  72    BEGIN_BATCH(2);
  73    OUT_BATCH(_3DSTATE_BLEND_STATE_POINTERS << 16 | (2 - 2));
  74    OUT_BATCH(cc_blend_state_offset | 1);
  75    ADVANCE_BATCH();
  76 }
  77
  78
  79 /* 3DSTATE_CC_STATE_POINTERS */
  80 static void
  81 gen7_blorp_emit_cc_state_pointer(struct brw_context *brw,
  82                                  const brw_blorp_params *params,
  83                                  uint32_t cc_state_offset)
  84 {
  85    struct intel_context *intel = &brw->intel;
  86
  87    BEGIN_BATCH(2);
  88    OUT_BATCH(_3DSTATE_CC_STATE_POINTERS << 16 | (2 - 2));
  89    OUT_BATCH(cc_state_offset | 1);
  90    ADVANCE_BATCH();
  91 }
  92
  93 static void
  94 gen7_blorp_emit_cc_viewport(struct brw_context *brw,
  95                             const brw_blorp_params *params)
  96 {
  97    struct intel_context *intel = &brw->intel;
  98    struct brw_cc_viewport *ccv;
  99    uint32_t cc_vp_offset;
 100
 101    ccv = (struct brw_cc_viewport *)brw_state_batch(brw, AUB_TRACE_CC_VP_STATE,
 102                                                    sizeof(*ccv), 32,
 103                                                    &cc_vp_offset);
 104    ccv->min_depth = 0.0;
 105    ccv->max_depth = 1.0;
 106
 107    BEGIN_BATCH(2);
 108    OUT_BATCH(_3DSTATE_VIEWPORT_STATE_POINTERS_CC << 16 | (2 - 2));
 109    OUT_BATCH(cc_vp_offset);
 110    ADVANCE_BATCH();
 111 }
 112
 113
 114 /* 3DSTATE_DEPTH_STENCIL_STATE_POINTERS
 115  *
 116  * The offset is relative to CMD_STATE_BASE_ADDRESS.DynamicStateBaseAddress.
 117  */
 118 static void
 119 gen7_blorp_emit_depth_stencil_state_pointers(struct brw_context *brw,
 120                                              const brw_blorp_params *params,
 121                                              uint32_t depthstencil_offset)
 122 {
 123    struct intel_context *intel = &brw->intel;
 124
 125    BEGIN_BATCH(2);
 126    OUT_BATCH(_3DSTATE_DEPTH_STENCIL_STATE_POINTERS << 16 | (2 - 2));
 127    OUT_BATCH(depthstencil_offset | 1);
 128    ADVANCE_BATCH();
 129 }
 130
 131
 132 /* SURFACE_STATE for renderbuffer or texture surface (see
 133  * brw_update_renderbuffer_surface and brw_update_texture_surface)
 134  */
 135 static uint32_t
 136 gen7_blorp_emit_surface_state(struct brw_context *brw,
 137                               const brw_blorp_params *params,
 138                               const brw_blorp_surface_info *surface,
 139                               uint32_t read_domains, uint32_t write_domain,
 140                               bool is_render_target)
 141 {
 142    struct intel_context *intel = &brw->intel;
 143
 144    uint32_t wm_surf_offset;
 145    uint32_t width, height;
 146    surface->get_miplevel_dims(&width, &height);
 147    if (surface->map_stencil_as_y_tiled) {
 148       width *= 2;
 149       height /= 2;
 150    }
 151    struct intel_region *region = surface->mt->region;
 152
 153    struct gen7_surface_state *surf = (struct gen7_surface_state *)
 154       brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, sizeof(*surf), 32,
 155                       &wm_surf_offset);
 156    memset(surf, 0, sizeof(*surf));
 157
 158    if (surface->mt->align_h == 4)
 159       surf->ss0.vertical_alignment = 1;
 160    if (surface->mt->align_w == 8)
 161       surf->ss0.horizontal_alignment = 1;
 162
 163    surf->ss0.surface_format = surface->brw_surfaceformat;
 164    surf->ss0.surface_type = BRW_SURFACE_2D;
 165    surf->ss0.surface_array_spacing = surface->array_spacing_lod0 ?
 166       GEN7_SURFACE_ARYSPC_LOD0 : GEN7_SURFACE_ARYSPC_FULL;
 167
 168    /* reloc */
 169    surf->ss1.base_addr = region->bo->offset; /* No tile offsets needed */
 170
 171    surf->ss2.width = width - 1;
 172    surf->ss2.height = height - 1;
 173
 174    uint32_t tiling = surface->map_stencil_as_y_tiled
 175       ? I915_TILING_Y : region->tiling;
 176    gen7_set_surface_tiling(surf, tiling);
 177
 178    uint32_t pitch_bytes = region->pitch * region->cpp;
 179    if (surface->map_stencil_as_y_tiled)
 180       pitch_bytes *= 2;
 181    surf->ss3.pitch = pitch_bytes - 1;
 182
 183    gen7_set_surface_num_multisamples(surf, surface->num_samples);
 184    if (surface->msaa_layout == INTEL_MSAA_LAYOUT_CMS) {
 185       gen7_set_surface_mcs_info(brw, surf, wm_surf_offset,
 186                                 surface->mt->mcs_mt, is_render_target);
 187    }
 188
 189    if (intel->is_haswell) {
 190       surf->ss7.shader_chanel_select_r = HSW_SCS_RED;
 191       surf->ss7.shader_chanel_select_g = HSW_SCS_GREEN;
 192       surf->ss7.shader_chanel_select_b = HSW_SCS_BLUE;
 193       surf->ss7.shader_chanel_select_a = HSW_SCS_ALPHA;
 194    }
 195
 196    /* Emit relocation to surface contents */
 197    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
 198                            wm_surf_offset +
 199                            offsetof(struct gen7_surface_state, ss1),
 200                            region->bo,
 201                            surf->ss1.base_addr - region->bo->offset,
 202                            read_domains, write_domain);
 203
 204    gen7_check_surface_setup(surf, is_render_target);
 205
 206    return wm_surf_offset;
 207 }
 208
 209
 210 /**
 211  * SAMPLER_STATE.  See gen7_update_sampler_state().
 212  */
 213 static uint32_t
 214 gen7_blorp_emit_sampler_state(struct brw_context *brw,
 215                               const brw_blorp_params *params)
 216 {
 217    uint32_t sampler_offset;
 218
 219    struct gen7_sampler_state *sampler = (struct gen7_sampler_state *)
 220       brw_state_batch(brw, AUB_TRACE_SAMPLER_STATE,
 221                       sizeof(struct gen7_sampler_state),
 222                       32, &sampler_offset);
 223    memset(sampler, 0, sizeof(*sampler));
 224
 225    sampler->ss0.min_filter = BRW_MAPFILTER_LINEAR;
 226    sampler->ss0.mip_filter = BRW_MIPFILTER_NONE;
 227    sampler->ss0.mag_filter = BRW_MAPFILTER_LINEAR;
 228
 229    sampler->ss3.r_wrap_mode = BRW_TEXCOORDMODE_CLAMP;
 230    sampler->ss3.s_wrap_mode = BRW_TEXCOORDMODE_CLAMP;
 231    sampler->ss3.t_wrap_mode = BRW_TEXCOORDMODE_CLAMP;
 232
 233    //   sampler->ss0.min_mag_neq = 1;
 234
 235    /* Set LOD bias:
 236     */
 237    sampler->ss0.lod_bias = 0;
 238
 239    sampler->ss0.lod_preclamp = 1; /* OpenGL mode */
 240    sampler->ss0.default_color_mode = 0; /* OpenGL/DX10 mode */
 241
 242    /* Set BaseMipLevel, MaxLOD, MinLOD:
 243     *
 244     * XXX: I don't think that using firstLevel, lastLevel works,
 245     * because we always setup the surface state as if firstLevel ==
 246     * level zero.  Probably have to subtract firstLevel from each of
 247     * these:
 248     */
 249    sampler->ss0.base_level = U_FIXED(0, 1);
 250
 251    sampler->ss1.max_lod = U_FIXED(0, 8);
 252    sampler->ss1.min_lod = U_FIXED(0, 8);
 253
 254    sampler->ss3.non_normalized_coord = 1;
 255
 256    sampler->ss3.address_round |= BRW_ADDRESS_ROUNDING_ENABLE_U_MIN |
 257       BRW_ADDRESS_ROUNDING_ENABLE_V_MIN |
 258       BRW_ADDRESS_ROUNDING_ENABLE_R_MIN;
 259    sampler->ss3.address_round |= BRW_ADDRESS_ROUNDING_ENABLE_U_MAG |
 260       BRW_ADDRESS_ROUNDING_ENABLE_V_MAG |
 261       BRW_ADDRESS_ROUNDING_ENABLE_R_MAG;
 262
 263    return sampler_offset;
 264 }
 265
 266
 267 /* 3DSTATE_HS
 268  *
 269  * Disable the hull shader.
 270  */
 271 static void
 272 gen7_blorp_emit_hs_disable(struct brw_context *brw,
 273                            const brw_blorp_params *params)
 274 {
 275    struct intel_context *intel = &brw->intel;
 276
 277    BEGIN_BATCH(7);
 278    OUT_BATCH(_3DSTATE_HS << 16 | (7 - 2));
 279    OUT_BATCH(0);
 280    OUT_BATCH(0);
 281    OUT_BATCH(0);
 282    OUT_BATCH(0);
 283    OUT_BATCH(0);
 284    OUT_BATCH(0);
 285    ADVANCE_BATCH();
 286 }
 287
 288
 289 /* 3DSTATE_TE
 290  *
 291  * Disable the tesselation engine.
 292  */
 293 static void
 294 gen7_blorp_emit_te_disable(struct brw_context *brw,
 295                            const brw_blorp_params *params)
 296 {
 297    struct intel_context *intel = &brw->intel;
 298
 299    BEGIN_BATCH(4);
 300    OUT_BATCH(_3DSTATE_TE << 16 | (4 - 2));
 301    OUT_BATCH(0);
 302    OUT_BATCH(0);
 303    OUT_BATCH(0);
 304    ADVANCE_BATCH();
 305 }
 306
 307
 308 /* 3DSTATE_DS
 309  *
 310  * Disable the domain shader.
 311  */
 312 static void
 313 gen7_blorp_emit_ds_disable(struct brw_context *brw,
 314                            const brw_blorp_params *params)
 315 {
 316    struct intel_context *intel = &brw->intel;
 317
 318    BEGIN_BATCH(6);
 319    OUT_BATCH(_3DSTATE_DS << 16 | (6 - 2));
 320    OUT_BATCH(0);
 321    OUT_BATCH(0);
 322    OUT_BATCH(0);
 323    OUT_BATCH(0);
 324    OUT_BATCH(0);
 325    ADVANCE_BATCH();
 326 }
 327
 328
 329 /* 3DSTATE_STREAMOUT
 330  *
 331  * Disable streamout.
 332  */
 333 static void
 334 gen7_blorp_emit_streamout_disable(struct brw_context *brw,
 335                                   const brw_blorp_params *params)
 336 {
 337    struct intel_context *intel = &brw->intel;
 338
 339    BEGIN_BATCH(3);
 340    OUT_BATCH(_3DSTATE_STREAMOUT << 16 | (3 - 2));
 341    OUT_BATCH(0);
 342    OUT_BATCH(0);
 343    ADVANCE_BATCH();
 344 }
 345
 346
 347 static void
 348 gen7_blorp_emit_sf_config(struct brw_context *brw,
 349                           const brw_blorp_params *params)
 350 {
 351    struct intel_context *intel = &brw->intel;
 352
 353    /* 3DSTATE_SF
 354     *
 355     * Disable ViewportTransformEnable (dw1.1)
 356     *
 357     * From the SandyBridge PRM, Volume 2, Part 1, Section 1.3, "3D
 358     * Primitives Overview":
 359     *     RECTLIST: Viewport Mapping must be DISABLED (as is typical with the
 360     *     use of screen- space coordinates).
 361     *
 362     * A solid rectangle must be rendered, so set FrontFaceFillMode (dw1.6:5)
 363     * and BackFaceFillMode (dw1.4:3) to SOLID(0).
 364     *
 365     * From the Sandy Bridge PRM, Volume 2, Part 1, Section
 366     * 6.4.1.1 3DSTATE_SF, Field FrontFaceFillMode:
 367     *     SOLID: Any triangle or rectangle object found to be front-facing
 368     *     is rendered as a solid object. This setting is required when
 369     *     (rendering rectangle (RECTLIST) objects.
 370     */
 371    {
 372       BEGIN_BATCH(7);
 373       OUT_BATCH(_3DSTATE_SF << 16 | (7 - 2));
 374       OUT_BATCH(params->depth_format <<
 375                 GEN7_SF_DEPTH_BUFFER_SURFACE_FORMAT_SHIFT);
 376       OUT_BATCH(params->num_samples > 0 ? GEN6_SF_MSRAST_ON_PATTERN : 0);
 377       OUT_BATCH(0);
 378       OUT_BATCH(0);
 379       OUT_BATCH(0);
 380       OUT_BATCH(0);
 381       ADVANCE_BATCH();
 382    }
 383
 384    /* 3DSTATE_SBE */
 385    {
 386       BEGIN_BATCH(14);
 387       OUT_BATCH(_3DSTATE_SBE << 16 | (14 - 2));
 388       OUT_BATCH((1 - 1) << GEN7_SBE_NUM_OUTPUTS_SHIFT | /* only position */
 389                 1 << GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT |
 390                 0 << GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT);
 391       for (int i = 0; i < 12; ++i)
 392          OUT_BATCH(0);
 393       ADVANCE_BATCH();
 394    }
 395 }
 396
 397
 398 /**
 399  * Disable thread dispatch (dw5.19) and enable the HiZ op.
 400  */
 401 static void
 402 gen7_blorp_emit_wm_config(struct brw_context *brw,
 403                           const brw_blorp_params *params,
 404                           brw_blorp_prog_data *prog_data)
 405 {
 406    struct intel_context *intel = &brw->intel;
 407
 408    uint32_t dw1 = 0, dw2 = 0;
 409
 410    switch (params->hiz_op) {
 411    case GEN6_HIZ_OP_DEPTH_CLEAR:
 412       dw1 |= GEN7_WM_DEPTH_CLEAR;
 413       break;
 414    case GEN6_HIZ_OP_DEPTH_RESOLVE:
 415       dw1 |= GEN7_WM_DEPTH_RESOLVE;
 416       break;
 417    case GEN6_HIZ_OP_HIZ_RESOLVE:
 418       dw1 |= GEN7_WM_HIERARCHICAL_DEPTH_RESOLVE;
 419       break;
 420    case GEN6_HIZ_OP_NONE:
 421       break;
 422    default:
 423       assert(0);
 424       break;
 425    }
 426    dw1 |= GEN7_WM_STATISTICS_ENABLE;
 427    dw1 |= GEN7_WM_LINE_AA_WIDTH_1_0;
 428    dw1 |= GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5;
 429    dw1 |= 0 << GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT; /* No interp */
 430    if (params->use_wm_prog) {
 431       dw1 |= GEN7_WM_KILL_ENABLE; /* TODO: temporarily smash on */
 432       dw1 |= GEN7_WM_DISPATCH_ENABLE; /* We are rendering */
 433    }
 434
 435       if (params->num_samples > 0) {
 436          dw1 |= GEN7_WM_MSRAST_ON_PATTERN;
 437          if (prog_data && prog_data->persample_msaa_dispatch)
 438             dw2 |= GEN7_WM_MSDISPMODE_PERSAMPLE;
 439          else
 440             dw2 |= GEN7_WM_MSDISPMODE_PERPIXEL;
 441       } else {
 442          dw1 |= GEN7_WM_MSRAST_OFF_PIXEL;
 443          dw2 |= GEN7_WM_MSDISPMODE_PERSAMPLE;
 444       }
 445
 446    BEGIN_BATCH(3);
 447    OUT_BATCH(_3DSTATE_WM << 16 | (3 - 2));
 448    OUT_BATCH(dw1);
 449    OUT_BATCH(dw2);
 450    ADVANCE_BATCH();
 451 }
 452
 453
 454 /**
 455  * 3DSTATE_PS
 456  *
 457  * Pixel shader dispatch is disabled above in 3DSTATE_WM, dw1.29. Despite
 458  * that, thread dispatch info must still be specified.
 459  *     - Maximum Number of Threads (dw4.24:31) must be nonzero, as the BSpec
 460  *       states that the valid range for this field is [0x3, 0x2f].
 461  *     - A dispatch mode must be given; that is, at least one of the
 462  *       "N Pixel Dispatch Enable" (N=8,16,32) fields must be set. This was
 463  *       discovered through simulator error messages.
 464  */
 465 static void
 466 gen7_blorp_emit_ps_config(struct brw_context *brw,
 467                           const brw_blorp_params *params,
 468                           uint32_t prog_offset,
 469                           brw_blorp_prog_data *prog_data)
 470 {
 471    struct intel_context *intel = &brw->intel;
 472    uint32_t dw2, dw4, dw5;
 473    const int max_threads_shift = brw->intel.is_haswell ?
 474       HSW_PS_MAX_THREADS_SHIFT : IVB_PS_MAX_THREADS_SHIFT;
 475
 476    dw2 = dw4 = dw5 = 0;
 477    dw4 |= (brw->max_wm_threads - 1) << max_threads_shift;
 478
 479    /* If there's a WM program, we need to do 16-pixel dispatch since that's
 480     * what the program is compiled for.  If there isn't, then it shouldn't
 481     * matter because no program is actually being run.  However, the hardware
 482     * gets angry if we don't enable at least one dispatch mode, so just enable
 483     * 16-pixel dispatch unconditionally.
 484     */
 485    dw4 |= GEN7_PS_16_DISPATCH_ENABLE;
 486
 487    if (intel->is_haswell)
 488       dw4 |= SET_FIELD(1, HSW_PS_SAMPLE_MASK); /* 1 sample for now */
 489    if (params->use_wm_prog) {
 490       dw2 |= 1 << GEN7_PS_SAMPLER_COUNT_SHIFT; /* Up to 4 samplers */
 491       dw4 |= GEN7_PS_PUSH_CONSTANT_ENABLE;
 492       dw5 |= prog_data->first_curbe_grf << GEN7_PS_DISPATCH_START_GRF_SHIFT_0;
 493    }
 494
 495    BEGIN_BATCH(8);
 496    OUT_BATCH(_3DSTATE_PS << 16 | (8 - 2));
 497    OUT_BATCH(params->use_wm_prog ? prog_offset : 0);
 498    OUT_BATCH(dw2);
 499    OUT_BATCH(0);
 500    OUT_BATCH(dw4);
 501    OUT_BATCH(dw5);
 502    OUT_BATCH(0);
 503    OUT_BATCH(0);
 504    ADVANCE_BATCH();
 505 }
 506
 507
 508 static void
 509 gen7_blorp_emit_binding_table_pointers_ps(struct brw_context *brw,
 510                                           const brw_blorp_params *params,
 511                                           uint32_t wm_bind_bo_offset)
 512 {
 513    struct intel_context *intel = &brw->intel;
 514
 515    BEGIN_BATCH(2);
 516    OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_PS << 16 | (2 - 2));
 517    OUT_BATCH(wm_bind_bo_offset);
 518    ADVANCE_BATCH();
 519 }
 520
 521
 522 static void
 523 gen7_blorp_emit_sampler_state_pointers_ps(struct brw_context *brw,
 524                                           const brw_blorp_params *params,
 525                                           uint32_t sampler_offset)
 526 {
 527    struct intel_context *intel = &brw->intel;
 528
 529    BEGIN_BATCH(2);
 530    OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS_PS << 16 | (2 - 2));
 531    OUT_BATCH(sampler_offset);
 532    ADVANCE_BATCH();
 533 }
 534
 535
 536 static void
 537 gen7_blorp_emit_constant_ps(struct brw_context *brw,
 538                             const brw_blorp_params *params,
 539                             uint32_t wm_push_const_offset)
 540 {
 541    struct intel_context *intel = &brw->intel;
 542
 543    /* Make sure the push constants fill an exact integer number of
 544     * registers.
 545     */
 546    assert(sizeof(brw_blorp_wm_push_constants) % 32 == 0);
 547
 548    /* There must be at least one register worth of push constant data. */
 549    assert(BRW_BLORP_NUM_PUSH_CONST_REGS > 0);
 550
 551    /* Enable push constant buffer 0. */
 552    BEGIN_BATCH(7);
 553    OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 |
 554              (7 - 2));
 555    OUT_BATCH(BRW_BLORP_NUM_PUSH_CONST_REGS);
 556    OUT_BATCH(0);
 557    OUT_BATCH(wm_push_const_offset);
 558    OUT_BATCH(0);
 559    OUT_BATCH(0);
 560    OUT_BATCH(0);
 561    ADVANCE_BATCH();
 562 }
 563
 564
 565 static void
 566 gen7_blorp_emit_depth_stencil_config(struct brw_context *brw,
 567                                      const brw_blorp_params *params)
 568 {
 569    struct intel_context *intel = &brw->intel;
 570    uint32_t draw_x, draw_y;
 571    uint32_t tile_mask_x, tile_mask_y;
 572
 573    if (params->depth.mt) {
 574       params->depth.get_draw_offsets(&draw_x, &draw_y);
 575       gen6_blorp_compute_tile_masks(params, &tile_mask_x, &tile_mask_y);
 576    }
 577
 578    /* 3DSTATE_DEPTH_BUFFER */
 579    {
 580       uint32_t width, height;
 581       params->depth.get_miplevel_dims(&width, &height);
 582
 583       uint32_t tile_x = draw_x & tile_mask_x;
 584       uint32_t tile_y = draw_y & tile_mask_y;
 585       uint32_t offset =
 586          intel_region_get_aligned_offset(params->depth.mt->region,
 587                                          draw_x & ~tile_mask_x,
 588                                          draw_y & ~tile_mask_y);
 589
 590       /* According to the Sandy Bridge PRM, volume 2 part 1, pp326-327
 591        * (3DSTATE_DEPTH_BUFFER dw5), in the documentation for "Depth
 592        * Coordinate Offset X/Y":
 593        *
 594        *   "The 3 LSBs of both offsets must be zero to ensure correct
 595        *   alignment"
 596        *
 597        * We have no guarantee that tile_x and tile_y are correctly aligned,
 598        * since they are determined by the mipmap layout, which is only aligned
 599        * to multiples of 4.
 600        *
 601        * So, to avoid hanging the GPU, just smash the low order 3 bits of
 602        * tile_x and tile_y to 0.  This is a temporary workaround until we come
 603        * up with a better solution.
 604        */
 605       tile_x &= ~7;
 606       tile_y &= ~7;
 607
 608       intel_emit_depth_stall_flushes(intel);
 609
 610       BEGIN_BATCH(7);
 611       OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
 612       uint32_t pitch_bytes =
 613          params->depth.mt->region->pitch * params->depth.mt->region->cpp;
 614       OUT_BATCH((pitch_bytes - 1) |
 615                 params->depth_format << 18 |
 616                 1 << 22 | /* hiz enable */
 617                 1 << 28 | /* depth write */
 618                 BRW_SURFACE_2D << 29);
 619       OUT_RELOC(params->depth.mt->region->bo,
 620                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 621                 offset);
 622       OUT_BATCH((width + tile_x - 1) << 4 |
 623                 (height + tile_y - 1) << 18);
 624       OUT_BATCH(0);
 625       OUT_BATCH(tile_x |
 626                 tile_y << 16);
 627       OUT_BATCH(0);
 628       ADVANCE_BATCH();
 629    }
 630
 631    /* 3DSTATE_HIER_DEPTH_BUFFER */
 632    {
 633       struct intel_region *hiz_region = params->depth.mt->hiz_mt->region;
 634       uint32_t hiz_offset =
 635          intel_region_get_aligned_offset(hiz_region,
 636                                          draw_x & ~tile_mask_x,
 637                                          (draw_y & ~tile_mask_y) / 2);
 638
 639       BEGIN_BATCH(3);
 640       OUT_BATCH((GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
 641       OUT_BATCH(hiz_region->pitch * hiz_region->cpp - 1);
 642       OUT_RELOC(hiz_region->bo,
 643                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 644                 hiz_offset);
 645       ADVANCE_BATCH();
 646    }
 647
 648    /* 3DSTATE_STENCIL_BUFFER */
 649    {
 650       BEGIN_BATCH(3);
 651       OUT_BATCH((GEN7_3DSTATE_STENCIL_BUFFER << 16) | (3 - 2));
 652       OUT_BATCH(0);
 653       OUT_BATCH(0);
 654       ADVANCE_BATCH();
 655    }
 656 }
 657
 658
 659 static void
 660 gen7_blorp_emit_depth_disable(struct brw_context *brw,
 661                               const brw_blorp_params *params)
 662 {
 663    struct intel_context *intel = &brw->intel;
 664
 665    BEGIN_BATCH(7);
 666    OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
 667    OUT_BATCH(BRW_DEPTHFORMAT_D32_FLOAT << 18 | (BRW_SURFACE_NULL << 29));
 668    OUT_BATCH(0);
 669    OUT_BATCH(0);
 670    OUT_BATCH(0);
 671    OUT_BATCH(0);
 672    OUT_BATCH(0);
 673    ADVANCE_BATCH();
 674 }
 675
 676
 677 /* 3DSTATE_CLEAR_PARAMS
 678  *
 679  * From the BSpec, Volume 2a.11 Windower, Section 1.5.6.3.2
 680  * 3DSTATE_CLEAR_PARAMS:
 681  *    [DevIVB] 3DSTATE_CLEAR_PARAMS must always be programmed in the along
 682  *    with the other Depth/Stencil state commands(i.e.  3DSTATE_DEPTH_BUFFER,
 683  *    3DSTATE_STENCIL_BUFFER, or 3DSTATE_HIER_DEPTH_BUFFER).
 684  */
 685 static void
 686 gen7_blorp_emit_clear_params(struct brw_context *brw,
 687                              const brw_blorp_params *params)
 688 {
 689    struct intel_context *intel = &brw->intel;
 690
 691    BEGIN_BATCH(3);
 692    OUT_BATCH(GEN7_3DSTATE_CLEAR_PARAMS << 16 | (3 - 2));
 693    OUT_BATCH(params->depth.mt ? params->depth.mt->depth_clear_value : 0);
 694    OUT_BATCH(GEN7_DEPTH_CLEAR_VALID);
 695    ADVANCE_BATCH();
 696 }
 697
 698
 699 /* 3DPRIMITIVE */
 700 static void
 701 gen7_blorp_emit_primitive(struct brw_context *brw,
 702                           const brw_blorp_params *params)
 703 {
 704    struct intel_context *intel = &brw->intel;
 705
 706    BEGIN_BATCH(7);
 707    OUT_BATCH(CMD_3D_PRIM << 16 | (7 - 2));
 708    OUT_BATCH(GEN7_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL |
 709              _3DPRIM_RECTLIST);
 710    OUT_BATCH(3); /* vertex count per instance */
 711    OUT_BATCH(0);
 712    OUT_BATCH(1); /* instance count */
 713    OUT_BATCH(0);
 714    OUT_BATCH(0);
 715    ADVANCE_BATCH();
 716 }
 717
 718
 719 /**
 720  * \copydoc gen6_blorp_exec()
 721  */
 722 void
 723 gen7_blorp_exec(struct intel_context *intel,
 724                 const brw_blorp_params *params)
 725 {
 726    struct gl_context *ctx = &intel->ctx;
 727    struct brw_context *brw = brw_context(ctx);
 728    brw_blorp_prog_data *prog_data = NULL;
 729    uint32_t cc_blend_state_offset = 0;
 730    uint32_t cc_state_offset = 0;
 731    uint32_t depthstencil_offset;
 732    uint32_t wm_push_const_offset = 0;
 733    uint32_t wm_bind_bo_offset = 0;
 734    uint32_t sampler_offset = 0;
 735
 736    uint32_t prog_offset = params->get_wm_prog(brw, &prog_data);
 737    gen6_blorp_emit_batch_head(brw, params);
 738    gen7_allocate_push_constants(brw);
 739    gen6_emit_3dstate_multisample(brw, params->num_samples);
 740    gen6_emit_3dstate_sample_mask(brw, params->num_samples, 1.0, false);
 741    gen6_blorp_emit_state_base_address(brw, params);
 742    gen6_blorp_emit_vertices(brw, params);
 743    gen7_blorp_emit_urb_config(brw, params);
 744    if (params->use_wm_prog) {
 745       cc_blend_state_offset = gen6_blorp_emit_blend_state(brw, params);
 746       cc_state_offset = gen6_blorp_emit_cc_state(brw, params);
 747       gen7_blorp_emit_blend_state_pointer(brw, params, cc_blend_state_offset);
 748       gen7_blorp_emit_cc_state_pointer(brw, params, cc_state_offset);
 749    }
 750    depthstencil_offset = gen6_blorp_emit_depth_stencil_state(brw, params);
 751    gen7_blorp_emit_depth_stencil_state_pointers(brw, params,
 752                                                 depthstencil_offset);
 753    if (params->use_wm_prog) {
 754       uint32_t wm_surf_offset_renderbuffer;
 755       uint32_t wm_surf_offset_texture;
 756       wm_push_const_offset = gen6_blorp_emit_wm_constants(brw, params);
 757       wm_surf_offset_renderbuffer =
 758          gen7_blorp_emit_surface_state(brw, params, &params->dst,
 759                                        I915_GEM_DOMAIN_RENDER,
 760                                        I915_GEM_DOMAIN_RENDER,
 761                                        true /* is_render_target */);
 762       wm_surf_offset_texture =
 763          gen7_blorp_emit_surface_state(brw, params, &params->src,
 764                                        I915_GEM_DOMAIN_SAMPLER, 0,
 765                                        false /* is_render_target */);
 766       wm_bind_bo_offset =
 767          gen6_blorp_emit_binding_table(brw, params,
 768                                        wm_surf_offset_renderbuffer,
 769                                        wm_surf_offset_texture);
 770       sampler_offset = gen7_blorp_emit_sampler_state(brw, params);
 771    }
 772    gen6_blorp_emit_vs_disable(brw, params);
 773    gen7_blorp_emit_hs_disable(brw, params);
 774    gen7_blorp_emit_te_disable(brw, params);
 775    gen7_blorp_emit_ds_disable(brw, params);
 776    gen6_blorp_emit_gs_disable(brw, params);
 777    gen7_blorp_emit_streamout_disable(brw, params);
 778    gen6_blorp_emit_clip_disable(brw, params);
 779    gen7_blorp_emit_sf_config(brw, params);
 780    gen7_blorp_emit_wm_config(brw, params, prog_data);
 781    if (params->use_wm_prog) {
 782       gen7_blorp_emit_binding_table_pointers_ps(brw, params,
 783                                                 wm_bind_bo_offset);
 784       gen7_blorp_emit_sampler_state_pointers_ps(brw, params, sampler_offset);
 785       gen7_blorp_emit_constant_ps(brw, params, wm_push_const_offset);
 786    }
 787    gen7_blorp_emit_ps_config(brw, params, prog_offset, prog_data);
 788    gen7_blorp_emit_cc_viewport(brw, params);
 789
 790    if (params->depth.mt)
 791       gen7_blorp_emit_depth_stencil_config(brw, params);
 792    else
 793       gen7_blorp_emit_depth_disable(brw, params);
 794    gen7_blorp_emit_clear_params(brw, params);
 795    gen6_blorp_emit_drawing_rectangle(brw, params);
 796    gen7_blorp_emit_primitive(brw, params);
 797
 798    /* See comments above at first invocation of intel_flush() in
 799     * gen6_blorp_emit_batch_head().
 800     */
 801    intel_flush(ctx);
 802
 803    /* Be safe. */
 804    brw->state.dirty.brw = ~0;
 805    brw->state.dirty.cache = ~0;
 806 }