src/mesa/drivers/dri/i965/gen7_blorp.cpp

   1 /*
   2  * Copyright © 2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include <assert.h>
  25
  26 #include "intel_batchbuffer.h"
  27 #include "intel_fbo.h"
  28 #include "intel_mipmap_tree.h"
  29
  30 #include "brw_context.h"
  31 #include "brw_defines.h"
  32 #include "brw_state.h"
  33
  34 #include "brw_blorp.h"
  35 #include "gen7_blorp.h"
  36
  37
  38 /* 3DSTATE_URB_VS
  39  * 3DSTATE_URB_HS
  40  * 3DSTATE_URB_DS
  41  * 3DSTATE_URB_GS
  42  *
  43  * If the 3DSTATE_URB_VS is emitted, than the others must be also.
  44  * From the Ivybridge PRM, Volume 2 Part 1, section 1.7.1 3DSTATE_URB_VS:
  45  *
  46  *     3DSTATE_URB_HS, 3DSTATE_URB_DS, and 3DSTATE_URB_GS must also be
  47  *     programmed in order for the programming of this state to be
  48  *     valid.
  49  */
  50 static void
  51 gen7_blorp_emit_urb_config(struct brw_context *brw)
  52 {
  53    unsigned urb_size = (brw->is_haswell && brw->gt == 3) ? 32 : 16;
  54    gen7_emit_push_constant_state(brw,
  55                                  urb_size / 2 /* vs_size */,
  56                                  0 /* gs_size */,
  57                                  urb_size / 2 /* fs_size */);
  58
  59    /* The minimum valid number of VS entries is 32. See 3DSTATE_URB_VS, Dword
  60     * 1.15:0 "VS Number of URB Entries".
  61     */
  62    gen7_emit_urb_state(brw,
  63                        32 /* num_vs_entries */,
  64                        2 /* vs_size */,
  65                        2 /* vs_start */,
  66                        0 /* num_gs_entries */,
  67                        1 /* gs_size */,
  68                        2 /* gs_start */);
  69 }
  70
  71
  72 /* 3DSTATE_BLEND_STATE_POINTERS */
  73 static void
  74 gen7_blorp_emit_blend_state_pointer(struct brw_context *brw,
  75                                     uint32_t cc_blend_state_offset)
  76 {
  77    BEGIN_BATCH(2);
  78    OUT_BATCH(_3DSTATE_BLEND_STATE_POINTERS << 16 | (2 - 2));
  79    OUT_BATCH(cc_blend_state_offset | 1);
  80    ADVANCE_BATCH();
  81 }
  82
  83
  84 /* 3DSTATE_CC_STATE_POINTERS */
  85 static void
  86 gen7_blorp_emit_cc_state_pointer(struct brw_context *brw,
  87                                  uint32_t cc_state_offset)
  88 {
  89    BEGIN_BATCH(2);
  90    OUT_BATCH(_3DSTATE_CC_STATE_POINTERS << 16 | (2 - 2));
  91    OUT_BATCH(cc_state_offset | 1);
  92    ADVANCE_BATCH();
  93 }
  94
  95 static void
  96 gen7_blorp_emit_cc_viewport(struct brw_context *brw)
  97 {
  98    struct brw_cc_viewport *ccv;
  99    uint32_t cc_vp_offset;
 100
 101    ccv = (struct brw_cc_viewport *)brw_state_batch(brw, AUB_TRACE_CC_VP_STATE,
 102                                                    sizeof(*ccv), 32,
 103                                                    &cc_vp_offset);
 104    ccv->min_depth = 0.0;
 105    ccv->max_depth = 1.0;
 106
 107    BEGIN_BATCH(2);
 108    OUT_BATCH(_3DSTATE_VIEWPORT_STATE_POINTERS_CC << 16 | (2 - 2));
 109    OUT_BATCH(cc_vp_offset);
 110    ADVANCE_BATCH();
 111 }
 112
 113
 114 /* 3DSTATE_DEPTH_STENCIL_STATE_POINTERS
 115  *
 116  * The offset is relative to CMD_STATE_BASE_ADDRESS.DynamicStateBaseAddress.
 117  */
 118 static void
 119 gen7_blorp_emit_depth_stencil_state_pointers(struct brw_context *brw,
 120                                              uint32_t depthstencil_offset)
 121 {
 122    BEGIN_BATCH(2);
 123    OUT_BATCH(_3DSTATE_DEPTH_STENCIL_STATE_POINTERS << 16 | (2 - 2));
 124    OUT_BATCH(depthstencil_offset | 1);
 125    ADVANCE_BATCH();
 126 }
 127
 128
 129 /* SURFACE_STATE for renderbuffer or texture surface (see
 130  * brw_update_renderbuffer_surface and brw_update_texture_surface)
 131  */
 132 static uint32_t
 133 gen7_blorp_emit_surface_state(struct brw_context *brw,
 134                               const brw_blorp_surface_info *surface,
 135                               uint32_t read_domains, uint32_t write_domain,
 136                               bool is_render_target)
 137 {
 138    uint32_t wm_surf_offset;
 139    uint32_t width = surface->width;
 140    uint32_t height = surface->height;
 141    /* Note: since gen7 uses INTEL_MSAA_LAYOUT_CMS or INTEL_MSAA_LAYOUT_UMS for
 142     * color surfaces, width and height are measured in pixels; we don't need
 143     * to divide them by 2 as we do for Gen6 (see
 144     * gen6_blorp_emit_surface_state).
 145     */
 146    struct intel_mipmap_tree *mt = surface->mt;
 147    uint32_t tile_x, tile_y;
 148    const uint8_t mocs = GEN7_MOCS_L3;
 149
 150    uint32_t tiling = surface->map_stencil_as_y_tiled
 151       ? I915_TILING_Y : mt->tiling;
 152
 153    uint32_t *surf = (uint32_t *)
 154       brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 8 * 4, 32, &wm_surf_offset);
 155    memset(surf, 0, 8 * 4);
 156
 157    surf[0] = BRW_SURFACE_2D << BRW_SURFACE_TYPE_SHIFT |
 158              surface->brw_surfaceformat << BRW_SURFACE_FORMAT_SHIFT |
 159              gen7_surface_tiling_mode(tiling);
 160
 161    if (surface->mt->valign == 4)
 162       surf[0] |= GEN7_SURFACE_VALIGN_4;
 163    if (surface->mt->halign == 8)
 164       surf[0] |= GEN7_SURFACE_HALIGN_8;
 165
 166    if (surface->array_layout == ALL_SLICES_AT_EACH_LOD)
 167       surf[0] |= GEN7_SURFACE_ARYSPC_LOD0;
 168    else
 169       surf[0] |= GEN7_SURFACE_ARYSPC_FULL;
 170
 171    /* reloc */
 172    surf[1] =
 173       surface->compute_tile_offsets(&tile_x, &tile_y) + mt->bo->offset64;
 174
 175    /* Note that the low bits of these fields are missing, so
 176     * there's the possibility of getting in trouble.
 177     */
 178    assert(tile_x % 4 == 0);
 179    assert(tile_y % 2 == 0);
 180    surf[5] = SET_FIELD(tile_x / 4, BRW_SURFACE_X_OFFSET) |
 181              SET_FIELD(tile_y / 2, BRW_SURFACE_Y_OFFSET) |
 182              SET_FIELD(mocs, GEN7_SURFACE_MOCS);
 183
 184    surf[2] = SET_FIELD(width - 1, GEN7_SURFACE_WIDTH) |
 185              SET_FIELD(height - 1, GEN7_SURFACE_HEIGHT);
 186
 187    uint32_t pitch_bytes = mt->pitch;
 188    if (surface->map_stencil_as_y_tiled)
 189       pitch_bytes *= 2;
 190    surf[3] = pitch_bytes - 1;
 191
 192    surf[4] = gen7_surface_msaa_bits(surface->num_samples, surface->msaa_layout);
 193    if (surface->mt->mcs_mt) {
 194       gen7_set_surface_mcs_info(brw, surf, wm_surf_offset, surface->mt->mcs_mt,
 195                                 is_render_target);
 196    }
 197
 198    surf[7] = surface->mt->fast_clear_color_value;
 199
 200    if (brw->is_haswell) {
 201       surf[7] |= (SET_FIELD(HSW_SCS_RED,   GEN7_SURFACE_SCS_R) |
 202                   SET_FIELD(HSW_SCS_GREEN, GEN7_SURFACE_SCS_G) |
 203                   SET_FIELD(HSW_SCS_BLUE,  GEN7_SURFACE_SCS_B) |
 204                   SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A));
 205    }
 206
 207    /* Emit relocation to surface contents */
 208    drm_intel_bo_emit_reloc(brw->batch.bo,
 209                            wm_surf_offset + 4,
 210                            mt->bo,
 211                            surf[1] - mt->bo->offset64,
 212                            read_domains, write_domain);
 213
 214    gen7_check_surface_setup(surf, is_render_target);
 215
 216    return wm_surf_offset;
 217 }
 218
 219
 220 /* 3DSTATE_VS
 221  *
 222  * Disable vertex shader.
 223  */
 224 static void
 225 gen7_blorp_emit_vs_disable(struct brw_context *brw)
 226 {
 227    BEGIN_BATCH(7);
 228    OUT_BATCH(_3DSTATE_CONSTANT_VS << 16 | (7 - 2));
 229    OUT_BATCH(0);
 230    OUT_BATCH(0);
 231    OUT_BATCH(0);
 232    OUT_BATCH(0);
 233    OUT_BATCH(0);
 234    OUT_BATCH(0);
 235    ADVANCE_BATCH();
 236
 237    BEGIN_BATCH(6);
 238    OUT_BATCH(_3DSTATE_VS << 16 | (6 - 2));
 239    OUT_BATCH(0);
 240    OUT_BATCH(0);
 241    OUT_BATCH(0);
 242    OUT_BATCH(0);
 243    OUT_BATCH(0);
 244    ADVANCE_BATCH();
 245 }
 246
 247
 248 /* 3DSTATE_HS
 249  *
 250  * Disable the hull shader.
 251  */
 252 static void
 253 gen7_blorp_emit_hs_disable(struct brw_context *brw)
 254 {
 255    BEGIN_BATCH(7);
 256    OUT_BATCH(_3DSTATE_CONSTANT_HS << 16 | (7 - 2));
 257    OUT_BATCH(0);
 258    OUT_BATCH(0);
 259    OUT_BATCH(0);
 260    OUT_BATCH(0);
 261    OUT_BATCH(0);
 262    OUT_BATCH(0);
 263    ADVANCE_BATCH();
 264
 265    BEGIN_BATCH(7);
 266    OUT_BATCH(_3DSTATE_HS << 16 | (7 - 2));
 267    OUT_BATCH(0);
 268    OUT_BATCH(0);
 269    OUT_BATCH(0);
 270    OUT_BATCH(0);
 271    OUT_BATCH(0);
 272    OUT_BATCH(0);
 273    ADVANCE_BATCH();
 274 }
 275
 276
 277 /* 3DSTATE_TE
 278  *
 279  * Disable the tesselation engine.
 280  */
 281 static void
 282 gen7_blorp_emit_te_disable(struct brw_context *brw)
 283 {
 284    BEGIN_BATCH(4);
 285    OUT_BATCH(_3DSTATE_TE << 16 | (4 - 2));
 286    OUT_BATCH(0);
 287    OUT_BATCH(0);
 288    OUT_BATCH(0);
 289    ADVANCE_BATCH();
 290 }
 291
 292
 293 /* 3DSTATE_DS
 294  *
 295  * Disable the domain shader.
 296  */
 297 static void
 298 gen7_blorp_emit_ds_disable(struct brw_context *brw)
 299 {
 300    BEGIN_BATCH(7);
 301    OUT_BATCH(_3DSTATE_CONSTANT_DS << 16 | (7 - 2));
 302    OUT_BATCH(0);
 303    OUT_BATCH(0);
 304    OUT_BATCH(0);
 305    OUT_BATCH(0);
 306    OUT_BATCH(0);
 307    OUT_BATCH(0);
 308    ADVANCE_BATCH();
 309
 310    BEGIN_BATCH(6);
 311    OUT_BATCH(_3DSTATE_DS << 16 | (6 - 2));
 312    OUT_BATCH(0);
 313    OUT_BATCH(0);
 314    OUT_BATCH(0);
 315    OUT_BATCH(0);
 316    OUT_BATCH(0);
 317    ADVANCE_BATCH();
 318 }
 319
 320 /* 3DSTATE_GS
 321  *
 322  * Disable the geometry shader.
 323  */
 324 static void
 325 gen7_blorp_emit_gs_disable(struct brw_context *brw)
 326 {
 327    BEGIN_BATCH(7);
 328    OUT_BATCH(_3DSTATE_CONSTANT_GS << 16 | (7 - 2));
 329    OUT_BATCH(0);
 330    OUT_BATCH(0);
 331    OUT_BATCH(0);
 332    OUT_BATCH(0);
 333    OUT_BATCH(0);
 334    OUT_BATCH(0);
 335    ADVANCE_BATCH();
 336
 337    /**
 338     * From Graphics BSpec: 3D-Media-GPGPU Engine > 3D Pipeline Stages >
 339     * Geometry > Geometry Shader > State:
 340     *
 341     *     "Note: Because of corruption in IVB:GT2, software needs to flush the
 342     *     whole fixed function pipeline when the GS enable changes value in
 343     *     the 3DSTATE_GS."
 344     *
 345     * The hardware architects have clarified that in this context "flush the
 346     * whole fixed function pipeline" means to emit a PIPE_CONTROL with the "CS
 347     * Stall" bit set.
 348     */
 349    if (!brw->is_haswell && brw->gt == 2 && brw->gs.enabled)
 350       gen7_emit_cs_stall_flush(brw);
 351
 352    BEGIN_BATCH(7);
 353    OUT_BATCH(_3DSTATE_GS << 16 | (7 - 2));
 354    OUT_BATCH(0);
 355    OUT_BATCH(0);
 356    OUT_BATCH(0);
 357    OUT_BATCH(0);
 358    OUT_BATCH(0);
 359    OUT_BATCH(0);
 360    ADVANCE_BATCH();
 361    brw->gs.enabled = false;
 362 }
 363
 364 /* 3DSTATE_STREAMOUT
 365  *
 366  * Disable streamout.
 367  */
 368 static void
 369 gen7_blorp_emit_streamout_disable(struct brw_context *brw)
 370 {
 371    BEGIN_BATCH(3);
 372    OUT_BATCH(_3DSTATE_STREAMOUT << 16 | (3 - 2));
 373    OUT_BATCH(0);
 374    OUT_BATCH(0);
 375    ADVANCE_BATCH();
 376 }
 377
 378
 379 static void
 380 gen7_blorp_emit_sf_config(struct brw_context *brw,
 381                           const brw_blorp_params *params)
 382 {
 383    /* 3DSTATE_SF
 384     *
 385     * Disable ViewportTransformEnable (dw1.1)
 386     *
 387     * From the SandyBridge PRM, Volume 2, Part 1, Section 1.3, "3D
 388     * Primitives Overview":
 389     *     RECTLIST: Viewport Mapping must be DISABLED (as is typical with the
 390     *     use of screen- space coordinates).
 391     *
 392     * A solid rectangle must be rendered, so set FrontFaceFillMode (dw1.6:5)
 393     * and BackFaceFillMode (dw1.4:3) to SOLID(0).
 394     *
 395     * From the Sandy Bridge PRM, Volume 2, Part 1, Section
 396     * 6.4.1.1 3DSTATE_SF, Field FrontFaceFillMode:
 397     *     SOLID: Any triangle or rectangle object found to be front-facing
 398     *     is rendered as a solid object. This setting is required when
 399     *     (rendering rectangle (RECTLIST) objects.
 400     */
 401    {
 402       BEGIN_BATCH(7);
 403       OUT_BATCH(_3DSTATE_SF << 16 | (7 - 2));
 404       OUT_BATCH(params->depth_format <<
 405                 GEN7_SF_DEPTH_BUFFER_SURFACE_FORMAT_SHIFT);
 406       OUT_BATCH(params->dst.num_samples > 1 ? GEN6_SF_MSRAST_ON_PATTERN : 0);
 407       OUT_BATCH(0);
 408       OUT_BATCH(0);
 409       OUT_BATCH(0);
 410       OUT_BATCH(0);
 411       ADVANCE_BATCH();
 412    }
 413
 414    /* 3DSTATE_SBE */
 415    {
 416       BEGIN_BATCH(14);
 417       OUT_BATCH(_3DSTATE_SBE << 16 | (14 - 2));
 418       OUT_BATCH(GEN7_SBE_SWIZZLE_ENABLE |
 419                 params->num_varyings << GEN7_SBE_NUM_OUTPUTS_SHIFT |
 420                 1 << GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT |
 421                 BRW_SF_URB_ENTRY_READ_OFFSET <<
 422                    GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT);
 423       for (int i = 0; i < 12; ++i)
 424          OUT_BATCH(0);
 425       ADVANCE_BATCH();
 426    }
 427 }
 428
 429
 430 /**
 431  * Disable thread dispatch (dw5.19) and enable the HiZ op.
 432  */
 433 static void
 434 gen7_blorp_emit_wm_config(struct brw_context *brw,
 435                           const brw_blorp_params *params,
 436                           brw_blorp_prog_data *prog_data)
 437 {
 438    uint32_t dw1 = 0, dw2 = 0;
 439
 440    switch (params->hiz_op) {
 441    case GEN6_HIZ_OP_DEPTH_CLEAR:
 442       dw1 |= GEN7_WM_DEPTH_CLEAR;
 443       break;
 444    case GEN6_HIZ_OP_DEPTH_RESOLVE:
 445       dw1 |= GEN7_WM_DEPTH_RESOLVE;
 446       break;
 447    case GEN6_HIZ_OP_HIZ_RESOLVE:
 448       dw1 |= GEN7_WM_HIERARCHICAL_DEPTH_RESOLVE;
 449       break;
 450    case GEN6_HIZ_OP_NONE:
 451       break;
 452    default:
 453       unreachable("not reached");
 454    }
 455    dw1 |= GEN7_WM_LINE_AA_WIDTH_1_0;
 456    dw1 |= GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5;
 457    dw1 |= 0 << GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT; /* No interp */
 458    if (params->use_wm_prog) {
 459       dw1 |= GEN7_WM_KILL_ENABLE; /* TODO: temporarily smash on */
 460       dw1 |= GEN7_WM_DISPATCH_ENABLE; /* We are rendering */
 461    }
 462
 463       if (params->dst.num_samples > 1) {
 464          dw1 |= GEN7_WM_MSRAST_ON_PATTERN;
 465          if (prog_data && prog_data->persample_msaa_dispatch)
 466             dw2 |= GEN7_WM_MSDISPMODE_PERSAMPLE;
 467          else
 468             dw2 |= GEN7_WM_MSDISPMODE_PERPIXEL;
 469       } else {
 470          dw1 |= GEN7_WM_MSRAST_OFF_PIXEL;
 471          dw2 |= GEN7_WM_MSDISPMODE_PERSAMPLE;
 472       }
 473
 474    BEGIN_BATCH(3);
 475    OUT_BATCH(_3DSTATE_WM << 16 | (3 - 2));
 476    OUT_BATCH(dw1);
 477    OUT_BATCH(dw2);
 478    ADVANCE_BATCH();
 479 }
 480
 481
 482 /**
 483  * 3DSTATE_PS
 484  *
 485  * Pixel shader dispatch is disabled above in 3DSTATE_WM, dw1.29. Despite
 486  * that, thread dispatch info must still be specified.
 487  *     - Maximum Number of Threads (dw4.24:31) must be nonzero, as the
 488  *       valid range for this field is [0x3, 0x2f].
 489  *     - A dispatch mode must be given; that is, at least one of the
 490  *       "N Pixel Dispatch Enable" (N=8,16,32) fields must be set. This was
 491  *       discovered through simulator error messages.
 492  */
 493 static void
 494 gen7_blorp_emit_ps_config(struct brw_context *brw,
 495                           const brw_blorp_params *params,
 496                           uint32_t prog_offset,
 497                           brw_blorp_prog_data *prog_data)
 498 {
 499    uint32_t dw2, dw4, dw5;
 500    const int max_threads_shift = brw->is_haswell ?
 501       HSW_PS_MAX_THREADS_SHIFT : IVB_PS_MAX_THREADS_SHIFT;
 502
 503    dw2 = dw4 = dw5 = 0;
 504    dw4 |= (brw->max_wm_threads - 1) << max_threads_shift;
 505
 506    /* If there's a WM program, we need to do 16-pixel dispatch since that's
 507     * what the program is compiled for.  If there isn't, then it shouldn't
 508     * matter because no program is actually being run.  However, the hardware
 509     * gets angry if we don't enable at least one dispatch mode, so just enable
 510     * 16-pixel dispatch unconditionally.
 511     */
 512    dw4 |= GEN7_PS_16_DISPATCH_ENABLE;
 513
 514    if (brw->is_haswell)
 515       dw4 |= SET_FIELD(1, HSW_PS_SAMPLE_MASK); /* 1 sample for now */
 516    if (params->use_wm_prog) {
 517       dw2 |= 1 << GEN7_PS_SAMPLER_COUNT_SHIFT; /* Up to 4 samplers */
 518       dw4 |= GEN7_PS_PUSH_CONSTANT_ENABLE;
 519       dw5 |= prog_data->first_curbe_grf << GEN7_PS_DISPATCH_START_GRF_SHIFT_0;
 520    }
 521
 522    BEGIN_BATCH(8);
 523    OUT_BATCH(_3DSTATE_PS << 16 | (8 - 2));
 524    OUT_BATCH(params->use_wm_prog ? prog_offset : 0);
 525    OUT_BATCH(dw2);
 526    OUT_BATCH(0);
 527    OUT_BATCH(dw4);
 528    OUT_BATCH(dw5);
 529    OUT_BATCH(0);
 530    OUT_BATCH(0);
 531    ADVANCE_BATCH();
 532 }
 533
 534
 535 static void
 536 gen7_blorp_emit_binding_table_pointers_ps(struct brw_context *brw,
 537                                           uint32_t wm_bind_bo_offset)
 538 {
 539    BEGIN_BATCH(2);
 540    OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_PS << 16 | (2 - 2));
 541    OUT_BATCH(wm_bind_bo_offset);
 542    ADVANCE_BATCH();
 543 }
 544
 545
 546 static void
 547 gen7_blorp_emit_sampler_state_pointers_ps(struct brw_context *brw,
 548                                           uint32_t sampler_offset)
 549 {
 550    BEGIN_BATCH(2);
 551    OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS_PS << 16 | (2 - 2));
 552    OUT_BATCH(sampler_offset);
 553    ADVANCE_BATCH();
 554 }
 555
 556
 557 static void
 558 gen7_blorp_emit_constant_ps(struct brw_context *brw,
 559                             uint32_t wm_push_const_offset)
 560 {
 561    const uint8_t mocs = GEN7_MOCS_L3;
 562
 563    /* Make sure the push constants fill an exact integer number of
 564     * registers.
 565     */
 566    assert(sizeof(brw_blorp_wm_push_constants) % 32 == 0);
 567
 568    /* There must be at least one register worth of push constant data. */
 569    assert(BRW_BLORP_NUM_PUSH_CONST_REGS > 0);
 570
 571    /* Enable push constant buffer 0. */
 572    BEGIN_BATCH(7);
 573    OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 |
 574              (7 - 2));
 575    OUT_BATCH(BRW_BLORP_NUM_PUSH_CONST_REGS);
 576    OUT_BATCH(0);
 577    OUT_BATCH(wm_push_const_offset | mocs);
 578    OUT_BATCH(0);
 579    OUT_BATCH(0);
 580    OUT_BATCH(0);
 581    ADVANCE_BATCH();
 582 }
 583
 584 static void
 585 gen7_blorp_emit_constant_ps_disable(struct brw_context *brw)
 586 {
 587    BEGIN_BATCH(7);
 588    OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 | (7 - 2));
 589    OUT_BATCH(0);
 590    OUT_BATCH(0);
 591    OUT_BATCH(0);
 592    OUT_BATCH(0);
 593    OUT_BATCH(0);
 594    OUT_BATCH(0);
 595    ADVANCE_BATCH();
 596 }
 597
 598 static void
 599 gen7_blorp_emit_depth_stencil_config(struct brw_context *brw,
 600                                      const brw_blorp_params *params)
 601 {
 602    const uint8_t mocs = GEN7_MOCS_L3;
 603    uint32_t surfwidth, surfheight;
 604    uint32_t surftype;
 605    unsigned int depth = MAX2(params->depth.mt->logical_depth0, 1);
 606    unsigned int min_array_element;
 607    GLenum gl_target = params->depth.mt->target;
 608    unsigned int lod;
 609
 610    switch (gl_target) {
 611    case GL_TEXTURE_CUBE_MAP_ARRAY:
 612    case GL_TEXTURE_CUBE_MAP:
 613       /* The PRM claims that we should use BRW_SURFACE_CUBE for this
 614        * situation, but experiments show that gl_Layer doesn't work when we do
 615        * this.  So we use BRW_SURFACE_2D, since for rendering purposes this is
 616        * equivalent.
 617        */
 618       surftype = BRW_SURFACE_2D;
 619       depth *= 6;
 620       break;
 621    default:
 622       surftype = translate_tex_target(gl_target);
 623       break;
 624    }
 625
 626    min_array_element = params->depth.layer;
 627    if (params->depth.mt->num_samples > 1) {
 628       /* Convert physical layer to logical layer. */
 629       min_array_element /= params->depth.mt->num_samples;
 630    }
 631
 632    lod = params->depth.level - params->depth.mt->first_level;
 633
 634    if (params->hiz_op != GEN6_HIZ_OP_NONE && lod == 0) {
 635       /* HIZ ops for lod 0 may set the width & height a little
 636        * larger to allow the fast depth clear to fit the hardware
 637        * alignment requirements. (8x4)
 638        */
 639       surfwidth = params->depth.width;
 640       surfheight = params->depth.height;
 641    } else {
 642       surfwidth = params->depth.mt->logical_width0;
 643       surfheight = params->depth.mt->logical_height0;
 644    }
 645
 646    /* 3DSTATE_DEPTH_BUFFER */
 647    {
 648       brw_emit_depth_stall_flushes(brw);
 649
 650       BEGIN_BATCH(7);
 651       OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
 652       OUT_BATCH((params->depth.mt->pitch - 1) |
 653                 params->depth_format << 18 |
 654                 1 << 22 | /* hiz enable */
 655                 1 << 28 | /* depth write */
 656                 surftype << 29);
 657       OUT_RELOC(params->depth.mt->bo,
 658                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 659                 0);
 660       OUT_BATCH((surfwidth - 1) << 4 |
 661                 (surfheight - 1) << 18 |
 662                 lod);
 663       OUT_BATCH(((depth - 1) << 21) |
 664                 (min_array_element << 10) |
 665                 mocs);
 666       OUT_BATCH(0);
 667       OUT_BATCH((depth - 1) << 21);
 668       ADVANCE_BATCH();
 669    }
 670
 671    /* 3DSTATE_HIER_DEPTH_BUFFER */
 672    {
 673       struct intel_miptree_aux_buffer *hiz_buf = params->depth.mt->hiz_buf;
 674
 675       BEGIN_BATCH(3);
 676       OUT_BATCH((GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2));
 677       OUT_BATCH((mocs << 25) |
 678                 (hiz_buf->pitch - 1));
 679       OUT_RELOC(hiz_buf->bo,
 680                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 681                 0);
 682       ADVANCE_BATCH();
 683    }
 684
 685    /* 3DSTATE_STENCIL_BUFFER */
 686    {
 687       BEGIN_BATCH(3);
 688       OUT_BATCH((GEN7_3DSTATE_STENCIL_BUFFER << 16) | (3 - 2));
 689       OUT_BATCH(0);
 690       OUT_BATCH(0);
 691       ADVANCE_BATCH();
 692    }
 693 }
 694
 695
 696 static void
 697 gen7_blorp_emit_depth_disable(struct brw_context *brw)
 698 {
 699    brw_emit_depth_stall_flushes(brw);
 700
 701    BEGIN_BATCH(7);
 702    OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
 703    OUT_BATCH(BRW_DEPTHFORMAT_D32_FLOAT << 18 | (BRW_SURFACE_NULL << 29));
 704    OUT_BATCH(0);
 705    OUT_BATCH(0);
 706    OUT_BATCH(0);
 707    OUT_BATCH(0);
 708    OUT_BATCH(0);
 709    ADVANCE_BATCH();
 710
 711    BEGIN_BATCH(3);
 712    OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (3 - 2));
 713    OUT_BATCH(0);
 714    OUT_BATCH(0);
 715    ADVANCE_BATCH();
 716
 717    BEGIN_BATCH(3);
 718    OUT_BATCH(GEN7_3DSTATE_STENCIL_BUFFER << 16 | (3 - 2));
 719    OUT_BATCH(0);
 720    OUT_BATCH(0);
 721    ADVANCE_BATCH();
 722 }
 723
 724
 725 /* 3DSTATE_CLEAR_PARAMS
 726  *
 727  * From the Ivybridge PRM, Volume 2 Part 1, Section 11.5.5.4
 728  * 3DSTATE_CLEAR_PARAMS:
 729  *    3DSTATE_CLEAR_PARAMS must always be programmed in the along
 730  *    with the other Depth/Stencil state commands(i.e.  3DSTATE_DEPTH_BUFFER,
 731  *    3DSTATE_STENCIL_BUFFER, or 3DSTATE_HIER_DEPTH_BUFFER).
 732  */
 733 static void
 734 gen7_blorp_emit_clear_params(struct brw_context *brw,
 735                              const brw_blorp_params *params)
 736 {
 737    BEGIN_BATCH(3);
 738    OUT_BATCH(GEN7_3DSTATE_CLEAR_PARAMS << 16 | (3 - 2));
 739    OUT_BATCH(params->depth.mt ? params->depth.mt->depth_clear_value : 0);
 740    OUT_BATCH(GEN7_DEPTH_CLEAR_VALID);
 741    ADVANCE_BATCH();
 742 }
 743
 744
 745 /* 3DPRIMITIVE */
 746 static void
 747 gen7_blorp_emit_primitive(struct brw_context *brw,
 748                           const brw_blorp_params *params)
 749 {
 750    BEGIN_BATCH(7);
 751    OUT_BATCH(CMD_3D_PRIM << 16 | (7 - 2));
 752    OUT_BATCH(GEN7_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL |
 753              _3DPRIM_RECTLIST);
 754    OUT_BATCH(3); /* vertex count per instance */
 755    OUT_BATCH(0);
 756    OUT_BATCH(params->num_layers); /* instance count */
 757    OUT_BATCH(0);
 758    OUT_BATCH(0);
 759    ADVANCE_BATCH();
 760 }
 761
 762
 763 /**
 764  * \copydoc gen6_blorp_exec()
 765  */
 766 void
 767 gen7_blorp_exec(struct brw_context *brw,
 768                 const brw_blorp_params *params)
 769 {
 770    if (brw->gen >= 8)
 771       return;
 772
 773    brw_blorp_prog_data *prog_data = NULL;
 774    uint32_t cc_blend_state_offset = 0;
 775    uint32_t cc_state_offset = 0;
 776    uint32_t depthstencil_offset;
 777    uint32_t wm_push_const_offset = 0;
 778    uint32_t wm_bind_bo_offset = 0;
 779    uint32_t sampler_offset = 0;
 780
 781    uint32_t prog_offset = params->get_wm_prog(brw, &prog_data);
 782    gen6_emit_3dstate_multisample(brw, params->dst.num_samples);
 783    gen6_emit_3dstate_sample_mask(brw,
 784                                  params->dst.num_samples > 1 ?
 785                                  (1 << params->dst.num_samples) - 1 : 1);
 786    gen6_blorp_emit_state_base_address(brw, params);
 787    gen6_blorp_emit_vertices(brw, params);
 788    gen7_blorp_emit_urb_config(brw);
 789    if (params->use_wm_prog) {
 790       cc_blend_state_offset = gen6_blorp_emit_blend_state(brw, params);
 791       cc_state_offset = gen6_blorp_emit_cc_state(brw);
 792       gen7_blorp_emit_blend_state_pointer(brw, cc_blend_state_offset);
 793       gen7_blorp_emit_cc_state_pointer(brw, cc_state_offset);
 794    }
 795    depthstencil_offset = gen6_blorp_emit_depth_stencil_state(brw, params);
 796    gen7_blorp_emit_depth_stencil_state_pointers(brw, depthstencil_offset);
 797    if (brw->use_resource_streamer)
 798       gen7_disable_hw_binding_tables(brw);
 799    if (params->use_wm_prog) {
 800       uint32_t wm_surf_offset_renderbuffer;
 801       uint32_t wm_surf_offset_texture = 0;
 802       wm_push_const_offset = gen6_blorp_emit_wm_constants(brw, params);
 803       intel_miptree_used_for_rendering(params->dst.mt);
 804       wm_surf_offset_renderbuffer =
 805          gen7_blorp_emit_surface_state(brw, &params->dst,
 806                                        I915_GEM_DOMAIN_RENDER,
 807                                        I915_GEM_DOMAIN_RENDER,
 808                                        true /* is_render_target */);
 809       if (params->src.mt) {
 810          wm_surf_offset_texture =
 811             gen7_blorp_emit_surface_state(brw, &params->src,
 812                                           I915_GEM_DOMAIN_SAMPLER, 0,
 813                                           false /* is_render_target */);
 814       }
 815       wm_bind_bo_offset =
 816          gen6_blorp_emit_binding_table(brw,
 817                                        wm_surf_offset_renderbuffer,
 818                                        wm_surf_offset_texture);
 819       sampler_offset =
 820          gen6_blorp_emit_sampler_state(brw, BRW_MAPFILTER_LINEAR, 0, true);
 821    }
 822    gen7_blorp_emit_vs_disable(brw);
 823    gen7_blorp_emit_hs_disable(brw);
 824    gen7_blorp_emit_te_disable(brw);
 825    gen7_blorp_emit_ds_disable(brw);
 826    gen7_blorp_emit_gs_disable(brw);
 827    gen7_blorp_emit_streamout_disable(brw);
 828    gen6_blorp_emit_clip_disable(brw);
 829    gen7_blorp_emit_sf_config(brw, params);
 830    gen7_blorp_emit_wm_config(brw, params, prog_data);
 831    if (params->use_wm_prog) {
 832       gen7_blorp_emit_binding_table_pointers_ps(brw, wm_bind_bo_offset);
 833       gen7_blorp_emit_sampler_state_pointers_ps(brw, sampler_offset);
 834       gen7_blorp_emit_constant_ps(brw, wm_push_const_offset);
 835    } else {
 836       gen7_blorp_emit_constant_ps_disable(brw);
 837    }
 838    gen7_blorp_emit_ps_config(brw, params, prog_offset, prog_data);
 839    gen7_blorp_emit_cc_viewport(brw);
 840
 841    if (params->depth.mt)
 842       gen7_blorp_emit_depth_stencil_config(brw, params);
 843    else
 844       gen7_blorp_emit_depth_disable(brw);
 845    gen7_blorp_emit_clear_params(brw, params);
 846    gen6_blorp_emit_drawing_rectangle(brw, params);
 847    gen7_blorp_emit_primitive(brw, params);
 848 }