src/mesa/drivers/dri/i965/gen7_cs_state.c

   1 /*
   2  * Copyright © 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "util/ralloc.h"
  25 #include "brw_context.h"
  26 #include "brw_cs.h"
  27 #include "brw_eu.h"
  28 #include "brw_wm.h"
  29 #include "brw_shader.h"
  30 #include "intel_mipmap_tree.h"
  31 #include "intel_batchbuffer.h"
  32 #include "brw_state.h"
  33 #include "program/prog_statevars.h"
  34 #include "compiler/glsl/ir_uniform.h"
  35
  36 static void
  37 brw_upload_cs_state(struct brw_context *brw)
  38 {
  39    if (!brw->cs.prog_data)
  40       return;
  41
  42    uint32_t offset;
  43    uint32_t *desc = (uint32_t*) brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
  44                                                 8 * 4, 64, &offset);
  45    struct brw_stage_state *stage_state = &brw->cs.base;
  46    struct brw_cs_prog_data *cs_prog_data = brw->cs.prog_data;
  47    struct brw_stage_prog_data *prog_data = &cs_prog_data->base;
  48    const struct brw_device_info *devinfo = brw->intelScreen->devinfo;
  49
  50    if (INTEL_DEBUG & DEBUG_SHADER_TIME) {
  51       brw_emit_buffer_surface_state(
  52          brw, &stage_state->surf_offset[
  53                  prog_data->binding_table.shader_time_start],
  54          brw->shader_time.bo, 0, BRW_SURFACEFORMAT_RAW,
  55          brw->shader_time.bo->size, 1, true);
  56    }
  57
  58    uint32_t *bind = (uint32_t*) brw_state_batch(brw, AUB_TRACE_BINDING_TABLE,
  59                                             prog_data->binding_table.size_bytes,
  60                                             32, &stage_state->bind_bo_offset);
  61
  62    uint32_t dwords = brw->gen < 8 ? 8 : 9;
  63    BEGIN_BATCH(dwords);
  64    OUT_BATCH(MEDIA_VFE_STATE << 16 | (dwords - 2));
  65
  66    if (prog_data->total_scratch) {
  67       if (brw->gen >= 8) {
  68          /* Broadwell's Per Thread Scratch Space is in the range [0, 11]
  69           * where 0 = 1k, 1 = 2k, 2 = 4k, ..., 11 = 2M.
  70           */
  71          OUT_RELOC64(stage_state->scratch_bo,
  72                      I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
  73                      ffs(stage_state->per_thread_scratch) - 11);
  74       } else if (brw->is_haswell) {
  75          /* Haswell's Per Thread Scratch Space is in the range [0, 10]
  76           * where 0 = 2k, 1 = 4k, 2 = 8k, ..., 10 = 2M.
  77           */
  78          OUT_RELOC(stage_state->scratch_bo,
  79                    I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
  80                    ffs(stage_state->per_thread_scratch) - 12);
  81       } else {
  82          /* Earlier platforms use the range [0, 11] to mean [1kB, 12kB]
  83           * where 0 = 1kB, 1 = 2kB, 2 = 3kB, ..., 11 = 12kB.
  84           */
  85          OUT_RELOC(stage_state->scratch_bo,
  86                    I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
  87                    stage_state->per_thread_scratch / 1024 - 1);
  88       }
  89    } else {
  90       OUT_BATCH(0);
  91       if (brw->gen >= 8)
  92          OUT_BATCH(0);
  93    }
  94
  95    const uint32_t vfe_num_urb_entries = brw->gen >= 8 ? 2 : 0;
  96    const uint32_t vfe_gpgpu_mode =
  97       brw->gen == 7 ? SET_FIELD(1, GEN7_MEDIA_VFE_STATE_GPGPU_MODE) : 0;
  98    const uint32_t subslices = MAX2(brw->intelScreen->subslice_total, 1);
  99    OUT_BATCH(SET_FIELD(brw->max_cs_threads * subslices - 1,
 100                        MEDIA_VFE_STATE_MAX_THREADS) |
 101              SET_FIELD(vfe_num_urb_entries, MEDIA_VFE_STATE_URB_ENTRIES) |
 102              SET_FIELD(1, MEDIA_VFE_STATE_RESET_GTW_TIMER) |
 103              SET_FIELD(1, MEDIA_VFE_STATE_BYPASS_GTW) |
 104              vfe_gpgpu_mode);
 105
 106    OUT_BATCH(0);
 107    const uint32_t vfe_urb_allocation = brw->gen >= 8 ? 2 : 0;
 108
 109    /* We are uploading duplicated copies of push constant uniforms for each
 110     * thread. Although the local id data needs to vary per thread, it won't
 111     * change for other uniform data. Unfortunately this duplication is
 112     * required for gen7. As of Haswell, this duplication can be avoided, but
 113     * this older mechanism with duplicated data continues to work.
 114     *
 115     * FINISHME: As of Haswell, we could make use of the
 116     * INTERFACE_DESCRIPTOR_DATA "Cross-Thread Constant Data Read Length" field
 117     * to only store one copy of uniform data.
 118     *
 119     * FINISHME: Broadwell adds a new alternative "Indirect Payload Storage"
 120     * which is described in the GPGPU_WALKER command and in the Broadwell PRM
 121     * Volume 7: 3D Media GPGPU, under Media GPGPU Pipeline => Mode of
 122     * Operations => GPGPU Mode => Indirect Payload Storage.
 123     *
 124     * Note: The constant data is built in brw_upload_cs_push_constants below.
 125     */
 126    const uint32_t vfe_curbe_allocation =
 127       ALIGN(cs_prog_data->push.per_thread.regs * cs_prog_data->threads +
 128             cs_prog_data->push.cross_thread.regs, 2);
 129    OUT_BATCH(SET_FIELD(vfe_urb_allocation, MEDIA_VFE_STATE_URB_ALLOC) |
 130              SET_FIELD(vfe_curbe_allocation, MEDIA_VFE_STATE_CURBE_ALLOC));
 131    OUT_BATCH(0);
 132    OUT_BATCH(0);
 133    OUT_BATCH(0);
 134    ADVANCE_BATCH();
 135
 136    if (cs_prog_data->push.total.size > 0) {
 137       BEGIN_BATCH(4);
 138       OUT_BATCH(MEDIA_CURBE_LOAD << 16 | (4 - 2));
 139       OUT_BATCH(0);
 140       OUT_BATCH(ALIGN(cs_prog_data->push.total.size, 64));
 141       OUT_BATCH(stage_state->push_const_offset);
 142       ADVANCE_BATCH();
 143    }
 144
 145    /* BRW_NEW_SURFACES and BRW_NEW_*_CONSTBUF */
 146    memcpy(bind, stage_state->surf_offset,
 147           prog_data->binding_table.size_bytes);
 148
 149    memset(desc, 0, 8 * 4);
 150
 151    int dw = 0;
 152    desc[dw++] = brw->cs.base.prog_offset;
 153    if (brw->gen >= 8)
 154       desc[dw++] = 0; /* Kernel Start Pointer High */
 155    desc[dw++] = 0;
 156    desc[dw++] = stage_state->sampler_offset |
 157       ((stage_state->sampler_count + 3) / 4);
 158    desc[dw++] = stage_state->bind_bo_offset;
 159    desc[dw++] = SET_FIELD(cs_prog_data->push.per_thread.regs,
 160                           MEDIA_CURBE_READ_LENGTH);
 161    const uint32_t media_threads =
 162       brw->gen >= 8 ?
 163       SET_FIELD(cs_prog_data->threads, GEN8_MEDIA_GPGPU_THREAD_COUNT) :
 164       SET_FIELD(cs_prog_data->threads, MEDIA_GPGPU_THREAD_COUNT);
 165    assert(cs_prog_data->threads <= brw->max_cs_threads);
 166
 167    const uint32_t slm_size =
 168       encode_slm_size(devinfo->gen, prog_data->total_shared);
 169
 170    desc[dw++] =
 171       SET_FIELD(cs_prog_data->uses_barrier, MEDIA_BARRIER_ENABLE) |
 172       SET_FIELD(slm_size, MEDIA_SHARED_LOCAL_MEMORY_SIZE) |
 173       media_threads;
 174
 175    desc[dw++] =
 176       SET_FIELD(cs_prog_data->push.cross_thread.regs, CROSS_THREAD_READ_LENGTH);
 177
 178    BEGIN_BATCH(4);
 179    OUT_BATCH(MEDIA_INTERFACE_DESCRIPTOR_LOAD << 16 | (4 - 2));
 180    OUT_BATCH(0);
 181    OUT_BATCH(8 * 4);
 182    OUT_BATCH(offset);
 183    ADVANCE_BATCH();
 184 }
 185
 186 const struct brw_tracked_state brw_cs_state = {
 187    .dirty = {
 188       .mesa = _NEW_PROGRAM_CONSTANTS,
 189       .brw = BRW_NEW_BATCH |
 190              BRW_NEW_BLORP |
 191              BRW_NEW_CS_PROG_DATA |
 192              BRW_NEW_PUSH_CONSTANT_ALLOCATION |
 193              BRW_NEW_SAMPLER_STATE_TABLE |
 194              BRW_NEW_SURFACES,
 195    },
 196    .emit = brw_upload_cs_state
 197 };
 198
 199
 200 /**
 201  * Creates a region containing the push constants for the CS on gen7+.
 202  *
 203  * Push constants are constant values (such as GLSL uniforms) that are
 204  * pre-loaded into a shader stage's register space at thread spawn time.
 205  *
 206  * For other stages, see brw_curbe.c:brw_upload_constant_buffer for the
 207  * equivalent gen4/5 code and gen6_vs_state.c:gen6_upload_push_constants for
 208  * gen6+.
 209  */
 210 static void
 211 brw_upload_cs_push_constants(struct brw_context *brw,
 212                              const struct gl_program *prog,
 213                              const struct brw_cs_prog_data *cs_prog_data,
 214                              struct brw_stage_state *stage_state,
 215                              enum aub_state_struct_type type)
 216 {
 217    struct gl_context *ctx = &brw->ctx;
 218    const struct brw_stage_prog_data *prog_data =
 219       (struct brw_stage_prog_data*) cs_prog_data;
 220
 221    /* Updates the ParamaterValues[i] pointers for all parameters of the
 222     * basic type of PROGRAM_STATE_VAR.
 223     */
 224    /* XXX: Should this happen somewhere before to get our state flag set? */
 225    _mesa_load_state_parameters(ctx, prog->Parameters);
 226
 227    if (cs_prog_data->push.total.size == 0) {
 228       stage_state->push_const_size = 0;
 229       return;
 230    }
 231
 232
 233    gl_constant_value *param = (gl_constant_value*)
 234       brw_state_batch(brw, type, ALIGN(cs_prog_data->push.total.size, 64),
 235                       64, &stage_state->push_const_offset);
 236    assert(param);
 237
 238    STATIC_ASSERT(sizeof(gl_constant_value) == sizeof(float));
 239
 240    if (cs_prog_data->push.cross_thread.size > 0) {
 241       gl_constant_value *param_copy = param;
 242       assert(cs_prog_data->thread_local_id_index < 0 ||
 243              cs_prog_data->thread_local_id_index >=
 244                 cs_prog_data->push.cross_thread.dwords);
 245       for (unsigned i = 0;
 246            i < cs_prog_data->push.cross_thread.dwords;
 247            i++) {
 248          param_copy[i] = *prog_data->param[i];
 249       }
 250    }
 251
 252    gl_constant_value thread_id;
 253    if (cs_prog_data->push.per_thread.size > 0) {
 254       for (unsigned t = 0; t < cs_prog_data->threads; t++) {
 255          unsigned dst =
 256             8 * (cs_prog_data->push.per_thread.regs * t +
 257                  cs_prog_data->push.cross_thread.regs);
 258          unsigned src = cs_prog_data->push.cross_thread.dwords;
 259          for ( ; src < prog_data->nr_params; src++, dst++) {
 260             if (src != cs_prog_data->thread_local_id_index)
 261                param[dst] = *prog_data->param[src];
 262             else {
 263                thread_id.u = t * cs_prog_data->simd_size;
 264                param[dst] = thread_id;
 265             }
 266          }
 267       }
 268    }
 269
 270    stage_state->push_const_size =
 271       cs_prog_data->push.cross_thread.regs +
 272       cs_prog_data->push.per_thread.regs;
 273 }
 274
 275
 276 static void
 277 gen7_upload_cs_push_constants(struct brw_context *brw)
 278 {
 279    struct brw_stage_state *stage_state = &brw->cs.base;
 280
 281    /* BRW_NEW_COMPUTE_PROGRAM */
 282    const struct brw_compute_program *cp =
 283       (struct brw_compute_program *) brw->compute_program;
 284
 285    if (cp) {
 286       /* CACHE_NEW_CS_PROG */
 287       struct brw_cs_prog_data *cs_prog_data = brw->cs.prog_data;
 288
 289       brw_upload_cs_push_constants(brw, &cp->program.Base, cs_prog_data,
 290                                    stage_state, AUB_TRACE_WM_CONSTANTS);
 291    }
 292 }
 293
 294 const struct brw_tracked_state gen7_cs_push_constants = {
 295    .dirty = {
 296       .mesa = _NEW_PROGRAM_CONSTANTS,
 297       .brw = BRW_NEW_BATCH |
 298              BRW_NEW_BLORP |
 299              BRW_NEW_COMPUTE_PROGRAM |
 300              BRW_NEW_PUSH_CONSTANT_ALLOCATION,
 301    },
 302    .emit = gen7_upload_cs_push_constants,
 303 };
 304
 305 /**
 306  * Creates a new CS constant buffer reflecting the current CS program's
 307  * constants, if needed by the CS program.
 308  */
 309 static void
 310 brw_upload_cs_pull_constants(struct brw_context *brw)
 311 {
 312    struct brw_stage_state *stage_state = &brw->cs.base;
 313
 314    /* BRW_NEW_COMPUTE_PROGRAM */
 315    struct brw_compute_program *cp =
 316       (struct brw_compute_program *) brw->compute_program;
 317
 318    /* BRW_NEW_CS_PROG_DATA */
 319    const struct brw_stage_prog_data *prog_data = &brw->cs.prog_data->base;
 320
 321    /* _NEW_PROGRAM_CONSTANTS */
 322    brw_upload_pull_constants(brw, BRW_NEW_SURFACES, &cp->program.Base,
 323                              stage_state, prog_data);
 324 }
 325
 326 const struct brw_tracked_state brw_cs_pull_constants = {
 327    .dirty = {
 328       .mesa = _NEW_PROGRAM_CONSTANTS,
 329       .brw = BRW_NEW_BATCH |
 330              BRW_NEW_BLORP |
 331              BRW_NEW_COMPUTE_PROGRAM |
 332              BRW_NEW_CS_PROG_DATA,
 333    },
 334    .emit = brw_upload_cs_pull_constants,
 335 };