Merge branch 'xa_branch'
[mesa.git] / src / mesa / drivers / dri / i965 / gen7_disable.c
1 /*
2 * Copyright © 2011 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "brw_context.h"
25 #include "brw_state.h"
26 #include "brw_defines.h"
27 #include "intel_batchbuffer.h"
28
29 static void
30 disable_stages(struct brw_context *brw)
31 {
32 struct intel_context *intel = &brw->intel;
33
34 assert(!brw->gs.prog_active);
35
36 /* Disable the Geometry Shader (GS) Unit */
37 BEGIN_BATCH(7);
38 OUT_BATCH(_3DSTATE_CONSTANT_GS << 16 | (7 - 2));
39 OUT_BATCH(0);
40 OUT_BATCH(0);
41 OUT_BATCH(0);
42 OUT_BATCH(0);
43 OUT_BATCH(0);
44 OUT_BATCH(0);
45 ADVANCE_BATCH();
46
47 BEGIN_BATCH(7);
48 OUT_BATCH(_3DSTATE_GS << 16 | (7 - 2));
49 OUT_BATCH(0); /* prog_bo */
50 OUT_BATCH((0 << GEN6_GS_SAMPLER_COUNT_SHIFT) |
51 (0 << GEN6_GS_BINDING_TABLE_ENTRY_COUNT_SHIFT));
52 OUT_BATCH(0); /* scratch space base offset */
53 OUT_BATCH((1 << GEN6_GS_DISPATCH_START_GRF_SHIFT) |
54 (0 << GEN6_GS_URB_READ_LENGTH_SHIFT) |
55 GEN7_GS_INCLUDE_VERTEX_HANDLES |
56 (0 << GEN6_GS_URB_ENTRY_READ_OFFSET_SHIFT));
57 OUT_BATCH((0 << GEN6_GS_MAX_THREADS_SHIFT) |
58 GEN6_GS_STATISTICS_ENABLE);
59 OUT_BATCH(0);
60 ADVANCE_BATCH();
61
62 BEGIN_BATCH(2);
63 OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_GS << 16 | (2 - 2));
64 OUT_BATCH(0);
65 ADVANCE_BATCH();
66
67 /* Disable the HS Unit */
68 BEGIN_BATCH(7);
69 OUT_BATCH(_3DSTATE_CONSTANT_HS << 16 | (7 - 2));
70 OUT_BATCH(0);
71 OUT_BATCH(0);
72 OUT_BATCH(0);
73 OUT_BATCH(0);
74 OUT_BATCH(0);
75 OUT_BATCH(0);
76 ADVANCE_BATCH();
77
78 BEGIN_BATCH(7);
79 OUT_BATCH(_3DSTATE_HS << 16 | (7 - 2));
80 OUT_BATCH(0);
81 OUT_BATCH(0);
82 OUT_BATCH(0);
83 OUT_BATCH(0);
84 OUT_BATCH(0);
85 OUT_BATCH(0);
86 ADVANCE_BATCH();
87
88 BEGIN_BATCH(2);
89 OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_HS << 16 | (2 - 2));
90 OUT_BATCH(0);
91 ADVANCE_BATCH();
92
93 /* Disable the TE */
94 BEGIN_BATCH(4);
95 OUT_BATCH(_3DSTATE_TE << 16 | (4 - 2));
96 OUT_BATCH(0);
97 OUT_BATCH(0);
98 OUT_BATCH(0);
99 ADVANCE_BATCH();
100
101 /* Disable the DS Unit */
102 BEGIN_BATCH(7);
103 OUT_BATCH(_3DSTATE_CONSTANT_DS << 16 | (7 - 2));
104 OUT_BATCH(0);
105 OUT_BATCH(0);
106 OUT_BATCH(0);
107 OUT_BATCH(0);
108 OUT_BATCH(0);
109 OUT_BATCH(0);
110 ADVANCE_BATCH();
111
112 BEGIN_BATCH(6);
113 OUT_BATCH(_3DSTATE_DS << 16 | (6 - 2));
114 OUT_BATCH(0);
115 OUT_BATCH(0);
116 OUT_BATCH(0);
117 OUT_BATCH(0);
118 OUT_BATCH(0);
119 ADVANCE_BATCH();
120
121 BEGIN_BATCH(2);
122 OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_DS << 16 | (2 - 2));
123 OUT_BATCH(0);
124 ADVANCE_BATCH();
125
126 /* Disable the SOL stage */
127 BEGIN_BATCH(3);
128 OUT_BATCH(_3DSTATE_STREAMOUT << 16 | (3 - 2));
129 OUT_BATCH(0);
130 OUT_BATCH(0);
131 ADVANCE_BATCH();
132 }
133
134 const struct brw_tracked_state gen7_disable_stages = {
135 .dirty = {
136 .mesa = 0,
137 .brw = BRW_NEW_BATCH,
138 .cache = 0,
139 },
140 .emit = disable_stages,
141 };